include/74xx_7xx.h

   1 /*
   2  * (C) Copyright 2001
   3  * Josh Huber, Mission Critical Linux, Inc. <huber@mclx.com>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * 74xx_7xx.h
  10  *
  11  * 74xx/7xx specific definitions
  12  */
  13
  14 #ifndef __MPC74XX_H__
  15 #define __MPC74XX_H__
  16
  17 /*----------------------------------------------------------------
  18  * Exception offsets (PowerPC standard)
  19  */
  20 #define EXC_OFF_SYS_RESET        0x0100      /* default system reset offset */
  21 #define _START_OFFSET           EXC_OFF_SYS_RESET
  22
  23 /*----------------------------------------------------------------
  24  * l2cr values
  25  */
  26 #define l2cr             1017
  27
  28 #define L2CR_L2E         0x80000000 /* bit 0 - enable */
  29 #define L2CR_L2PE        0x40000000 /* bit 1 - data parity */
  30 #define L2CR_L2SIZ_2M    0x00000000 /* bits 2-3 - 2MB, MPC7400 only! */
  31 #define L2CR_L2SIZ_1M    0x30000000 /* ... 1MB */
  32 #define L2CR_L2SIZ_HM    0x20000000 /* ... 512K */
  33 #define L2CR_L2SIZ_QM    0x10000000 /* ... 256k */
  34 #define L2CR_L2CLK_1     0x02000000 /* bits 4-6 clock ratio div 1 */
  35 #define L2CR_L2CLK_1_5   0x04000000 /* bits 4-6 clock ratio div 1.5 */
  36 #define L2CR_L2CLK_2     0x08000000 /* bits 4-6 clock ratio div 2 */
  37 #define L2CR_L2CLK_2_5   0x0a000000 /* bits 4-6 clock ratio div 2.5 */
  38 #define L2CR_L2CLK_3     0x0c000000 /* bits 4-6 clock ratio div 3 */
  39 #define L2CR_L2CLK_3_5   0x06000000 /* bits 4-6 clock ratio div 3.5 */
  40 #define L2CR_L2CLK_4     0x0e000000 /* bits 4-6 clock ratio div 4 */
  41 #define L2CR_L2RAM_BURST 0x01000000 /* bits 7-8 - burst SRAM */
  42 #define L2CR_DO          0x00400000 /* bit 9 - enable caching of instr. in L2 */
  43 #define L2CR_L2I         0x00200000 /* bit 10 - global invalidate bit */
  44 #define L2CR_L2CTL       0x00100000 /* bit 11 - l2 ram control */
  45 #define L2CR_L2WT        0x00080000 /* bit 12 - l2 write-through */
  46 #define L2CR_TS          0x00040000 /* bit 13 - test support on */
  47 #define L2CR_TS_OFF      -L2CR_TS   /* bit 13 - test support off */
  48 #define L2CR_L2OH_5      0x00000000 /* bits 14-15 - output hold time = short */
  49 #define L2CR_L2OH_1      0x00010000 /* bits 14-15 - output hold time = medium */
  50 #define L2CR_L2OH_INV    0x00020000 /* bits 14-15 - output hold time = long */
  51 #define L2CR_L2IP        0x00000001 /* global invalidate in progress */
  52
  53 #ifndef __ASSEMBLY__
  54 /* cpu ids we detect */
  55 typedef enum __cpu_t {
  56         CPU_740, CPU_750,
  57         CPU_740P, CPU_750P,
  58         CPU_745, CPU_755,
  59         CPU_750CX, CPU_750FX, CPU_750GX,
  60         CPU_7400,
  61         CPU_7410,
  62         CPU_7447A, CPU_7448,
  63         CPU_7450, CPU_7455, CPU_7457,
  64         CPU_UNKNOWN} cpu_t;
  65
  66 extern cpu_t get_cpu_type(void);
  67
  68 #define l1icache_enable icache_enable
  69
  70 void l2cache_enable(void);
  71 void l1dcache_enable(void);
  72
  73 static __inline__ unsigned long get_msr (void)
  74 {
  75         unsigned long msr;
  76         asm volatile("mfmsr %0" : "=r" (msr) :);
  77         return msr;
  78 }
  79
  80 static __inline__ void set_msr (unsigned long msr)
  81 {
  82         asm volatile("mtmsr %0" : : "r" (msr));
  83 }
  84
  85 static __inline__ unsigned long get_hid0 (void)
  86 {
  87         unsigned long hid0;
  88         asm volatile("mfspr %0, 1008" : "=r" (hid0) :);
  89         return hid0;
  90 }
  91
  92 static __inline__ unsigned long get_hid1 (void)
  93 {
  94         unsigned long hid1;
  95         asm volatile("mfspr %0, 1009" : "=r" (hid1) :);
  96         return hid1;
  97 }
  98
  99 static __inline__ void set_hid0 (unsigned long hid0)
 100 {
 101         asm volatile("mtspr 1008, %0" : : "r" (hid0));
 102 }
 103
 104 static __inline__ void set_hid1 (unsigned long hid1)
 105 {
 106         asm volatile("mtspr 1009, %0" : : "r" (hid1));
 107 }
 108
 109 #endif  /* __ASSEMBLY__ */
 110 #endif  /* __MPC74XX_H__ */