include/asm-arm/arch-a320/ftsmc020.h

   1 /*
   2  * (C) Copyright 2009 Faraday Technology
   3  * Po-Yu Chuang <ratbert@faraday-tech.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License as published by
   7  * the Free Software Foundation; either version 2 of the License, or
   8  * (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  18  */
  19
  20 /*
  21  * Static Memory Controller
  22  */
  23 #ifndef __FTSMC020_H
  24 #define __FTSMC020_H
  25
  26 #ifndef __ASSEMBLY__
  27
  28 struct ftsmc020 {
  29         struct {
  30                 unsigned int    cr;     /* 0x00, 0x08, 0x10, 0x18 */
  31                 unsigned int    tpr;    /* 0x04, 0x0c, 0x14, 0x1c */
  32         } bank[4];
  33         unsigned int    pad[8]; /* 0x20 - 0x3c */
  34         unsigned int    ssr;    /* 0x40 */
  35 };
  36
  37 void ftsmc020_init(void);
  38
  39 #endif /* __ASSEMBLY__ */
  40
  41 /*
  42  * Memory Bank Configuration Register
  43  */
  44 #define FTSMC020_BANK_ENABLE    (1 << 28)
  45 #define FTSMC020_BANK_BASE(x)   ((x) & 0x0fff1000)
  46
  47 #define FTSMC020_BANK_WPROT     (1 << 11)
  48
  49 #define FTSMC020_BANK_SIZE_32K  (0xb << 4)
  50 #define FTSMC020_BANK_SIZE_64K  (0xc << 4)
  51 #define FTSMC020_BANK_SIZE_128K (0xd << 4)
  52 #define FTSMC020_BANK_SIZE_256K (0xe << 4)
  53 #define FTSMC020_BANK_SIZE_512K (0xf << 4)
  54 #define FTSMC020_BANK_SIZE_1M   (0x0 << 4)
  55 #define FTSMC020_BANK_SIZE_2M   (0x1 << 4)
  56 #define FTSMC020_BANK_SIZE_4M   (0x2 << 4)
  57 #define FTSMC020_BANK_SIZE_8M   (0x3 << 4)
  58 #define FTSMC020_BANK_SIZE_16M  (0x4 << 4)
  59 #define FTSMC020_BANK_SIZE_32M  (0x5 << 4)
  60
  61 #define FTSMC020_BANK_MBW_8     (0x0 << 0)
  62 #define FTSMC020_BANK_MBW_16    (0x1 << 0)
  63 #define FTSMC020_BANK_MBW_32    (0x2 << 0)
  64
  65 /*
  66  * Memory Bank Timing Parameter Register
  67  */
  68 #define FTSMC020_TPR_ETRNA(x)   (((x) & 0xf) << 28)
  69 #define FTSMC020_TPR_EATI(x)    (((x) & 0xf) << 24)
  70 #define FTSMC020_TPR_RBE        (1 << 20)
  71 #define FTSMC020_TPR_AST(x)     (((x) & 0x3) << 18)
  72 #define FTSMC020_TPR_CTW(x)     (((x) & 0x3) << 16)
  73 #define FTSMC020_TPR_ATI(x)     (((x) & 0xf) << 12)
  74 #define FTSMC020_TPR_AT2(x)     (((x) & 0x3) << 8)
  75 #define FTSMC020_TPR_WTC(x)     (((x) & 0x3) << 6)
  76 #define FTSMC020_TPR_AHT(x)     (((x) & 0x3) << 4)
  77 #define FTSMC020_TPR_TRNA(x)    (((x) & 0xf) << 0)
  78
  79 #endif  /* __FTSMC020_H */