include/asm-arm/arch-arm1136/i2c.h

   1 /*
   2  * (C) Copyright 2004
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23 #ifndef _OMAP24XX_I2C_H_
  24 #define _OMAP24XX_I2C_H_
  25
  26 #define I2C_BASE                0x48070000
  27 #define I2C_BASE2               0x48072000 /* nothing hooked up on h4 */
  28
  29 #define I2C_REV                 (I2C_BASE + 0x00)
  30 #define I2C_IE                  (I2C_BASE + 0x04)
  31 #define I2C_STAT                (I2C_BASE + 0x08)
  32 #define I2C_IV                  (I2C_BASE + 0x0c)
  33 #define I2C_BUF                 (I2C_BASE + 0x14)
  34 #define I2C_CNT                 (I2C_BASE + 0x18)
  35 #define I2C_DATA                (I2C_BASE + 0x1c)
  36 #define I2C_CON                 (I2C_BASE + 0x24)
  37 #define I2C_OA                  (I2C_BASE + 0x28)
  38 #define I2C_SA                  (I2C_BASE + 0x2c)
  39 #define I2C_PSC                 (I2C_BASE + 0x30)
  40 #define I2C_SCLL                (I2C_BASE + 0x34)
  41 #define I2C_SCLH                (I2C_BASE + 0x38)
  42 #define I2C_SYSTEST             (I2C_BASE + 0x3c)
  43
  44 /* I2C masks */
  45
  46 /* I2C Interrupt Enable Register (I2C_IE): */
  47 #define I2C_IE_GC_IE    (1 << 5)
  48 #define I2C_IE_XRDY_IE  (1 << 4)        /* Transmit data ready interrupt enable */
  49 #define I2C_IE_RRDY_IE  (1 << 3)        /* Receive data ready interrupt enable */
  50 #define I2C_IE_ARDY_IE  (1 << 2)        /* Register access ready interrupt enable */
  51 #define I2C_IE_NACK_IE  (1 << 1)        /* No acknowledgment interrupt enable */
  52 #define I2C_IE_AL_IE    (1 << 0)        /* Arbitration lost interrupt enable */
  53
  54 /* I2C Status Register (I2C_STAT): */
  55
  56 #define I2C_STAT_SBD    (1 << 15)       /* Single byte data */
  57 #define I2C_STAT_BB     (1 << 12)       /* Bus busy */
  58 #define I2C_STAT_ROVR   (1 << 11)       /* Receive overrun */
  59 #define I2C_STAT_XUDF   (1 << 10)       /* Transmit underflow */
  60 #define I2C_STAT_AAS    (1 << 9)        /* Address as slave */
  61 #define I2C_STAT_GC     (1 << 5)
  62 #define I2C_STAT_XRDY   (1 << 4)        /* Transmit data ready */
  63 #define I2C_STAT_RRDY   (1 << 3)        /* Receive data ready */
  64 #define I2C_STAT_ARDY   (1 << 2)        /* Register access ready */
  65 #define I2C_STAT_NACK   (1 << 1)        /* No acknowledgment interrupt enable */
  66 #define I2C_STAT_AL     (1 << 0)        /* Arbitration lost interrupt enable */
  67
  68
  69 /* I2C Interrupt Code Register (I2C_INTCODE): */
  70
  71 #define I2C_INTCODE_MASK        7
  72 #define I2C_INTCODE_NONE        0
  73 #define I2C_INTCODE_AL          1       /* Arbitration lost */
  74 #define I2C_INTCODE_NAK         2       /* No acknowledgement/general call */
  75 #define I2C_INTCODE_ARDY        3       /* Register access ready */
  76 #define I2C_INTCODE_RRDY        4       /* Rcv data ready */
  77 #define I2C_INTCODE_XRDY        5       /* Xmit data ready */
  78
  79 /* I2C Buffer Configuration Register (I2C_BUF): */
  80
  81 #define I2C_BUF_RDMA_EN         (1 << 15)       /* Receive DMA channel enable */
  82 #define I2C_BUF_XDMA_EN         (1 << 7)        /* Transmit DMA channel enable */
  83
  84 /* I2C Configuration Register (I2C_CON): */
  85
  86 #define I2C_CON_EN      (1 << 15)       /* I2C module enable */
  87 #define I2C_CON_BE      (1 << 14)       /* Big endian mode */
  88 #define I2C_CON_STB     (1 << 11)       /* Start byte mode (master mode only) */
  89 #define I2C_CON_MST     (1 << 10)       /* Master/slave mode */
  90 #define I2C_CON_TRX     (1 << 9)        /* Transmitter/receiver mode (master mode only) */
  91 #define I2C_CON_XA      (1 << 8)        /* Expand address */
  92 #define I2C_CON_STP     (1 << 1)        /* Stop condition (master mode only) */
  93 #define I2C_CON_STT     (1 << 0)        /* Start condition (master mode only) */
  94
  95 /* I2C System Test Register (I2C_SYSTEST): */
  96
  97 #define I2C_SYSTEST_ST_EN       (1 << 15)       /* System test enable */
  98 #define I2C_SYSTEST_FREE        (1 << 14)       /* Free running mode (on breakpoint) */
  99 #define I2C_SYSTEST_TMODE_MASK  (3 << 12)       /* Test mode select */
 100 #define I2C_SYSTEST_TMODE_SHIFT (12)            /* Test mode select */
 101 #define I2C_SYSTEST_SCL_I       (1 << 3)        /* SCL line sense input value */
 102 #define I2C_SYSTEST_SCL_O       (1 << 2)        /* SCL line drive output value */
 103 #define I2C_SYSTEST_SDA_I       (1 << 1)        /* SDA line sense input value */
 104 #define I2C_SYSTEST_SDA_O       (1 << 0)        /* SDA line drive output value */
 105
 106 #endif