include/asm-arm/arch-arm720t/netarm_ser_module.h

   1 /*
   2  * linux/include/asm-arm/arch-netarm/netarm_ser_module.h
   3  *
   4  * Copyright (C) 2000 NETsilicon, Inc.
   5  * Copyright (C) 2000 Red Hat, Inc.
   6  *
   7  * This software is copyrighted by Red Hat. LICENSEE agrees that
   8  * it will not delete this copyright notice, trademarks or protective
   9  * notices from any copy made by LICENSEE.
  10  *
  11  * This software is provided "AS-IS" and any express or implied
  12  * warranties or conditions, including but not limited to any
  13  * implied warranties of merchantability and fitness for a particular
  14  * purpose regarding this software. In no event shall Red Hat
  15  * be liable for any indirect, consequential, or incidental damages,
  16  * loss of profits or revenue, loss of use or data, or interruption
  17  * of business, whether the alleged damages are labeled in contract,
  18  * tort, or indemnity.
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License as published by
  22  * the Free Software Foundation; either version 2 of the License, or
  23  * (at your option) any later version.
  24  *
  25  * You should have received a copy of the GNU General Public License
  26  * along with this program; if not, write to the Free Software
  27  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  28  *
  29  * author(s) : Joe deBlaquiere
  30  *             Clark Williams
  31  */
  32
  33 #ifndef __NETARM_SER_MODULE_REGISTERS_H
  34 #define __NETARM_SER_MODULE_REGISTERS_H
  35
  36 #ifndef __ASSEMBLER__
  37
  38 /* (--sub)#include "types.h" */
  39
  40 /* serial channel control structure */
  41 typedef struct {
  42   u32   ctrl_a;
  43   u32   ctrl_b;
  44   u32   status_a;
  45   u32   bitrate;
  46   u32   fifo;
  47   u32   rx_buf_timer;
  48   u32   rx_char_timer;
  49   u32   rx_match;
  50   u32   rx_match_mask;
  51   u32   ctrl_c;
  52   u32   status_b;
  53   u32   status_c;
  54   u32   fifo_last;
  55   u32   unused[3];
  56 } netarm_serial_channel_t;
  57
  58 #endif
  59
  60 /* SER unit register offsets */
  61
  62 /* #ifdef CONFIG_ARCH_NETARM */
  63 #define NETARM_SER_MODULE_BASE          (0xFFD00000)
  64 /* #else */
  65 /* extern serial_channel_t netarm_dummy_registers[]; */
  66 /* #define NETARM_SER_MODULE_BASE               (netarm_dummy_registers) */
  67 /* #ifndef NETARM_XTAL_FREQ */
  68 /* #define NETARM_XTAL_FREQ                18432000 */
  69 /* #endif */
  70 /* #endif */
  71
  72 /* calculate the sysclk value from the pll setting */
  73 #define NETARM_PLLED_SYSCLK_FREQ        (( NETARM_XTAL_FREQ / 5 ) * \
  74                                          ( NETARM_PLL_COUNT_VAL + 3 ))
  75
  76 #define get_serial_channel(c) (&(((netarm_serial_channel_t *)NETARM_SER_MODULE_BASE)[c]))
  77
  78 #define NETARM_SER_CH1_CTRL_A           (0x00)
  79 #define NETARM_SER_CH1_CTRL_B           (0x04)
  80 #define NETARM_SER_CH1_STATUS_A         (0x08)
  81 #define NETARM_SER_CH1_BITRATE          (0x0C)
  82 #define NETARM_SER_CH1_FIFO             (0x10)
  83 #define NETARM_SER_CH1_RX_BUF_TMR       (0x14)
  84 #define NETARM_SER_CH1_RX_CHAR_TMR      (0x18)
  85 #define NETARM_SER_CH1_RX_MATCH         (0x1c)
  86 #define NETARM_SER_CH1_RX_MATCH_MASK    (0x20)
  87 #define NETARM_SER_CH1_CTRL_C           (0x24)
  88 #define NETARM_SER_CH1_STATUS_B         (0x28)
  89 #define NETARM_SER_CH1_STATUS_C         (0x2c)
  90 #define NETARM_SER_CH1_FIFO_LAST        (0x30)
  91
  92 #define NETARM_SER_CH2_CTRL_A           (0x40)
  93 #define NETARM_SER_CH2_CTRL_B           (0x44)
  94 #define NETARM_SER_CH2_STATUS_A         (0x48)
  95 #define NETARM_SER_CH2_BITRATE          (0x4C)
  96 #define NETARM_SER_CH2_FIFO             (0x50)
  97 #define NETARM_SER_CH2_RX_BUF_TMR       (0x54)
  98 #define NETARM_SER_CH2_RX_CHAR_TMR      (0x58)
  99 #define NETARM_SER_CH2_RX_MATCH         (0x5c)
 100 #define NETARM_SER_CH2_RX_MATCH_MASK    (0x60)
 101 #define NETARM_SER_CH2_CTRL_C           (0x64)
 102 #define NETARM_SER_CH2_STATUS_B         (0x68)
 103 #define NETARM_SER_CH2_STATUS_C         (0x6c)
 104 #define NETARM_SER_CH2_FIFO_LAST        (0x70)
 105
 106 /* select bitfield defintions */
 107
 108 /* Control Register A */
 109
 110 #define NETARM_SER_CTLA_ENABLE          (0x80000000)
 111 #define NETARM_SER_CTLA_BRK             (0x40000000)
 112
 113 #define NETARM_SER_CTLA_STICKP          (0x20000000)
 114
 115 #define NETARM_SER_CTLA_P_EVEN          (0x18000000)
 116 #define NETARM_SER_CTLA_P_ODD           (0x08000000)
 117 #define NETARM_SER_CTLA_P_NONE          (0x00000000)
 118
 119 /* if you read the errata, you will find that the STOP bits don't work right */
 120 #define NETARM_SER_CTLA_2STOP           (0x00000000)
 121 #define NETARM_SER_CTLA_3STOP           (0x04000000)
 122
 123 #define NETARM_SER_CTLA_5BITS           (0x00000000)
 124 #define NETARM_SER_CTLA_6BITS           (0x01000000)
 125 #define NETARM_SER_CTLA_7BITS           (0x02000000)
 126 #define NETARM_SER_CTLA_8BITS           (0x03000000)
 127
 128 #define NETARM_SER_CTLA_CTSTX           (0x00800000)
 129 #define NETARM_SER_CTLA_RTSRX           (0x00400000)
 130
 131 #define NETARM_SER_CTLA_LOOP_REM        (0x00200000)
 132 #define NETARM_SER_CTLA_LOOP_LOC        (0x00100000)
 133
 134 #define NETARM_SER_CTLA_GPIO2           (0x00080000)
 135 #define NETARM_SER_CTLA_GPIO1           (0x00040000)
 136
 137 #define NETARM_SER_CTLA_DTR_EN          (0x00020000)
 138 #define NETARM_SER_CTLA_RTS_EN          (0x00010000)
 139
 140 #define NETARM_SER_CTLA_IE_RX_BRK       (0x00008000)
 141 #define NETARM_SER_CTLA_IE_RX_FRMERR    (0x00004000)
 142 #define NETARM_SER_CTLA_IE_RX_PARERR    (0x00002000)
 143 #define NETARM_SER_CTLA_IE_RX_OVERRUN   (0x00001000)
 144 #define NETARM_SER_CTLA_IE_RX_RDY       (0x00000800)
 145 #define NETARM_SER_CTLA_IE_RX_HALF      (0x00000400)
 146 #define NETARM_SER_CTLA_IE_RX_FULL      (0x00000200)
 147 #define NETARM_SER_CTLA_IE_RX_DMAEN     (0x00000100)
 148 #define NETARM_SER_CTLA_IE_RX_DCD       (0x00000080)
 149 #define NETARM_SER_CTLA_IE_RX_RI        (0x00000040)
 150 #define NETARM_SER_CTLA_IE_RX_DSR       (0x00000020)
 151
 152 #define NETARM_SER_CTLA_IE_RX_ALL       (NETARM_SER_CTLA_IE_RX_BRK \
 153                                         |NETARM_SER_CTLA_IE_RX_FRMERR \
 154                                         |NETARM_SER_CTLA_IE_RX_PARERR \
 155                                         |NETARM_SER_CTLA_IE_RX_OVERRUN \
 156                                         |NETARM_SER_CTLA_IE_RX_RDY \
 157                                         |NETARM_SER_CTLA_IE_RX_HALF \
 158                                         |NETARM_SER_CTLA_IE_RX_FULL \
 159                                         |NETARM_SER_CTLA_IE_RX_DMAEN \
 160                                         |NETARM_SER_CTLA_IE_RX_DCD \
 161                                         |NETARM_SER_CTLA_IE_RX_RI \
 162                                         |NETARM_SER_CTLA_IE_RX_DSR)
 163
 164 #define NETARM_SER_CTLA_IE_TX_CTS       (0x00000010)
 165 #define NETARM_SER_CTLA_IE_TX_EMPTY     (0x00000008)
 166 #define NETARM_SER_CTLA_IE_TX_HALF      (0x00000004)
 167 #define NETARM_SER_CTLA_IE_TX_FULL      (0x00000002)
 168 #define NETARM_SER_CTLA_IE_TX_DMAEN     (0x00000001)
 169
 170 #define NETARM_SER_CTLA_IE_TX_ALL       (NETARM_SER_CTLA_IE_TX_CTS \
 171                                         |NETARM_SER_CTLA_IE_TX_EMPTY \
 172                                         |NETARM_SER_CTLA_IE_TX_HALF \
 173                                         |NETARM_SER_CTLA_IE_TX_FULL \
 174                                         |NETARM_SER_CTLA_IE_TX_DMAEN)
 175
 176 /* Control Register B */
 177
 178 #define NETARM_SER_CTLB_MATCH1_EN       (0x80000000)
 179 #define NETARM_SER_CTLB_MATCH2_EN       (0x40000000)
 180 #define NETARM_SER_CTLB_MATCH3_EN       (0x20000000)
 181 #define NETARM_SER_CTLB_MATCH4_EN       (0x10000000)
 182
 183 #define NETARM_SER_CTLB_RBGT_EN         (0x08000000)
 184 #define NETARM_SER_CTLB_RCGT_EN         (0x04000000)
 185
 186 #define NETARM_SER_CTLB_UART_MODE       (0x00000000)
 187 #define NETARM_SER_CTLB_HDLC_MODE       (0x00100000)
 188 #define NETARM_SER_CTLB_SPI_MAS_MODE    (0x00200000)
 189 #define NETARM_SER_CTLB_SPI_SLV_MODE    (0x00300000)
 190
 191 #define NETARM_SER_CTLB_REV_BIT_ORDER   (0x00080000)
 192
 193 #define NETARM_SER_CTLB_MAM1            (0x00040000)
 194 #define NETARM_SER_CTLB_MAM2            (0x00020000)
 195
 196 /* Status Register A */
 197
 198 #define NETARM_SER_STATA_MATCH1         (0x80000000)
 199 #define NETARM_SER_STATA_MATCH2         (0x40000000)
 200 #define NETARM_SER_STATA_MATCH3         (0x20000000)
 201 #define NETARM_SER_STATA_MATCH4         (0x10000000)
 202
 203 #define NETARM_SER_STATA_BGAP           (0x80000000)
 204 #define NETARM_SER_STATA_CGAP           (0x40000000)
 205
 206 #define NETARM_SER_STATA_RX_1B          (0x00100000)
 207 #define NETARM_SER_STATA_RX_2B          (0x00200000)
 208 #define NETARM_SER_STATA_RX_3B          (0x00300000)
 209 #define NETARM_SER_STATA_RX_4B          (0x00000000)
 210
 211 /* downshifted values */
 212
 213 #define NETARM_SER_STATA_RXFDB_1BYTES   (0x001)
 214 #define NETARM_SER_STATA_RXFDB_2BYTES   (0x002)
 215 #define NETARM_SER_STATA_RXFDB_3BYTES   (0x003)
 216 #define NETARM_SER_STATA_RXFDB_4BYTES   (0x000)
 217
 218 #define NETARM_SER_STATA_RXFDB_MASK     (0x00300000)
 219 #define NETARM_SER_STATA_RXFDB(x)       (((x) & NETARM_SER_STATA_RXFDB_MASK) \
 220                                          >> 20)
 221
 222 #define NETARM_SER_STATA_DCD            (0x00080000)
 223 #define NETARM_SER_STATA_RI             (0x00040000)
 224 #define NETARM_SER_STATA_DSR            (0x00020000)
 225 #define NETARM_SER_STATA_CTS            (0x00010000)
 226
 227 #define NETARM_SER_STATA_RX_BRK         (0x00008000)
 228 #define NETARM_SER_STATA_RX_FRMERR      (0x00004000)
 229 #define NETARM_SER_STATA_RX_PARERR      (0x00002000)
 230 #define NETARM_SER_STATA_RX_OVERRUN     (0x00001000)
 231 #define NETARM_SER_STATA_RX_RDY         (0x00000800)
 232 #define NETARM_SER_STATA_RX_HALF        (0x00000400)
 233 #define NETARM_SER_STATA_RX_CLOSED      (0x00000200)
 234 #define NETARM_SER_STATA_RX_FULL        (0x00000100)
 235 #define NETARM_SER_STATA_RX_DCD         (0x00000080)
 236 #define NETARM_SER_STATA_RX_RI          (0x00000040)
 237 #define NETARM_SER_STATA_RX_DSR         (0x00000020)
 238
 239 #define NETARM_SER_STATA_TX_CTS         (0x00000010)
 240 #define NETARM_SER_STATA_TX_RDY         (0x00000008)
 241 #define NETARM_SER_STATA_TX_HALF        (0x00000004)
 242 #define NETARM_SER_STATA_TX_FULL        (0x00000002)
 243 #define NETARM_SER_STATA_TX_DMAEN       (0x00000001)
 244
 245 /* you have to clear all receive signals to get the fifo to move forward */
 246 #define NETARM_SER_STATA_CLR_ALL        (NETARM_SER_STATA_RX_BRK | \
 247                                          NETARM_SER_STATA_RX_FRMERR | \
 248                                          NETARM_SER_STATA_RX_PARERR | \
 249                                          NETARM_SER_STATA_RX_OVERRUN | \
 250                                          NETARM_SER_STATA_RX_HALF | \
 251                                          NETARM_SER_STATA_RX_CLOSED | \
 252                                          NETARM_SER_STATA_RX_FULL | \
 253                                          NETARM_SER_STATA_RX_DCD | \
 254                                          NETARM_SER_STATA_RX_RI | \
 255                                          NETARM_SER_STATA_RX_DSR | \
 256                                          NETARM_SER_STATA_TX_CTS )
 257
 258 /* Bit Rate Registers */
 259
 260 #define NETARM_SER_BR_EN                (0x80000000)
 261 #define NETARM_SER_BR_TMODE             (0x40000000)
 262
 263 #define NETARM_SER_BR_RX_CLK_INT        (0x00000000)
 264 #define NETARM_SER_BR_RX_CLK_EXT        (0x20000000)
 265 #define NETARM_SER_BR_TX_CLK_INT        (0x00000000)
 266 #define NETARM_SER_BR_TX_CLK_EXT        (0x10000000)
 267
 268 #define NETARM_SER_BR_RX_CLK_DRV        (0x08000000)
 269 #define NETARM_SER_BR_TX_CLK_DRV        (0x04000000)
 270
 271 #define NETARM_SER_BR_CLK_EXT_5         (0x00000000)
 272 #define NETARM_SER_BR_CLK_SYSTEM        (0x01000000)
 273 #define NETARM_SER_BR_CLK_OUT1A         (0x02000000)
 274 #define NETARM_SER_BR_CLK_OUT2A         (0x03000000)
 275
 276 #define NETARM_SER_BR_TX_CLK_INV        (0x00800000)
 277 #define NETARM_SER_BR_RX_CLK_INV        (0x00400000)
 278
 279 /* complete settings assuming system clock input is 18MHz */
 280
 281 #define NETARM_SER_BR_MASK              (0x000007FF)
 282
 283 /* bit rate determined from equation Fbr = Fxtal / [ 10 * ( N + 1 ) ] */
 284 /* from section 7.5.4 of HW Ref Guide */
 285
 286 /* #ifdef CONFIG_NETARM_PLL_BYPASS */
 287 #define NETARM_SER_BR_X16(x)    ( NETARM_SER_BR_EN |                    \
 288                                   NETARM_SER_BR_RX_CLK_INT |            \
 289                                   NETARM_SER_BR_TX_CLK_INT |            \
 290                                   NETARM_SER_BR_CLK_EXT_5 |             \
 291                                   ( ( ( ( NETARM_XTAL_FREQ /            \
 292                                           ( x * 10 ) ) - 1 ) /  16 ) &  \
 293                                     NETARM_SER_BR_MASK ) )
 294 /*
 295 #else
 296 #define NETARM_SER_BR_X16(x)    ( NETARM_SER_BR_EN |                    \
 297                                   NETARM_SER_BR_RX_CLK_INT |            \
 298                                   NETARM_SER_BR_TX_CLK_INT |            \
 299                                   NETARM_SER_BR_CLK_SYSTEM |            \
 300                                   ( ( ( ( NETARM_PLLED_SYSCLK_FREQ /            \
 301                                           ( x * 2 ) ) - 1 ) /   16 ) &  \
 302                                     NETARM_SER_BR_MASK ) )
 303 #endif
 304 */
 305
 306 /* Receive Buffer Gap Timer */
 307
 308 #define NETARM_SER_RX_GAP_TIMER_EN      (0x80000000)
 309 #define NETARM_SER_RX_GAP_MASK          (0x00003FFF)
 310
 311 /* rx gap is a function of bit rate x */
 312
 313 /* #ifdef CONFIG_NETARM_PLL_BYPASS */
 314 #define NETARM_SER_RXGAP(x)     ( NETARM_SER_RX_GAP_TIMER_EN |          \
 315                                   ( ( ( ( 10 * NETARM_XTAL_FREQ ) /     \
 316                                         ( x * 5 * 512 ) ) - 1 ) &       \
 317                                       NETARM_SER_RX_GAP_MASK ) )
 318 /*
 319 #else
 320 #define NETARM_SER_RXGAP(x)     ( NETARM_SER_RX_GAP_TIMER_EN |                  \
 321                                   ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) /      \
 322                                         ( x * 512 ) ) - 1 ) &                   \
 323                                       NETARM_SER_RX_GAP_MASK ) )
 324 #endif
 325 */
 326
 327 #if 0
 328 #define NETARM_SER_RXGAP(x)     ( NETARM_SER_RX_GAP_TIMER_EN |          \
 329                                   ( ( ( ( 2 * NETARM_PLLED_SYSCLK_FREQ ) /      \
 330                                         ( x * 5 * 512 ) ) - 1 ) &       \
 331                                       NETARM_SER_RX_GAP_MASK ) )
 332 #define NETARM_SER_RXGAP(x)     ( NETARM_SER_RX_GAP_TIMER_EN |          \
 333                                   ( ( ( ( 10 * NETARM_XTAL_FREQ ) /     \
 334                                         ( x * 512 ) ) - 1 ) &   \
 335                                       NETARM_SER_RX_GAP_MASK ) )
 336 #endif
 337
 338 #define MIN_BAUD_RATE        600
 339 #define MAX_BAUD_RATE     115200
 340
 341 /* the default BAUD rate for the BOOTLOADER, there is a separate */
 342 /* setting in the serial driver <arch/armnommu/drivers/char/serial-netarm.h> */
 343 #define DEFAULT_BAUD_RATE 9600
 344 #define NETARM_SER_FIFO_SIZE 32
 345 #define MIN_GAP 0
 346
 347 #endif