include/asm-arm/arch-at91/at91_spi.h

   1 /*
   2  * [origin: Linux kernel include/asm-arm/arch-at91/at91_spi.h]
   3  *
   4  * Copyright (C) 2005 Ivan Kokshaysky
   5  * Copyright (C) SAN People
   6  *
   7  * Serial Peripheral Interface (SPI) registers.
   8  * Based on AT91RM9200 datasheet revision E.
   9  *
  10  * This program is free software; you can redistribute it and/or modify
  11  * it under the terms of the GNU General Public License as published by
  12  * the Free Software Foundation; either version 2 of the License, or
  13  * (at your option) any later version.
  14  */
  15
  16 #ifndef AT91_SPI_H
  17 #define AT91_SPI_H
  18
  19 #include <asm/arch/at91_pdc.h>
  20
  21 typedef struct at91_spi {
  22         u32             cr;             /* 0x00 Control Register */
  23         u32             mr;             /* 0x04 Mode Register */
  24         u32             rdr;            /* 0x08 Receive Data Register */
  25         u32             tdr;            /* 0x0C Transmit Data Register */
  26         u32             sr;             /* 0x10 Status Register */
  27         u32             ier;            /* 0x14 Interrupt Enable Register */
  28         u32             idr;            /* 0x18 Interrupt Disable Register */
  29         u32             imr;            /* 0x1C Interrupt Mask Register */
  30         u32             reserve1[4];
  31         u32             csr[4];         /* 0x30 Chip Select Register 0-3 */
  32         u32             reserve2[48];
  33         at91_pdc_t      pdc;
  34 } at91_spi_t;
  35
  36 #ifdef CONFIG_AT91_LEGACY
  37
  38 #define AT91_SPI_CR                     0x00            /* Control Register */
  39 #define         AT91_SPI_SPIEN          (1 <<  0)               /* SPI Enable */
  40 #define         AT91_SPI_SPIDIS         (1 <<  1)               /* SPI Disable */
  41 #define         AT91_SPI_SWRST          (1 <<  7)               /* SPI Software Reset */
  42 #define         AT91_SPI_LASTXFER       (1 << 24)               /* Last Transfer [SAM9261 only] */
  43
  44 #define AT91_SPI_MR                     0x04            /* Mode Register */
  45 #define         AT91_SPI_MSTR           (1    <<  0)            /* Master/Slave Mode */
  46 #define         AT91_SPI_PS             (1    <<  1)            /* Peripheral Select */
  47 #define                 AT91_SPI_PS_FIXED       (0 << 1)
  48 #define                 AT91_SPI_PS_VARIABLE    (1 << 1)
  49 #define         AT91_SPI_PCSDEC         (1    <<  2)            /* Chip Select Decode */
  50 #define         AT91_SPI_DIV32          (1    <<  3)            /* Clock Selection [AT91RM9200 only] */
  51 #define         AT91_SPI_MODFDIS        (1    <<  4)            /* Mode Fault Detection */
  52 #define         AT91_SPI_LLB            (1    <<  7)            /* Local Loopback Enable */
  53 #define         AT91_SPI_PCS            (0xf  << 16)            /* Peripheral Chip Select */
  54 #define         AT91_SPI_DLYBCS         (0xff << 24)            /* Delay Between Chip Selects */
  55
  56 #define AT91_SPI_RDR            0x08                    /* Receive Data Register */
  57 #define         AT91_SPI_RD             (0xffff <<  0)          /* Receive Data */
  58 #define         AT91_SPI_PCS            (0xf    << 16)          /* Peripheral Chip Select */
  59
  60 #define AT91_SPI_TDR            0x0c                    /* Transmit Data Register */
  61 #define         AT91_SPI_TD             (0xffff <<  0)          /* Transmit Data */
  62 #define         AT91_SPI_PCS            (0xf    << 16)          /* Peripheral Chip Select */
  63 #define         AT91_SPI_LASTXFER       (1      << 24)          /* Last Transfer [SAM9261 only] */
  64
  65 #define AT91_SPI_SR             0x10                    /* Status Register */
  66 #define         AT91_SPI_RDRF           (1 <<  0)               /* Receive Data Register Full */
  67 #define         AT91_SPI_TDRE           (1 <<  1)               /* Transmit Data Register Full */
  68 #define         AT91_SPI_MODF           (1 <<  2)               /* Mode Fault Error */
  69 #define         AT91_SPI_OVRES          (1 <<  3)               /* Overrun Error Status */
  70 #define         AT91_SPI_ENDRX          (1 <<  4)               /* End of RX buffer */
  71 #define         AT91_SPI_ENDTX          (1 <<  5)               /* End of TX buffer */
  72 #define         AT91_SPI_RXBUFF         (1 <<  6)               /* RX Buffer Full */
  73 #define         AT91_SPI_TXBUFE         (1 <<  7)               /* TX Buffer Empty */
  74 #define         AT91_SPI_NSSR           (1 <<  8)               /* NSS Rising [SAM9261 only] */
  75 #define         AT91_SPI_TXEMPTY        (1 <<  9)               /* Transmission Register Empty [SAM9261 only] */
  76 #define         AT91_SPI_SPIENS         (1 << 16)               /* SPI Enable Status */
  77
  78 #define AT91_SPI_IER            0x14                    /* Interrupt Enable Register */
  79 #define AT91_SPI_IDR            0x18                    /* Interrupt Disable Register */
  80 #define AT91_SPI_IMR            0x1c                    /* Interrupt Mask Register */
  81
  82 #define AT91_SPI_CSR(n)         (0x30 + ((n) * 4))      /* Chip Select Registers 0-3 */
  83 #define         AT91_SPI_CPOL           (1    <<  0)            /* Clock Polarity */
  84 #define         AT91_SPI_NCPHA          (1    <<  1)            /* Clock Phase */
  85 #define         AT91_SPI_CSAAT          (1    <<  3)            /* Chip Select Active After Transfer [SAM9261 only] */
  86 #define         AT91_SPI_BITS           (0xf  <<  4)            /* Bits Per Transfer */
  87 #define                 AT91_SPI_BITS_8         (0 << 4)
  88 #define                 AT91_SPI_BITS_9         (1 << 4)
  89 #define                 AT91_SPI_BITS_10        (2 << 4)
  90 #define                 AT91_SPI_BITS_11        (3 << 4)
  91 #define                 AT91_SPI_BITS_12        (4 << 4)
  92 #define                 AT91_SPI_BITS_13        (5 << 4)
  93 #define                 AT91_SPI_BITS_14        (6 << 4)
  94 #define                 AT91_SPI_BITS_15        (7 << 4)
  95 #define                 AT91_SPI_BITS_16        (8 << 4)
  96 #define         AT91_SPI_SCBR           (0xff <<  8)            /* Serial Clock Baud Rate */
  97 #define         AT91_SPI_DLYBS          (0xff << 16)            /* Delay before SPCK */
  98 #define         AT91_SPI_DLYBCT         (0xff << 24)            /* Delay between Consecutive Transfers */
  99
 100 #define AT91_SPI_RPR            0x0100                  /* Receive Pointer Register */
 101
 102 #define AT91_SPI_RCR            0x0104                  /* Receive Counter Register */
 103
 104 #define AT91_SPI_TPR            0x0108                  /* Transmit Pointer Register */
 105
 106 #define AT91_SPI_TCR            0x010c                  /* Transmit Counter Register */
 107
 108 #define AT91_SPI_RNPR           0x0110                  /* Receive Next Pointer Register */
 109
 110 #define AT91_SPI_RNCR           0x0114                  /* Receive Next Counter Register */
 111
 112 #define AT91_SPI_TNPR           0x0118                  /* Transmit Next Pointer Register */
 113
 114 #define AT91_SPI_TNCR           0x011c                  /* Transmit Next Counter Register */
 115
 116 #define AT91_SPI_PTCR           0x0120                  /* PDC Transfer Control Register */
 117 #define         AT91_SPI_RXTEN          (0x1 << 0)              /* Receiver Transfer Enable */
 118 #define         AT91_SPI_RXTDIS         (0x1 << 1)              /* Receiver Transfer Disable */
 119 #define         AT91_SPI_TXTEN          (0x1 << 8)              /* Transmitter Transfer Enable */
 120 #define         AT91_SPI_TXTDIS         (0x1 << 9)              /* Transmitter Transfer Disable */
 121
 122 #define AT91_SPI_PTSR           0x0124                  /* PDC Transfer Status Register */
 123
 124 #endif /* CONFIG_AT91_LEGACY */
 125
 126 #endif