include/asm-arm/arch-davinci/emif_defs.h

   1 /*
   2  * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net>
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22 #ifndef _EMIF_DEFS_H_
  23 #define _EMIF_DEFS_H_
  24
  25 #include <asm/arch/hardware.h>
  26
  27 typedef struct {
  28         dv_reg          ERCSR;
  29         dv_reg          AWCCR;
  30         dv_reg          SDBCR;
  31         dv_reg          SDRCR;
  32         dv_reg          AB1CR;
  33         dv_reg          AB2CR;
  34         dv_reg          AB3CR;
  35         dv_reg          AB4CR;
  36         dv_reg          SDTIMR;
  37         dv_reg          DDRSR;
  38         dv_reg          DDRPHYCR;
  39         dv_reg          DDRPHYSR;
  40         dv_reg          TOTAR;
  41         dv_reg          TOTACTR;
  42         dv_reg          DDRPHYID_REV;
  43         dv_reg          SDSRETR;
  44         dv_reg          EIRR;
  45         dv_reg          EIMR;
  46         dv_reg          EIMSR;
  47         dv_reg          EIMCR;
  48         dv_reg          IOCTRLR;
  49         dv_reg          IOSTATR;
  50         u_int8_t        RSVD0[8];
  51         dv_reg          NANDFCR;
  52         dv_reg          NANDFSR;
  53         u_int8_t        RSVD1[8];
  54         dv_reg          NANDF1ECC;
  55         dv_reg          NANDF2ECC;
  56         dv_reg          NANDF3ECC;
  57         dv_reg          NANDF4ECC;
  58         u_int8_t        RSVD2[60];
  59         dv_reg          NAND4BITECCLOAD;
  60         dv_reg          NAND4BITECC1;
  61         dv_reg          NAND4BITECC2;
  62         dv_reg          NAND4BITECC3;
  63         dv_reg          NAND4BITECC4;
  64         dv_reg          NANDERRADD1;
  65         dv_reg          NANDERRADD2;
  66         dv_reg          NANDERRVAL1;
  67         dv_reg          NANDERRVAL2;
  68 } emif_registers;
  69
  70 typedef emif_registers  *emifregs;
  71 #endif