include/asm-arm/arch-mx25/imx25-pinmux.h

   1 /*
   2  * iopin settings are controlled by four different sets of registers
   3  *      iopad mux control
   4  *      individual iopad setup (voltage select, pull/keep, drive strength ...)
   5  *      group iopad setup (same as above but for groups of signals)
   6  *      input select when multiple inputs are possible
   7  */
   8
   9 /*
  10  * software pad mux control
  11  */
  12 /* SW Input On (Loopback) */
  13 #define MX25_PIN_MUX_SION               (1 << 4)
  14 /* MUX Mode (0-7) */
  15 #define MX25_PIN_MUX_MODE(mode)         ((mode & 0x7) << 0)
  16 struct iomuxc_mux_ctl {
  17         u32 gpr1;
  18         u32 observe_int_mux;
  19         u32 pad_a10;
  20         u32 pad_a13;
  21         u32 pad_a14;
  22         u32 pad_a15;
  23         u32 pad_a16;
  24         u32 pad_a17;
  25         u32 pad_a18;
  26         u32 pad_a19;
  27         u32 pad_a20;
  28         u32 pad_a21;
  29         u32 pad_a22;
  30         u32 pad_a23;
  31         u32 pad_a24;
  32         u32 pad_a25;
  33         u32 pad_eb0;
  34         u32 pad_eb1;
  35         u32 pad_oe;
  36         u32 pad_cs0;
  37         u32 pad_cs1;
  38         u32 pad_cs4;
  39         u32 pad_cs5;
  40         u32 pad_nf_ce0;
  41         u32 pad_ecb;
  42         u32 pad_lba;
  43         u32 pad_bclk;
  44         u32 pad_rw;
  45         u32 pad_nfwe_b;
  46         u32 pad_nfre_b;
  47         u32 pad_nfale;
  48         u32 pad_nfcle;
  49         u32 pad_nfwp_b;
  50         u32 pad_nfrb;
  51         u32 pad_d15;
  52         u32 pad_d14;
  53         u32 pad_d13;
  54         u32 pad_d12;
  55         u32 pad_d11;
  56         u32 pad_d10;
  57         u32 pad_d9;
  58         u32 pad_d8;
  59         u32 pad_d7;
  60         u32 pad_d6;
  61         u32 pad_d5;
  62         u32 pad_d4;
  63         u32 pad_d3;
  64         u32 pad_d2;
  65         u32 pad_d1;
  66         u32 pad_d0;
  67         u32 pad_ld0;
  68         u32 pad_ld1;
  69         u32 pad_ld2;
  70         u32 pad_ld3;
  71         u32 pad_ld4;
  72         u32 pad_ld5;
  73         u32 pad_ld6;
  74         u32 pad_ld7;
  75         u32 pad_ld8;
  76         u32 pad_ld9;
  77         u32 pad_ld10;
  78         u32 pad_ld11;
  79         u32 pad_ld12;
  80         u32 pad_ld13;
  81         u32 pad_ld14;
  82         u32 pad_ld15;
  83         u32 pad_hsync;
  84         u32 pad_vsync;
  85         u32 pad_lsclk;
  86         u32 pad_oe_acd;
  87         u32 pad_contrast;
  88         u32 pad_pwm;
  89         u32 pad_csi_d2;
  90         u32 pad_csi_d3;
  91         u32 pad_csi_d4;
  92         u32 pad_csi_d5;
  93         u32 pad_csi_d6;
  94         u32 pad_csi_d7;
  95         u32 pad_csi_d8;
  96         u32 pad_csi_d9;
  97         u32 pad_csi_mclk;
  98         u32 pad_csi_vsync;
  99         u32 pad_csi_hsync;
 100         u32 pad_csi_pixclk;
 101         u32 pad_i2c1_clk;
 102         u32 pad_i2c1_dat;
 103         u32 pad_cspi1_mosi;
 104         u32 pad_cspi1_miso;
 105         u32 pad_cspi1_ss0;
 106         u32 pad_cspi1_ss1;
 107         u32 pad_cspi1_sclk;
 108         u32 pad_cspi1_rdy;
 109         u32 pad_uart1_rxd;
 110         u32 pad_uart1_txd;
 111         u32 pad_uart1_rts;
 112         u32 pad_uart1_cts;
 113         u32 pad_uart2_rxd;
 114         u32 pad_uart2_txd;
 115         u32 pad_uart2_rts;
 116         u32 pad_uart2_cts;
 117         u32 pad_sd1_cmd;
 118         u32 pad_sd1_clk;
 119         u32 pad_sd1_data0;
 120         u32 pad_sd1_data1;
 121         u32 pad_sd1_data2;
 122         u32 pad_sd1_data3;
 123         u32 pad_kpp_row0;
 124         u32 pad_kpp_row1;
 125         u32 pad_kpp_row2;
 126         u32 pad_kpp_row3;
 127         u32 pad_kpp_col0;
 128         u32 pad_kpp_col1;
 129         u32 pad_kpp_col2;
 130         u32 pad_kpp_col3;
 131         u32 pad_fec_mdc;
 132         u32 pad_fec_mdio;
 133         u32 pad_fec_tdata0;
 134         u32 pad_fec_tdata1;
 135         u32 pad_fec_tx_en;
 136         u32 pad_fec_rdata0;
 137         u32 pad_fec_rdata1;
 138         u32 pad_fec_rx_dv;
 139         u32 pad_fec_tx_clk;
 140         u32 pad_rtck;
 141         u32 pad_de_b;
 142         u32 pad_gpio_a;
 143         u32 pad_gpio_b;
 144         u32 pad_gpio_c;
 145         u32 pad_gpio_d;
 146         u32 pad_gpio_e;
 147         u32 pad_gpio_f;
 148         u32 pad_ext_armclk;
 149         u32 pad_upll_bypclk;
 150         u32 pad_vstby_req;
 151         u32 pad_vstby_ack;
 152         u32 pad_power_fail;
 153         u32 pad_clko;
 154         u32 pad_boot_mode0;
 155         u32 pad_boot_mode1;
 156 };
 157
 158 /*
 159  * software pad control
 160  */
 161 /* Select 3.3 or 1.8 volts */
 162 #define MX25_PIN_PAD_CTL_DVS_33                 (0 << 13)
 163 #define MX25_PIN_PAD_CTL_DVS_18                 (1 << 13)
 164 /* Enable hysteresis */
 165 #define MX25_PIN_PAD_CTL_HYS                    (1 << 8)
 166 /* Enable pull/keeper */
 167 #define MX25_PIN_PAD_CTL_PKE                    (1 << 7)
 168 /* 0 - keeper / 1 - pull */
 169 #define MX25_PIN_PAD_CTL_PUE                    (1 << 6)
 170 /* pull up/down strength */
 171 #define MX25_PIN_PAD_CTL_100K_PD                (0 << 4)
 172 #define MX25_PIN_PAD_CTL_47K_PU                 (1 << 4)
 173 #define MX25_PIN_PAD_CTL_100K_PU                (2 << 4)
 174 #define MX25_PIN_PAD_CTL_22K_PU                 (3 << 4)
 175 /* open drain control */
 176 #define MX25_PIN_PAD_CTL_OD                     (1 << 3)
 177 /* drive strength */
 178 #define MX25_PIN_PAD_CTL_DS_NOM                 (0 << 1)
 179 #define MX25_PIN_PAD_CTL_DS_HIGH                (1 << 1)
 180 #define MX25_PIN_PAD_CTL_DS_MAX                 (2 << 1)
 181 #define MX25_PIN_PAD_CTL_DS_MAX11               (3 << 1)
 182 /* slew rate */
 183 #define MX25_PIN_PAD_CTL_SRE_SLOW               (0 << 0)
 184 #define MX25_PIN_PAD_CTL_SRE_FAST               (1 << 0)
 185 struct  iomuxc_pad_ctl {
 186         u32 pad_a13;
 187         u32 pad_a14;
 188         u32 pad_a15;
 189         u32 pad_a17;
 190         u32 pad_a18;
 191         u32 pad_a19;
 192         u32 pad_a20;
 193         u32 pad_a21;
 194         u32 pad_a23;
 195         u32 pad_a24;
 196         u32 pad_a25;
 197         u32 pad_eb0;
 198         u32 pad_eb1;
 199         u32 pad_oe;
 200         u32 pad_cs4;
 201         u32 pad_cs5;
 202         u32 pad_nf_ce0;
 203         u32 pad_ecb;
 204         u32 pad_lba;
 205         u32 pad_rw;
 206         u32 pad_nfrb;
 207         u32 pad_d15;
 208         u32 pad_d14;
 209         u32 pad_d13;
 210         u32 pad_d12;
 211         u32 pad_d11;
 212         u32 pad_d10;
 213         u32 pad_d9;
 214         u32 pad_d8;
 215         u32 pad_d7;
 216         u32 pad_d6;
 217         u32 pad_d5;
 218         u32 pad_d4;
 219         u32 pad_d3;
 220         u32 pad_d2;
 221         u32 pad_d1;
 222         u32 pad_d0;
 223         u32 pad_ld0;
 224         u32 pad_ld1;
 225         u32 pad_ld2;
 226         u32 pad_ld3;
 227         u32 pad_ld4;
 228         u32 pad_ld5;
 229         u32 pad_ld6;
 230         u32 pad_ld7;
 231         u32 pad_ld8;
 232         u32 pad_ld9;
 233         u32 pad_ld10;
 234         u32 pad_ld11;
 235         u32 pad_ld12;
 236         u32 pad_ld13;
 237         u32 pad_ld14;
 238         u32 pad_ld15;
 239         u32 pad_hsync;
 240         u32 pad_vsync;
 241         u32 pad_lsclk;
 242         u32 pad_oe_acd;
 243         u32 pad_contrast;
 244         u32 pad_pwm;
 245         u32 pad_csi_d2;
 246         u32 pad_csi_d3;
 247         u32 pad_csi_d4;
 248         u32 pad_csi_d5;
 249         u32 pad_csi_d6;
 250         u32 pad_csi_d7;
 251         u32 pad_csi_d8;
 252         u32 pad_csi_d9;
 253         u32 pad_csi_mclk;
 254         u32 pad_csi_vsync;
 255         u32 pad_csi_hsync;
 256         u32 pad_csi_pixclk;
 257         u32 pad_i2c1_clk;
 258         u32 pad_i2c1_dat;
 259         u32 pad_cspi1_mosi;
 260         u32 pad_cspi1_miso;
 261         u32 pad_cspi1_ss0;
 262         u32 pad_cspi1_ss1;
 263         u32 pad_cspi1_sclk;
 264         u32 pad_cspi1_rdy;
 265         u32 pad_uart1_rxd;
 266         u32 pad_uart1_txd;
 267         u32 pad_uart1_rts;
 268         u32 pad_uart1_cts;
 269         u32 pad_uart2_rxd;
 270         u32 pad_uart2_txd;
 271         u32 pad_uart2_rts;
 272         u32 pad_uart2_cts;
 273         u32 pad_sd1_cmd;
 274         u32 pad_sd1_clk;
 275         u32 pad_sd1_data0;
 276         u32 pad_sd1_data1;
 277         u32 pad_sd1_data2;
 278         u32 pad_sd1_data3;
 279         u32 pad_kpp_row0;
 280         u32 pad_kpp_row1;
 281         u32 pad_kpp_row2;
 282         u32 pad_kpp_row3;
 283         u32 pad_kpp_col0;
 284         u32 pad_kpp_col1;
 285         u32 pad_kpp_col2;
 286         u32 pad_kpp_col3;
 287         u32 pad_fec_mdc;
 288         u32 pad_fec_mdio;
 289         u32 pad_fec_tdata0;
 290         u32 pad_fec_tdata1;
 291         u32 pad_fec_tx_en;
 292         u32 pad_fec_rdata0;
 293         u32 pad_fec_rdata1;
 294         u32 pad_fec_rx_dv;
 295         u32 pad_fec_tx_clk;
 296         u32 pad_rtck;
 297         u32 pad_tdo;
 298         u32 pad_de_b;
 299         u32 pad_gpio_a;
 300         u32 pad_gpio_b;
 301         u32 pad_gpio_c;
 302         u32 pad_gpio_d;
 303         u32 pad_gpio_e;
 304         u32 pad_gpio_f;
 305         u32 pad_vstby_req;
 306         u32 pad_vstby_ack;
 307         u32 pad_power_fail;
 308         u32 pad_clko;
 309 };
 310
 311
 312 /*
 313  * Pad group drive strength and voltage select
 314  * Same fields as iomuxc_pad_ctl plus ddr type
 315  */
 316 /* Select DDR type */
 317 #define MX25_PIN_PAD_CTL_DDR_18                 (0 << 11)
 318 #define MX25_PIN_PAD_CTL_DDR_33                 (1 << 11)
 319 #define MX25_PIN_PAD_CTL_DDR_MAX                (2 << 11)
 320 struct iomuxc_pad_grp_ctl {
 321         u32 grp_dvs_misc;
 322         u32 grp_dse_fec;
 323         u32 grp_dvs_jtag;
 324         u32 grp_dse_nfc;
 325         u32 grp_dse_csi;
 326         u32 grp_dse_weim;
 327         u32 grp_dse_ddr;
 328         u32 grp_dvs_crm;
 329         u32 grp_dse_kpp;
 330         u32 grp_dse_sdhc1;
 331         u32 grp_dse_lcd;
 332         u32 grp_dse_uart;
 333         u32 grp_dvs_nfc;
 334         u32 grp_dvs_csi;
 335         u32 grp_dse_cspi1;
 336         u32 grp_ddrtype;
 337         u32 grp_dvs_sdhc1;
 338         u32 grp_dvs_lcd;
 339 };
 340
 341 /*
 342  * Pad input select control
 343  * Select which pad to connect to an input port
 344  * where multiple pads can function as given input
 345  */
 346 #define MX25_PAD_INPUT_SELECT_DAISY(in)         ((in & 0x7) << 0)
 347 struct iomuxc_pad_input_select {
 348         u32 audmux_p4_input_da_amx;
 349         u32 audmux_p4_input_db_amx;
 350         u32 audmux_p4_input_rxclk_amx;
 351         u32 audmux_p4_input_rxfs_amx;
 352         u32 audmux_p4_input_txclk_amx;
 353         u32 audmux_p4_input_txfs_amx;
 354         u32 audmux_p7_input_da_amx;
 355         u32 audmux_p7_input_txfs_amx;
 356         u32 can1_ipp_ind_canrx;
 357         u32 can2_ipp_ind_canrx;
 358         u32 csi_ipp_csi_d_0;
 359         u32 csi_ipp_csi_d_1;
 360         u32 cspi1_ipp_ind_ss3_b;
 361         u32 cspi2_ipp_cspi_clk_in;
 362         u32 cspi2_ipp_ind_dataready_b;
 363         u32 cspi2_ipp_ind_miso;
 364         u32 cspi2_ipp_ind_mosi;
 365         u32 cspi2_ipp_ind_ss0_b;
 366         u32 cspi2_ipp_ind_ss1_b;
 367         u32 cspi3_ipp_cspi_clk_in;
 368         u32 cspi3_ipp_ind_dataready_b;
 369         u32 cspi3_ipp_ind_miso;
 370         u32 cspi3_ipp_ind_mosi;
 371         u32 cspi3_ipp_ind_ss0_b;
 372         u32 cspi3_ipp_ind_ss1_b;
 373         u32 cspi3_ipp_ind_ss2_b;
 374         u32 cspi3_ipp_ind_ss3_b;
 375         u32 esdhc1_ipp_dat4_in;
 376         u32 esdhc1_ipp_dat5_in;
 377         u32 esdhc1_ipp_dat6_in;
 378         u32 esdhc1_ipp_dat7_in;
 379         u32 esdhc2_ipp_card_clk_in;
 380         u32 esdhc2_ipp_cmd_in;
 381         u32 esdhc2_ipp_dat0_in;
 382         u32 esdhc2_ipp_dat1_in;
 383         u32 esdhc2_ipp_dat2_in;
 384         u32 esdhc2_ipp_dat3_in;
 385         u32 esdhc2_ipp_dat4_in;
 386         u32 esdhc2_ipp_dat5_in;
 387         u32 esdhc2_ipp_dat6_in;
 388         u32 esdhc2_ipp_dat7_in;
 389         u32 fec_fec_col;
 390         u32 fec_fec_crs;
 391         u32 fec_fec_rdata_2;
 392         u32 fec_fec_rdata_3;
 393         u32 fec_fec_rx_clk;
 394         u32 fec_fec_rx_er;
 395         u32 i2c2_ipp_scl_in;
 396         u32 i2c2_ipp_sda_in;
 397         u32 i2c3_ipp_scl_in;
 398         u32 i2c3_ipp_sda_in;
 399         u32 kpp_ipp_ind_col_4;
 400         u32 kpp_ipp_ind_col_5;
 401         u32 kpp_ipp_ind_col_6;
 402         u32 kpp_ipp_ind_col_7;
 403         u32 kpp_ipp_ind_row_4;
 404         u32 kpp_ipp_ind_row_5;
 405         u32 kpp_ipp_ind_row_6;
 406         u32 kpp_ipp_ind_row_7;
 407         u32 sim1_pin_sim_rcvd1_in;
 408         u32 sim1_pin_sim_simpd1;
 409         u32 sim1_sim_rcvd1_io;
 410         u32 sim2_pin_sim_rcvd1_in;
 411         u32 sim2_pin_sim_simpd1;
 412         u32 sim2_sim_rcvd1_io;
 413         u32 uart3_ipp_uart_rts_b;
 414         u32 uart3_ipp_uart_rxd_mux;
 415         u32 uart4_ipp_uart_rts_b;
 416         u32 uart4_ipp_uart_rxd_mux;
 417         u32 uart5_ipp_uart_rts_b;
 418         u32 uart5_ipp_uart_rxd_mux;
 419         u32 usb_top_ipp_ind_otg_usb_oc;
 420         u32 usb_top_ipp_ind_uh2_usb_oc;
 421 };