include/asm-arm/arch-omap3/i2c.h

   1 /*
   2  * (C) Copyright 2004-2008
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23 #ifndef _I2C_H_
  24 #define _I2C_H_
  25
  26 #define I2C_DEFAULT_BASE        I2C_BASE1
  27
  28 struct i2c {
  29         unsigned short rev;     /* 0x00 */
  30         unsigned short res1;
  31         unsigned short ie;      /* 0x04 */
  32         unsigned short res2;
  33         unsigned short stat;    /* 0x08 */
  34         unsigned short res3;
  35         unsigned short iv;      /* 0x0C */
  36         unsigned short res4[3];
  37         unsigned short buf;     /* 0x14 */
  38         unsigned short res5;
  39         unsigned short cnt;     /* 0x18 */
  40         unsigned short res6;
  41         unsigned short data;    /* 0x1C */
  42         unsigned short res7;
  43         unsigned short sysc;    /* 0x20 */
  44         unsigned short res8;
  45         unsigned short con;     /* 0x24 */
  46         unsigned short res9;
  47         unsigned short oa;      /* 0x28 */
  48         unsigned short res10;
  49         unsigned short sa;      /* 0x2C */
  50         unsigned short res11;
  51         unsigned short psc;     /* 0x30 */
  52         unsigned short res12;
  53         unsigned short scll;    /* 0x34 */
  54         unsigned short res13;
  55         unsigned short sclh;    /* 0x38 */
  56         unsigned short res14;
  57         unsigned short systest; /* 0x3c */
  58         unsigned short res15;
  59 };
  60
  61 #define I2C_BUS_MAX     3
  62
  63 /* I2C masks */
  64
  65 /* I2C Interrupt Enable Register (I2C_IE): */
  66 #define I2C_IE_GC_IE    (1 << 5)
  67 #define I2C_IE_XRDY_IE  (1 << 4) /* Transmit data ready interrupt enable */
  68 #define I2C_IE_RRDY_IE  (1 << 3) /* Receive data ready interrupt enable */
  69 #define I2C_IE_ARDY_IE  (1 << 2) /* Register access ready interrupt enable */
  70 #define I2C_IE_NACK_IE  (1 << 1) /* No acknowledgment interrupt enable */
  71 #define I2C_IE_AL_IE    (1 << 0) /* Arbitration lost interrupt enable */
  72
  73 /* I2C Status Register (I2C_STAT): */
  74
  75 #define I2C_STAT_SBD    (1 << 15) /* Single byte data */
  76 #define I2C_STAT_BB     (1 << 12) /* Bus busy */
  77 #define I2C_STAT_ROVR   (1 << 11) /* Receive overrun */
  78 #define I2C_STAT_XUDF   (1 << 10) /* Transmit underflow */
  79 #define I2C_STAT_AAS    (1 << 9)  /* Address as slave */
  80 #define I2C_STAT_GC     (1 << 5)
  81 #define I2C_STAT_XRDY   (1 << 4)  /* Transmit data ready */
  82 #define I2C_STAT_RRDY   (1 << 3)  /* Receive data ready */
  83 #define I2C_STAT_ARDY   (1 << 2)  /* Register access ready */
  84 #define I2C_STAT_NACK   (1 << 1)  /* No acknowledgment interrupt enable */
  85 #define I2C_STAT_AL     (1 << 0)  /* Arbitration lost interrupt enable */
  86
  87 /* I2C Interrupt Code Register (I2C_INTCODE): */
  88
  89 #define I2C_INTCODE_MASK        7
  90 #define I2C_INTCODE_NONE        0
  91 #define I2C_INTCODE_AL          1       /* Arbitration lost */
  92 #define I2C_INTCODE_NAK         2       /* No acknowledgement/general call */
  93 #define I2C_INTCODE_ARDY        3       /* Register access ready */
  94 #define I2C_INTCODE_RRDY        4       /* Rcv data ready */
  95 #define I2C_INTCODE_XRDY        5       /* Xmit data ready */
  96
  97 /* I2C Buffer Configuration Register (I2C_BUF): */
  98
  99 #define I2C_BUF_RDMA_EN         (1 << 15) /* Receive DMA channel enable */
 100 #define I2C_BUF_XDMA_EN         (1 << 7)  /* Transmit DMA channel enable */
 101
 102 /* I2C Configuration Register (I2C_CON): */
 103
 104 #define I2C_CON_EN      (1 << 15)  /* I2C module enable */
 105 #define I2C_CON_BE      (1 << 14)  /* Big endian mode */
 106 #define I2C_CON_STB     (1 << 11)  /* Start byte mode (master mode only) */
 107 #define I2C_CON_MST     (1 << 10)  /* Master/slave mode */
 108 #define I2C_CON_TRX     (1 << 9)   /* Transmitter/receiver mode */
 109                                    /* (master mode only) */
 110 #define I2C_CON_XA      (1 << 8)   /* Expand address */
 111 #define I2C_CON_STP     (1 << 1)   /* Stop condition (master mode only) */
 112 #define I2C_CON_STT     (1 << 0)   /* Start condition (master mode only) */
 113
 114 /* I2C System Test Register (I2C_SYSTEST): */
 115
 116 #define I2C_SYSTEST_ST_EN       (1 << 15) /* System test enable */
 117 #define I2C_SYSTEST_FREE        (1 << 14) /* Free running mode, on brkpoint) */
 118 #define I2C_SYSTEST_TMODE_MASK  (3 << 12) /* Test mode select */
 119 #define I2C_SYSTEST_TMODE_SHIFT (12)      /* Test mode select */
 120 #define I2C_SYSTEST_SCL_I       (1 << 3)  /* SCL line sense input value */
 121 #define I2C_SYSTEST_SCL_O       (1 << 2)  /* SCL line drive output value */
 122 #define I2C_SYSTEST_SDA_I       (1 << 1)  /* SDA line sense input value */
 123 #define I2C_SYSTEST_SDA_O       (1 << 0)  /* SDA line drive output value */
 124
 125 #define I2C_SCLL_SCLL           0
 126 #define I2C_SCLL_SCLL_M         0xFF
 127 #define I2C_SCLL_HSSCLL         8
 128 #define I2C_SCLH_HSSCLL_M       0xFF
 129 #define I2C_SCLH_SCLH           0
 130 #define I2C_SCLH_SCLH_M         0xFF
 131 #define I2C_SCLH_HSSCLH         8
 132 #define I2C_SCLH_HSSCLH_M       0xFF
 133
 134 #define OMAP_I2C_STANDARD       100000
 135 #define OMAP_I2C_FAST_MODE      400000
 136 #define OMAP_I2C_HIGH_SPEED     3400000
 137
 138 #define SYSTEM_CLOCK_12         12000000
 139 #define SYSTEM_CLOCK_13         13000000
 140 #define SYSTEM_CLOCK_192        19200000
 141 #define SYSTEM_CLOCK_96         96000000
 142
 143 /* Use the reference value of 96MHz if not explicitly set by the board */
 144 #ifndef I2C_IP_CLK
 145 #define I2C_IP_CLK              SYSTEM_CLOCK_96
 146 #endif
 147
 148 /*
 149  * The reference minimum clock for high speed is 19.2MHz.
 150  * The linux 2.6.30 kernel uses this value.
 151  * The reference minimum clock for fast mode is 9.6MHz
 152  * The reference minimum clock for standard mode is 4MHz
 153  * In TRM, the value of 12MHz is used.
 154  */
 155 #ifndef I2C_INTERNAL_SAMPLING_CLK
 156 #define I2C_INTERNAL_SAMPLING_CLK       19200000
 157 #endif
 158
 159 /*
 160  * The equation for the low and high time is
 161  * tlow = scll + scll_trim = (sampling clock * tlow_duty) / speed
 162  * thigh = sclh + sclh_trim = (sampling clock * (1 - tlow_duty)) / speed
 163  *
 164  * If the duty cycle is 50%
 165  *
 166  * tlow = scll + scll_trim = sampling clock / (2 * speed)
 167  * thigh = sclh + sclh_trim = sampling clock / (2 * speed)
 168  *
 169  * In TRM
 170  * scll_trim = 7
 171  * sclh_trim = 5
 172  *
 173  * The linux 2.6.30 kernel uses
 174  * scll_trim = 6
 175  * sclh_trim = 6
 176  *
 177  * These are the trim values for standard and fast speed
 178  */
 179 #ifndef I2C_FASTSPEED_SCLL_TRIM
 180 #define I2C_FASTSPEED_SCLL_TRIM         6
 181 #endif
 182 #ifndef I2C_FASTSPEED_SCLH_TRIM
 183 #define I2C_FASTSPEED_SCLH_TRIM         6
 184 #endif
 185
 186 /* These are the trim values for high speed */
 187 #ifndef I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM
 188 #define I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM       I2C_FASTSPEED_SCLL_TRIM
 189 #endif
 190 #ifndef I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM
 191 #define I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM       I2C_FASTSPEED_SCLH_TRIM
 192 #endif
 193 #ifndef I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM
 194 #define I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM       I2C_FASTSPEED_SCLL_TRIM
 195 #endif
 196 #ifndef I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM
 197 #define I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM       I2C_FASTSPEED_SCLH_TRIM
 198 #endif
 199
 200 #define I2C_PSC_MAX             0x0f
 201 #define I2C_PSC_MIN             0x00
 202
 203 #endif /* _I2C_H_ */