include/asm-arm/arch-omap3/mmc_host_def.h

   1 /*
   2  * (C) Copyright 2008
   3  * Texas Instruments, <www.ti.com>
   4  * Syed Mohammed Khasim <khasim@ti.com>
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation's version 2 of
  12  * the License.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 #ifndef MMC_HOST_DEF_H
  26 #define MMC_HOST_DEF_H
  27
  28 /* T2 Register definitions */
  29 #define T2_BASE                 0x48002000
  30
  31 typedef struct t2 {
  32         unsigned char res1[0x274];
  33         unsigned int devconf0;          /* 0x274 */
  34         unsigned char res2[0x2A8];
  35         unsigned int pbias_lite;        /* 0x520 */
  36 } t2_t;
  37
  38 #define MMCSDIO1ADPCLKISEL              (1 << 24)
  39
  40 #define PBIASLITEPWRDNZ0                (1 << 1)
  41 #define PBIASSPEEDCTRL0                 (1 << 2)
  42 #define PBIASLITEPWRDNZ1                (1 << 9)
  43
  44 /*
  45  * OMAP HSMMC register definitions
  46  */
  47 #define OMAP_HSMMC_BASE         0x4809C000
  48
  49 typedef struct hsmmc {
  50         unsigned char res1[0x10];
  51         unsigned int sysconfig;         /* 0x10 */
  52         unsigned int sysstatus;         /* 0x14 */
  53         unsigned char res2[0x14];
  54         unsigned int con;               /* 0x2C */
  55         unsigned char res3[0xD4];
  56         unsigned int blk;               /* 0x104 */
  57         unsigned int arg;               /* 0x108 */
  58         unsigned int cmd;               /* 0x10C */
  59         unsigned int rsp10;             /* 0x110 */
  60         unsigned int rsp32;             /* 0x114 */
  61         unsigned int rsp54;             /* 0x118 */
  62         unsigned int rsp76;             /* 0x11C */
  63         unsigned int data;              /* 0x120 */
  64         unsigned int pstate;            /* 0x124 */
  65         unsigned int hctl;              /* 0x128 */
  66         unsigned int sysctl;            /* 0x12C */
  67         unsigned int stat;              /* 0x130 */
  68         unsigned int ie;                /* 0x134 */
  69         unsigned char res4[0x8];
  70         unsigned int capa;              /* 0x140 */
  71 } hsmmc_t;
  72
  73 /*
  74  * OMAP HS MMC Bit definitions
  75  */
  76 #define MMC_SOFTRESET                   (0x1 << 1)
  77 #define RESETDONE                       (0x1 << 0)
  78 #define NOOPENDRAIN                     (0x0 << 0)
  79 #define OPENDRAIN                       (0x1 << 0)
  80 #define OD                              (0x1 << 0)
  81 #define INIT_NOINIT                     (0x0 << 1)
  82 #define INIT_INITSTREAM                 (0x1 << 1)
  83 #define HR_NOHOSTRESP                   (0x0 << 2)
  84 #define STR_BLOCK                       (0x0 << 3)
  85 #define MODE_FUNC                       (0x0 << 4)
  86 #define DW8_1_4BITMODE                  (0x0 << 5)
  87 #define MIT_CTO                         (0x0 << 6)
  88 #define CDP_ACTIVEHIGH                  (0x0 << 7)
  89 #define WPP_ACTIVEHIGH                  (0x0 << 8)
  90 #define RESERVED_MASK                   (0x3 << 9)
  91 #define CTPL_MMC_SD                     (0x0 << 11)
  92 #define BLEN_512BYTESLEN                (0x200 << 0)
  93 #define NBLK_STPCNT                     (0x0 << 16)
  94 #define DE_DISABLE                      (0x0 << 0)
  95 #define BCE_DISABLE                     (0x0 << 1)
  96 #define ACEN_DISABLE                    (0x0 << 2)
  97 #define DDIR_OFFSET                     (4)
  98 #define DDIR_MASK                       (0x1 << 4)
  99 #define DDIR_WRITE                      (0x0 << 4)
 100 #define DDIR_READ                       (0x1 << 4)
 101 #define MSBS_SGLEBLK                    (0x0 << 5)
 102 #define RSP_TYPE_OFFSET                 (16)
 103 #define RSP_TYPE_MASK                   (0x3 << 16)
 104 #define RSP_TYPE_NORSP                  (0x0 << 16)
 105 #define RSP_TYPE_LGHT136                (0x1 << 16)
 106 #define RSP_TYPE_LGHT48                 (0x2 << 16)
 107 #define RSP_TYPE_LGHT48B                (0x3 << 16)
 108 #define CCCE_NOCHECK                    (0x0 << 19)
 109 #define CCCE_CHECK                      (0x1 << 19)
 110 #define CICE_NOCHECK                    (0x0 << 20)
 111 #define CICE_CHECK                      (0x1 << 20)
 112 #define DP_OFFSET                       (21)
 113 #define DP_MASK                         (0x1 << 21)
 114 #define DP_NO_DATA                      (0x0 << 21)
 115 #define DP_DATA                         (0x1 << 21)
 116 #define CMD_TYPE_NORMAL                 (0x0 << 22)
 117 #define INDEX_OFFSET                    (24)
 118 #define INDEX_MASK                      (0x3f << 24)
 119 #define INDEX(i)                        (i << 24)
 120 #define DATI_MASK                       (0x1 << 1)
 121 #define DATI_CMDDIS                     (0x1 << 1)
 122 #define DTW_1_BITMODE                   (0x0 << 1)
 123 #define DTW_4_BITMODE                   (0x1 << 1)
 124 #define SDBP_PWROFF                     (0x0 << 8)
 125 #define SDBP_PWRON                      (0x1 << 8)
 126 #define SDVS_1V8                        (0x5 << 9)
 127 #define SDVS_3V0                        (0x6 << 9)
 128 #define ICE_MASK                        (0x1 << 0)
 129 #define ICE_STOP                        (0x0 << 0)
 130 #define ICS_MASK                        (0x1 << 1)
 131 #define ICS_NOTREADY                    (0x0 << 1)
 132 #define ICE_OSCILLATE                   (0x1 << 0)
 133 #define CEN_MASK                        (0x1 << 2)
 134 #define CEN_DISABLE                     (0x0 << 2)
 135 #define CEN_ENABLE                      (0x1 << 2)
 136 #define CLKD_OFFSET                     (6)
 137 #define CLKD_MASK                       (0x3FF << 6)
 138 #define DTO_MASK                        (0xF << 16)
 139 #define DTO_15THDTO                     (0xE << 16)
 140 #define SOFTRESETALL                    (0x1 << 24)
 141 #define CC_MASK                         (0x1 << 0)
 142 #define TC_MASK                         (0x1 << 1)
 143 #define BWR_MASK                        (0x1 << 4)
 144 #define BRR_MASK                        (0x1 << 5)
 145 #define ERRI_MASK                       (0x1 << 15)
 146 #define IE_CC                           (0x01 << 0)
 147 #define IE_TC                           (0x01 << 1)
 148 #define IE_BWR                          (0x01 << 4)
 149 #define IE_BRR                          (0x01 << 5)
 150 #define IE_CTO                          (0x01 << 16)
 151 #define IE_CCRC                         (0x01 << 17)
 152 #define IE_CEB                          (0x01 << 18)
 153 #define IE_CIE                          (0x01 << 19)
 154 #define IE_DTO                          (0x01 << 20)
 155 #define IE_DCRC                         (0x01 << 21)
 156 #define IE_DEB                          (0x01 << 22)
 157 #define IE_CERR                         (0x01 << 28)
 158 #define IE_BADA                         (0x01 << 29)
 159
 160 #define VS30_3V0SUP                     (1 << 25)
 161 #define VS18_1V8SUP                     (1 << 26)
 162
 163 /* Driver definitions */
 164 #define MMCSD_SECTOR_SIZE               512
 165 #define MMC_CARD                        0
 166 #define SD_CARD                         1
 167 #define BYTE_MODE                       0
 168 #define SECTOR_MODE                     1
 169 #define CLK_INITSEQ                     0
 170 #define CLK_400KHZ                      1
 171 #define CLK_MISC                        2
 172
 173 typedef struct {
 174         unsigned int card_type;
 175         unsigned int version;
 176         unsigned int mode;
 177         unsigned int size;
 178         unsigned int RCA;
 179 } mmc_card_data;
 180
 181 #define mmc_reg_out(addr, mask, val)\
 182         writel((readl(addr) & (~(mask))) | ((val) & (mask)), (addr))
 183
 184 #endif /* MMC_HOST_DEF_H */