include/asm-arm/arch-s5pc1xx/smc.h

   1 /*
   2  * (C) Copyright 2010 Samsung Electronics
   3  * Naveen Krishna Ch <ch.naveen@samsung.com>
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  *
  20  * Note: This file contains the register description for Memory subsystem
  21  *       (SROM, NAND Flash, OneNand, DDR, OneDRAM) on S5PC1XX.
  22  *
  23  *       Only SROMC is defined as of now
  24  */
  25
  26 #ifndef __ASM_ARCH_SMC_H_
  27 #define __ASM_ARCH_SMC_H_
  28
  29 #define SMC_DATA16_WIDTH(x)    (1<<((x*4)+0))
  30 #define SMC_BYTE_ADDR_MODE(x)  (1<<((x*4)+1))  /* 0-> Half-word base address*/
  31                                                 /* 1-> Byte base address*/
  32 #define SMC_WAIT_ENABLE(x)     (1<<((x*4)+2))
  33 #define SMC_BYTE_ENABLE(x)     (1<<((x*4)+3))
  34
  35 #define SMC_BC_TACS(x) (x << 28) /* 0clk     address set-up */
  36 #define SMC_BC_TCOS(x) (x << 24) /* 4clk     chip selection set-up */
  37 #define SMC_BC_TACC(x) (x << 16) /* 14clk    access cycle */
  38 #define SMC_BC_TCOH(x) (x << 12) /* 1clk     chip selection hold */
  39 #define SMC_BC_TAH(x)  (x << 8)  /* 4clk     address holding time */
  40 #define SMC_BC_TACP(x) (x << 4)  /* 6clk     page mode access cycle */
  41 #define SMC_BC_PMC(x)  (x << 0)  /* normal(1data)page mode configuration */
  42
  43 #ifndef __ASSEMBLY__
  44 struct s5pc1xx_smc {
  45         unsigned int    bw;
  46         unsigned int    bc[6];
  47 };
  48 #endif  /* __ASSEMBLY__ */
  49
  50 /* Configure the Band Width and Bank Control Regs for required SROMC Bank */
  51 void s5pc1xx_config_sromc(u32 srom_bank, u32 smc_bw_conf, u32 smc_bc_conf);
  52
  53 #endif /* __ASM_ARCH_SMC_H_ */