194#define EMAC_TXC_EQ64 0xFFC031C0/* Good TX Frame Count - Byte Count x = 64 */
195#define EMAC_TXC_LT128 0xFFC031C4/* Good TX Frame Count - Byte Count 64 <= x < 128 */
196#define EMAC_TXC_LT256 0xFFC031C8/* Good TX Frame Count - Byte Count 128 <= x < 256 */
197#define EMAC_TXC_LT512 0xFFC031CC/* Good TX Frame Count - Byte Count 256 <= x < 512 */
198#define EMAC_TXC_LT1024 0xFFC031D0/* Good TX Frame Count - Byte Count 512 <= x < 1024 */
199#define EMAC_TXC_GE1024 0xFFC031D4/* Good TX Frame Count - Byte Count x >= 1024 */
200#define EMAC_TXC_ABORT 0xFFC031D8/* Total TX Frames Aborted Count */
201#define USB_FADDR 0xFFC03800/* Function address register */
202#define USB_POWER 0xFFC03804/* Power management register */
203#define USB_INTRTX 0xFFC03808/* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
204#define USB_INTRRX 0xFFC0380C/* Interrupt register for Rx endpoints 1 to 7 */
205#define USB_INTRTXE 0xFFC03810/* Interrupt enable register for IntrTx */
206#define USB_INTRRXE 0xFFC03814/* Interrupt enable register for IntrRx */
207#define USB_INTRUSB 0xFFC03818/* Interrupt register for common USB interrupts */
208#define USB_INTRUSBE 0xFFC0381C/* Interrupt enable register for IntrUSB */
209#define USB_FRAME 0xFFC03820/* USB frame number */
210#define USB_INDEX 0xFFC03824/* Index register for selecting the indexed endpoint registers */
211#define USB_TESTMODE 0xFFC03828/* Enabled USB 20 test modes */
212#define USB_GLOBINTR 0xFFC0382C/* Global Interrupt Mask register and Wakeup Exception Interrupt */
213#define USB_GLOBAL_CTL 0xFFC03830/* Global Clock Control for the core */
214#define USB_TX_MAX_PACKET 0xFFC03840/* Maximum packet size for Host Tx endpoint */
215#define USB_CSR0 0xFFC03844/* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
216#define USB_TXCSR 0xFFC03844/* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
217#define USB_RX_MAX_PACKET 0xFFC03848/* Maximum packet size for Host Rx endpoint */
218#define USB_RXCSR 0xFFC0384C/* Control Status register for Host Rx endpoint */
219#define USB_COUNT0 0xFFC03850/* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
220#define USB_RXCOUNT 0xFFC03850/* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
221#define USB_TXTYPE 0xFFC03854/* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
222#define USB_NAKLIMIT0 0xFFC03858/* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
223#define USB_TXINTERVAL 0xFFC03858/* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
224#define USB_RXTYPE 0xFFC0385C/* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
225#define USB_RXINTERVAL 0xFFC03860/* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
226#define USB_TXCOUNT 0xFFC03868/* Number of bytes to be written to the selected endpoint Tx FIFO */
235#define USB_OTG_DEV_CTL 0xFFC03900/* OTG Device Control Register */
236#define USB_OTG_VBUS_IRQ 0xFFC03904/* OTG VBUS Control Interrupts */
237#define USB_OTG_VBUS_MASK 0xFFC03908/* VBUS Control Interrupt Enable */
238#define USB_LINKINFO 0xFFC03948/* Enables programming of some PHY-side delays */
239#define USB_VPLEN 0xFFC0394C/* Determines duration of VBUS pulse for VBUS charging */
240#define USB_HS_EOF1 0xFFC03950/* Time buffer for High-Speed transactions */
241#define USB_FS_EOF1 0xFFC03954/* Time buffer for Full-Speed transactions */
242#define USB_LS_EOF1 0xFFC03958/* Time buffer for Low-Speed transactions */
243#define USB_APHY_CNTRL 0xFFC039E0/* Register that increases visibility of Analog PHY */
244#define USB_APHY_CALIB 0xFFC039E4/* Register used to set some calibration values */
245#define USB_APHY_CNTRL2 0xFFC039E8/* Register used to prevent re-enumeration once Moab goes into hibernate mode */
246#define USB_PHY_TEST 0xFFC039EC/* Used for reducing simulation time and simplifies FIFO testability */
247#define USB_PLLOSC_CTRL 0xFFC039F0/* Used to program different parameters for USB PLL and Oscillator */
248#define USB_SRP_CLKDIV 0xFFC039F4/* Used to program clock divide value for the clock fed to the SRP detection logic */
249#define USB_EP_NI0_TXMAXP 0xFFC03A00/* Maximum packet size for Host Tx endpoint0 */
250#define USB_EP_NI0_TXCSR 0xFFC03A04/* Control Status register for endpoint 0 */
251#define USB_EP_NI0_RXMAXP 0xFFC03A08/* Maximum packet size for Host Rx endpoint0 */
252#define USB_EP_NI0_RXCSR 0xFFC03A0C/* Control Status register for Host Rx endpoint0 */
253#define USB_EP_NI0_RXCOUNT 0xFFC03A10/* Number of bytes received in endpoint 0 FIFO */
254#define USB_EP_NI0_TXTYPE 0xFFC03A14/* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
255#define USB_EP_NI0_TXINTERVAL 0xFFC03A18/* Sets the NAK response timeout on Endpoint 0 */
256#define USB_EP_NI0_RXTYPE 0xFFC03A1C/* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
257#define USB_EP_NI0_RXINTERVAL 0xFFC03A20/* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
258#define USB_EP_NI0_TXCOUNT 0xFFC03A28/* Number of bytes to be written to the endpoint0 Tx FIFO */
259#define USB_EP_NI1_TXMAXP 0xFFC03A40/* Maximum packet size for Host Tx endpoint1 */
260#define USB_EP_NI1_TXCSR 0xFFC03A44/* Control Status register for endpoint1 */
261#define USB_EP_NI1_RXMAXP 0xFFC03A48/* Maximum packet size for Host Rx endpoint1 */
262#define USB_EP_NI1_RXCSR 0xFFC03A4C/* Control Status register for Host Rx endpoint1 */
263#define USB_EP_NI1_RXCOUNT 0xFFC03A50/* Number of bytes received in endpoint1 FIFO */
264#define USB_EP_NI1_TXTYPE 0xFFC03A54/* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
265#define USB_EP_NI1_TXINTERVAL 0xFFC03A58/* Sets the NAK response timeout on Endpoint1 */
266#define USB_EP_NI1_RXTYPE 0xFFC03A5C/* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
267#define USB_EP_NI1_RXINTERVAL 0xFFC03A60/* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
268#define USB_EP_NI1_TXCOUNT 0xFFC03A68/* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
269#define USB_EP_NI2_TXMAXP 0xFFC03A80/* Maximum packet size for Host Tx endpoint2 */
270#define USB_EP_NI2_TXCSR 0xFFC03A84/* Control Status register for endpoint2 */
271#define USB_EP_NI2_RXMAXP 0xFFC03A88/* Maximum packet size for Host Rx endpoint2 */
272#define USB_EP_NI2_RXCSR 0xFFC03A8C/* Control Status register for Host Rx endpoint2 */
273#define USB_EP_NI2_RXCOUNT 0xFFC03A90/* Number of bytes received in endpoint2 FIFO */
274#define USB_EP_NI2_TXTYPE 0xFFC03A94/* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
275#define USB_EP_NI2_TXINTERVAL 0xFFC03A98/* Sets the NAK response timeout on Endpoint2 */
276#define USB_EP_NI2_RXTYPE 0xFFC03A9C/* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
277#define USB_EP_NI2_RXINTERVAL 0xFFC03AA0/* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
278#define USB_EP_NI2_TXCOUNT 0xFFC03AA8/* Number of bytes to be written to the endpoint2 Tx FIFO */
279#define USB_EP_NI3_TXMAXP 0xFFC03AC0/* Maximum packet size for Host Tx endpoint3 */
280#define USB_EP_NI3_TXCSR 0xFFC03AC4/* Control Status register for endpoint3 */
281#define USB_EP_NI3_RXMAXP 0xFFC03AC8/* Maximum packet size for Host Rx endpoint3 */
282#define USB_EP_NI3_RXCSR 0xFFC03ACC/* Control Status register for Host Rx endpoint3 */
283#define USB_EP_NI3_RXCOUNT 0xFFC03AD0/* Number of bytes received in endpoint3 FIFO */
284#define USB_EP_NI3_TXTYPE 0xFFC03AD4/* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
285#define USB_EP_NI3_TXINTERVAL 0xFFC03AD8/* Sets the NAK response timeout on Endpoint3 */
286#define USB_EP_NI3_RXTYPE 0xFFC03ADC/* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
287#define USB_EP_NI3_RXINTERVAL 0xFFC03AE0/* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
288#define USB_EP_NI3_TXCOUNT 0xFFC03AE8/* Number of bytes to be written to the H124endpoint3 Tx FIFO */
289#define USB_EP_NI4_TXMAXP 0xFFC03B00/* Maximum packet size for Host Tx endpoint4 */
290#define USB_EP_NI4_TXCSR 0xFFC03B04/* Control Status register for endpoint4 */
291#define USB_EP_NI4_RXMAXP 0xFFC03B08/* Maximum packet size for Host Rx endpoint4 */
292#define USB_EP_NI4_RXCSR 0xFFC03B0C/* Control Status register for Host Rx endpoint4 */
293#define USB_EP_NI4_RXCOUNT 0xFFC03B10/* Number of bytes received in endpoint4 FIFO */
294#define USB_EP_NI4_TXTYPE 0xFFC03B14/* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
295#define USB_EP_NI4_TXINTERVAL 0xFFC03B18/* Sets the NAK response timeout on Endpoint4 */
296#define USB_EP_NI4_RXTYPE 0xFFC03B1C/* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
297#define USB_EP_NI4_RXINTERVAL 0xFFC03B20/* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
298#define USB_EP_NI4_TXCOUNT 0xFFC03B28/* Number of bytes to be written to the endpoint4 Tx FIFO */
299#define USB_EP_NI5_TXMAXP 0xFFC03B40/* Maximum packet size for Host Tx endpoint5 */
300#define USB_EP_NI5_TXCSR 0xFFC03B44/* Control Status register for endpoint5 */
301#define USB_EP_NI5_RXMAXP 0xFFC03B48/* Maximum packet size for Host Rx endpoint5 */
302#define USB_EP_NI5_RXCSR 0xFFC03B4C/* Control Status register for Host Rx endpoint5 */
303#define USB_EP_NI5_RXCOUNT 0xFFC03B50/* Number of bytes received in endpoint5 FIFO */
304#define USB_EP_NI5_TXTYPE 0xFFC03B54/* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
305#define USB_EP_NI5_TXINTERVAL 0xFFC03B58/* Sets the NAK response timeout on Endpoint5 */
306#define USB_EP_NI5_RXTYPE 0xFFC03B5C/* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
307#define USB_EP_NI5_RXINTERVAL 0xFFC03B60/* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
308#define USB_EP_NI5_TXCOUNT 0xFFC03B68/* Number of bytes to be written to the endpoint5 Tx FIFO */
309#define USB_EP_NI6_TXMAXP 0xFFC03B80/* Maximum packet size for Host Tx endpoint6 */
310#define USB_EP_NI6_TXCSR 0xFFC03B84/* Control Status register for endpoint6 */
311#define USB_EP_NI6_RXMAXP 0xFFC03B88/* Maximum packet size for Host Rx endpoint6 */
312#define USB_EP_NI6_RXCSR 0xFFC03B8C/* Control Status register for Host Rx endpoint6 */
313#define USB_EP_NI6_RXCOUNT 0xFFC03B90/* Number of bytes received in endpoint6 FIFO */
314#define USB_EP_NI6_TXTYPE 0xFFC03B94/* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
315#define USB_EP_NI6_TXINTERVAL 0xFFC03B98/* Sets the NAK response timeout on Endpoint6 */
316#define USB_EP_NI6_RXTYPE 0xFFC03B9C/* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
317#define USB_EP_NI6_RXINTERVAL 0xFFC03BA0/* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
318#define USB_EP_NI6_TXCOUNT 0xFFC03BA8/* Number of bytes to be written to the endpoint6 Tx FIFO */
319#define USB_EP_NI7_TXMAXP 0xFFC03BC0/* Maximum packet size for Host Tx endpoint7 */
320#define USB_EP_NI7_TXCSR 0xFFC03BC4/* Control Status register for endpoint7 */
321#define USB_EP_NI7_RXMAXP 0xFFC03BC8/* Maximum packet size for Host Rx endpoint7 */
322#define USB_EP_NI7_RXCSR 0xFFC03BCC/* Control Status register for Host Rx endpoint7 */
323#define USB_EP_NI7_RXCOUNT 0xFFC03BD0/* Number of bytes received in endpoint7 FIFO */
324#define USB_EP_NI7_TXTYPE 0xFFC03BD4/* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
325#define USB_EP_NI7_TXINTERVAL 0xFFC03BD8/* Sets the NAK response timeout on Endpoint7 */
326#define USB_EP_NI7_RXTYPE 0xFFC03BDC/* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
327#define USB_EP_NI7_RXINTERVAL 0xFFC03BF0/* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
328#define USB_EP_NI7_TXCOUNT 0xFFC03BF8/* Number of bytes to be written to the endpoint7 Tx FIFO */
329#define USB_DMA_INTERRUPT 0xFFC03C00/* Indicates pending interrupts for the DMA channels */