include/asm-blackfin/mach-common/bits/core.h

   1 /*
   2  * Misc Core Masks
   3  */
   4
   5 #ifndef __BFIN_PERIPHERAL_CORE__
   6 #define __BFIN_PERIPHERAL_CORE__
   7
   8 /*
   9  * EVT registers (ILAT, IMASK, and IPEND).
  10  */
  11
  12 #define EVT_EMU_P               0       /* Emulator interrupt bit position */
  13 #define EVT_RST_P               1       /* Reset interrupt bit position */
  14 #define EVT_NMI_P               2       /* Non Maskable interrupt bit position */
  15 #define EVT_EVX_P               3       /* Exception bit position */
  16 #define EVT_IRPTEN_P            4       /* Global interrupt enable bit position */
  17 #define EVT_IVHW_P              5       /* Hardware Error interrupt bit position */
  18 #define EVT_IVTMR_P             6       /* Timer interrupt bit position */
  19 #define EVT_IVG7_P              7       /* IVG7 interrupt bit position */
  20 #define EVT_IVG8_P              8       /* IVG8 interrupt bit position */
  21 #define EVT_IVG9_P              9       /* IVG9 interrupt bit position */
  22 #define EVT_IVG10_P             10      /* IVG10 interrupt bit position */
  23 #define EVT_IVG11_P             11      /* IVG11 interrupt bit position */
  24 #define EVT_IVG12_P             12      /* IVG12 interrupt bit position */
  25 #define EVT_IVG13_P             13      /* IVG13 interrupt bit position */
  26 #define EVT_IVG14_P             14      /* IVG14 interrupt bit position */
  27 #define EVT_IVG15_P             15      /* IVG15 interrupt bit position */
  28
  29 #define EVT_EMU                 MK_BMSK_(EVT_EMU_P   )  /* Emulator interrupt mask */
  30 #define EVT_RST                 MK_BMSK_(EVT_RST_P   )  /* Reset interrupt mask */
  31 #define EVT_NMI                 MK_BMSK_(EVT_NMI_P   )  /* Non Maskable interrupt mask */
  32 #define EVT_EVX                 MK_BMSK_(EVT_EVX_P   )  /* Exception mask */
  33 #define EVT_IRPTEN              MK_BMSK_(EVT_IRPTEN_P)  /* Global interrupt enable mask */
  34 #define EVT_IVHW                MK_BMSK_(EVT_IVHW_P  )  /* Hardware Error interrupt mask */
  35 #define EVT_IVTMR               MK_BMSK_(EVT_IVTMR_P )  /* Timer interrupt mask */
  36 #define EVT_IVG7                MK_BMSK_(EVT_IVG7_P  )  /* IVG7 interrupt mask */
  37 #define EVT_IVG8                MK_BMSK_(EVT_IVG8_P  )  /* IVG8 interrupt mask */
  38 #define EVT_IVG9                MK_BMSK_(EVT_IVG9_P  )  /* IVG9 interrupt mask */
  39 #define EVT_IVG10               MK_BMSK_(EVT_IVG10_P )  /* IVG10 interrupt mask */
  40 #define EVT_IVG11               MK_BMSK_(EVT_IVG11_P )  /* IVG11 interrupt mask */
  41 #define EVT_IVG12               MK_BMSK_(EVT_IVG12_P )  /* IVG12 interrupt mask */
  42 #define EVT_IVG13               MK_BMSK_(EVT_IVG13_P )  /* IVG13 interrupt mask */
  43 #define EVT_IVG14               MK_BMSK_(EVT_IVG14_P )  /* IVG14 interrupt mask */
  44 #define EVT_IVG15               MK_BMSK_(EVT_IVG15_P )  /* IVG15 interrupt mask */
  45
  46 /*
  47  * SEQSTAT register
  48  */
  49
  50 #define EXCAUSE_P       0       /* Last exception cause bit positions */
  51 #define EXCAUSE0_P      0       /* Last exception cause bit 0 */
  52 #define EXCAUSE1_P      1       /* Last exception cause bit 1 */
  53 #define EXCAUSE2_P      2       /* Last exception cause bit 2 */
  54 #define EXCAUSE3_P      3       /* Last exception cause bit 3 */
  55 #define EXCAUSE4_P      4       /* Last exception cause bit 4 */
  56 #define EXCAUSE5_P      5       /* Last exception cause bit 5 */
  57 #define IDLE_REQ_P      12      /* Pending idle mode request, set by IDLE instruction */
  58 #define SFTRESET_P      13      /* Indicates whether the last reset was a software reset (=1) */
  59 #define HWERRCAUSE_P    14      /* Last hw error cause bit positions */
  60 #define HWERRCAUSE0_P   14      /* Last hw error cause bit 0 */
  61 #define HWERRCAUSE1_P   15      /* Last hw error cause bit 1 */
  62 #define HWERRCAUSE2_P   16      /* Last hw error cause bit 2 */
  63 #define HWERRCAUSE3_P   17      /* Last hw error cause bit 3 */
  64 #define HWERRCAUSE4_P   18      /* Last hw error cause bit 4 */
  65 #define HWERRCAUSE5_P   19      /* Last hw error cause bit 5 */
  66 #define HWERRCAUSE6_P   20      /* Last hw error cause bit 6 */
  67 #define HWERRCAUSE7_P   21      /* Last hw error cause bit 7 */
  68
  69 #define EXCAUSE \
  70         ( MK_BMSK_(EXCAUSE0_P) | \
  71           MK_BMSK_(EXCAUSE1_P) | \
  72           MK_BMSK_(EXCAUSE2_P) | \
  73           MK_BMSK_(EXCAUSE3_P) | \
  74           MK_BMSK_(EXCAUSE4_P) | \
  75           MK_BMSK_(EXCAUSE5_P) )
  76 #define SFTRESET \
  77         ( MK_BMSK_(SFTRESET_P) )
  78 #define HWERRCAUSE \
  79         ( MK_BMSK_(HWERRCAUSE0_P) | \
  80           MK_BMSK_(HWERRCAUSE1_P) | \
  81           MK_BMSK_(HWERRCAUSE2_P) | \
  82           MK_BMSK_(HWERRCAUSE3_P) | \
  83           MK_BMSK_(HWERRCAUSE4_P) )
  84
  85 /* SWRST Masks */
  86 #define SYSTEM_RESET            0x0007          /* Initiates A System Software Reset */
  87 #ifdef __ADSPBF561__
  88 # define DOUBLE_FAULT_A         0x0008
  89 # define DOUBLE_FAULT_B         0x0010
  90 # define DOUBLE_FAULT           0x0018          /* Core [A|B] Double Fault Causes Reset */
  91 # define RESET_DOUBLE_A         0x0800
  92 # define RESET_DOUBLE_B         0x1000
  93 # define RESET_DOUBLE           0x1800          /* SW Reset Generated By Core [A|B] Double-Fault */
  94 # define RESET_WDOG_B           0x2000
  95 # define RESET_WDOG_A           0x4000
  96 # define RESET_WDOG             0x6000          /* SW Reset Generated By Watchdog [A|B] Timer */
  97 #else
  98 # define DOUBLE_FAULT           0x0008          /* Core Double Fault Causes Reset */
  99 # define RESET_DOUBLE           0x2000          /* SW Reset Generated By Core Double-Fault */
 100 # define RESET_WDOG             0x4000          /* SW Reset Generated By Watchdog Timer */
 101 #endif
 102 #define RESET_SOFTWARE          0x8000          /* SW Reset Occurred Since Last Read Of SWRST */
 103
 104 /* SYSCFG Masks */
 105 #define SSSTEP                  0x00000001      /* Supervisor Single Step */
 106 #define CCEN                    0x00000002      /* Cycle Counter Enable */
 107 #define SNEN                    0x00000004      /* Self-Nesting Interrupt Enable */
 108 #define SYSCFG_SSSTEP_P 0
 109 #define SYSCFG_CCEN_P   1
 110 #define SYSCFG_SCEN_P   2
 111
 112 #endif