include/asm-blackfin/mach-common/bits/uart.h

   1 /*
   2  * UART Masks
   3  */
   4
   5 #ifndef __BFIN_PERIPHERAL_UART__
   6 #define __BFIN_PERIPHERAL_UART__
   7
   8 /* UARTx_LCR Masks */
   9 #define WLS                     0x03    /* Word Length Select */
  10 #define WLS_5                   0x00    /* 5 bit word */
  11 #define WLS_6                   0x01    /* 6 bit word */
  12 #define WLS_7                   0x02    /* 7 bit word */
  13 #define WLS_8                   0x03    /* 8 bit word */
  14 #define STB                     0x04    /* Stop Bits */
  15 #define PEN                     0x08    /* Parity Enable */
  16 #define EPS                     0x10    /* Even Parity Select */
  17 #define STP                     0x20    /* Stick Parity */
  18 #define SB                      0x40    /* Set Break */
  19 #define DLAB                    0x80    /* Divisor Latch Access */
  20
  21 #define DLAB_P                  0x07
  22 #define SB_P                    0x06
  23 #define STP_P                   0x05
  24 #define EPS_P                   0x04
  25 #define PEN_P                   0x03
  26 #define STB_P                   0x02
  27 #define WLS_P1                  0x01
  28 #define WLS_P0                  0x00
  29
  30 /* UARTx_MCR Mask */
  31 #define XOFF                    0x01    /* Transmitter off */
  32 #define MRTS                    0x02    /* Manual Request to Send */
  33 #define RFIT                    0x04    /* Receive FIFO IRQ Threshold */
  34 #define RFRT                    0x08    /* Receive FIFO RTS Threshold */
  35 #define LOOP_ENA                0x10    /* Loopback Mode Enable */
  36 #define FCPOL                   0x20    /* Flow Control Pin Polarity */
  37 #define ARTS                    0x40    /* Auto RTS generation for RX handshake */
  38 #define ACTS                    0x80    /* Auto CTS operation for TX handshake */
  39
  40 #define XOFF_P                  0
  41 #define MRTS_P                  1
  42 #define RFIT_P                  2
  43 #define RFRT_P                  3
  44 #define LOOP_ENA_P              4
  45 #define FCPOL_P                 5
  46 #define ARTS_P                  6
  47 #define ACTS_P                  7
  48
  49 /* UARTx_LSR Masks */
  50 #define DR                      0x01    /* Data Ready */
  51 #define OE                      0x02    /* Overrun Error */
  52 #define PE                      0x04    /* Parity Error */
  53 #define FE                      0x08    /* Framing Error */
  54 #define BI                      0x10    /* Break Interrupt */
  55 #define THRE                    0x20    /* THR Empty */
  56 #define TEMT                    0x40    /* TSR and UART_THR Empty */
  57
  58 #define DR_P                    0x00
  59 #define OE_P                    0x01
  60 #define PE_P                    0x02
  61 #define FE_P                    0x03
  62 #define BI_P                    0x04
  63 #define THRE_P                  0x05
  64 #define TEMT_P                  0x06
  65
  66 /* UARTx_IER Masks */
  67 #define ERBFI                   0x01    /* Enable Receive Buffer Full Interrupt */
  68 #define ETBEI                   0x02    /* Enable Transmit Buffer Empty Interrupt */
  69 #define ELSI                    0x04    /* Enable RX Status Interrupt */
  70
  71 #define ERBFI_P                 0x00
  72 #define ETBEI_P                 0x01
  73 #define ELSI_P                  0x02
  74
  75 /* UARTx_IIR Masks */
  76 #define NINT                    0x01    /* Pending Interrupt */
  77 #define STATUS                  0x06    /* Highest Priority Pending Interrupt */
  78
  79 #define NINT_P                  0x00
  80 #define STATUS_P0               0x01
  81 #define STATUS_P1               0x02
  82
  83 /* UARTx_GCTL Masks */
  84 #define UCEN                    0x01    /* Enable UARTx Clocks */
  85 #define IREN                    0x02    /* Enable IrDA Mode */
  86 #define TPOLC                   0x04    /* IrDA TX Polarity Change */
  87 #define RPOLC                   0x08    /* IrDA RX Polarity Change */
  88 #define FPE                     0x10    /* Force Parity Error On Transmit */
  89 #define FFE                     0x20    /* Force Framing Error On Transmit */
  90
  91 #define UCEN_P                  0x00
  92 #define IREN_P                  0x01
  93 #define TPOLC_P                 0x02
  94 #define RPOLC_P                 0x03
  95 #define FPE_P                   0x04
  96 #define FFE_P                   0x05
  97
  98 #endif