include/asm-m68k/coldfire/pwm.h

   1 /*
   2  * Pulse Width Modulation Memory Map
   3  *
   4  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 #ifndef __ATA_H__
  27 #define __ATA_H__
  28
  29 /* Pulse Width Modulation (PWM) */
  30 typedef struct pwm_ctrl {
  31 #ifdef CONFIG_M5272
  32         u8 cr0;
  33         u8 res1[3];
  34         u8 cr1;
  35         u8 res2[3];
  36         u8 cr2;
  37         u8 res3[7];
  38         u8 pwr0;
  39         u8 res4[3];
  40         u8 pwr1;
  41         u8 res5[3];
  42         u8 pwr2;
  43         u8 res6[7];
  44 #else
  45         u8 en;                  /* 0x00 PWM Enable */
  46         u8 pol;                 /* 0x01 Polarity */
  47         u8 clk;                 /* 0x02 Clock Select */
  48         u8 prclk;               /* 0x03 Prescale Clock Select */
  49         u8 cae;                 /* 0x04 Center Align Enable */
  50         u8 ctl;                 /* 0x05 Control */
  51         u16 res1;               /* 0x06 - 0x07 */
  52         u8 scla;                /* 0x08 Scale A */
  53         u8 sclb;                /* 0x09 Scale B */
  54         u16 res2;               /* 0x0A - 0x0B */
  55 #ifdef CONFIG_M5275
  56         u8 cnt[4];              /* 0x0C Channel n Counter */
  57         u16 res3;               /* 0x10 - 0x11 */
  58         u8 per[4];              /* 0x14 Channel n Period */
  59         u16 res4;               /* 0x16 - 0x17 */
  60         u8 dty[4];              /* 0x18 Channel n Duty */
  61 #else
  62         u8 cnt[8];              /* 0x0C Channel n Counter */
  63         u8 per[8];              /* 0x14 Channel n Period */
  64         u8 dty[8];              /* 0x1C Channel n Duty */
  65         u8 sdn;                 /* 0x24 Shutdown */
  66         u8 res3[3];             /* 0x25 - 0x27 */
  67 #endif                          /* CONFIG_M5275 */
  68 #endif                          /* CONFIG_M5272 */
  69 } pwm_t;
  70
  71 #ifdef CONFIG_M5272
  72
  73 #define PWM_CR_EN                       (0x80)
  74 #define PWM_CR_FRC1                     (0x40)
  75 #define PWM_CR_LVL                      (0x20)
  76 #define PWM_CR_CLKSEL(x)                ((x) & 0x0F)
  77 #define PWM_CR_CLKSEL_MASK              (0xF0)
  78
  79 #else
  80
  81 #define PWM_EN_PWMEn(x)                 (1 << ((x) & 0x07))
  82 #define PWM_EN_PWMEn_MASK               (0xF0)
  83
  84 #define PWM_POL_PPOLn(x)                (1 << ((x) & 0x07))
  85 #define PWM_POL_PPOLn_MASK              (0xF0)
  86
  87 #define PWM_CLK_PCLKn(x)                (1 << ((x) & 0x07))
  88 #define PWM_CLK_PCLKn_MASK              (0xF0)
  89
  90 #define PWM_PRCLK_PCKB(x)               (((x) & 0x07) << 4)
  91 #define PWM_PRCLK_PCKB_MASK             (0x8F)
  92 #define PWM_PRCLK_PCKA(x)               ((x) & 0x07)
  93 #define PWM_PRCLK_PCKA_MASK             (0xF8)
  94
  95 #define PWM_CLK_PCLKn(x)                (1 << ((x) & 0x07))
  96 #define PWM_CLK_PCLKn_MASK              (0xF0)
  97
  98 #define PWM_CTL_CON67                   (0x80)
  99 #define PWM_CTL_CON45                   (0x40)
 100 #define PWM_CTL_CON23                   (0x20)
 101 #define PWM_CTL_CON01                   (0x10)
 102 #define PWM_CTL_PSWAR                   (0x08)
 103 #define PWM_CTL_PFRZ                    (0x04)
 104
 105 #define PWM_SDN_IF                      (0x80)
 106 #define PWM_SDN_IE                      (0x40)
 107 #define PWM_SDN_RESTART                 (0x20)
 108 #define PWM_SDN_LVL                     (0x10)
 109 #define PWM_SDN_PWM7IN                  (0x04)
 110 #define PWM_SDN_PWM7IL                  (0x02)
 111 #define PWM_SDN_SDNEN                   (0x01)
 112
 113 #endif                          /* CONFIG_M5272 */
 114
 115 #endif                          /* __ATA_H__ */