include/asm-ppc/hymod.h

   1 #ifndef _ASM_HYMOD_H_
   2 #define _ASM_HYMOD_H_
   3
   4 #include <linux/config.h>
   5 #ifdef CONFIG_8260
   6 #include <asm/iopin_8260.h>
   7 #endif
   8
   9 /*
  10  * hymod configuration data - passed by boot code via the board information
  11  * structure (only U-Boot has support for this at the moment)
  12  *
  13  * there are three types of data passed up from the boot monitor. the first
  14  * (type hymod_eeprom_t) is the eeprom data that was read off both the main
  15  * (or mother) board and the mezzanine board (if any). this data defines how
  16  * many Xilinx fpgas are on each board, and their types (among other things).
  17  * the second type of data (type xlx_mmap_t, one per Xilinx fpga) defines where
  18  * in the physical address space the various Xilinx fpga access regions have
  19  * been mapped by the boot rom. the third type of data (type xlx_iopins_t,
  20  * one per Xilinx fpga) defines which io port pins are connected to the various
  21  * signals required to program a Xilinx fpga.
  22  *
  23  * A ram/flash "bank" refers to memory controlled by the same chip select.
  24  *
  25  * the eeprom contents are defined as in technical note #2 - basically,
  26  * a header, zero or more records in no particular order, and a 32 bit crc
  27  * a record is 1 or more type bytes, a length byte and "length" bytes.
  28  */
  29
  30 #define HYMOD_EEPROM_ID         0xAA    /* eeprom id byte */
  31 #define HYMOD_EEPROM_VER        1       /* eeprom contents version */
  32 #define HYMOD_EEPROM_SIZE       256     /* number of bytes in the eeprom */
  33
  34 /* eeprom header */
  35 typedef
  36     struct {
  37         unsigned char id;               /* eeprom id byte */
  38         unsigned char ver;              /* eeprom contents version number */
  39         unsigned long len;              /* total # of bytes btw hdr and crc */
  40     }
  41 hymod_eehdr_t;
  42
  43 /* maximum number of bytes available for eeprom data records */
  44 #define HYMOD_EEPROM_MAXLEN     (HYMOD_EEPROM_SIZE \
  45                                         - sizeof (hymod_eehdr_t) \
  46                                         - sizeof (unsigned long))
  47
  48 /* eeprom data record */
  49 typedef
  50     union {
  51         struct {
  52             unsigned char topbit:1;
  53             unsigned char type:7;
  54             unsigned char len;
  55             unsigned char data[1];      /* variable length */
  56         } small;
  57         struct {
  58             unsigned short topbit:1;
  59             unsigned short nxtbit:1;
  60             unsigned short type:14;
  61             unsigned short len;
  62             unsigned char data[1];      /* variable length */
  63         } medium;
  64         struct {
  65             unsigned long topbit:1;
  66             unsigned long nxtbit:1;
  67             unsigned long type:30;
  68             unsigned long len;
  69             unsigned char data[1];      /* variable length */
  70         } large;
  71     }
  72 hymod_eerec_t;
  73
  74 #define HYMOD_EEOFF_MAIN        0x00    /* i2c addr offset for main eeprom */
  75 #define HYMOD_EEOFF_MEZZ        0x04    /* i2c addr offset for mezz eepomr */
  76
  77 /* eeprom record types */
  78 #define HYMOD_EEREC_SERNO       1       /* serial number */
  79 #define HYMOD_EEREC_DATE        2       /* date */
  80 #define HYMOD_EEREC_BATCH       3       /* batch id */
  81 #define HYMOD_EEREC_TYPE        4       /* board type */
  82 #define HYMOD_EEREC_REV         5       /* revision number */
  83 #define HYMOD_EEREC_SDRAM       6       /* sdram sizes */
  84 #define HYMOD_EEREC_FLASH       7       /* flash sizes */
  85 #define HYMOD_EEREC_ZBT         8       /* zbt ram sizes */
  86 #define HYMOD_EEREC_XLXTYP      9       /* Xilinx fpga types */
  87 #define HYMOD_EEREC_XLXSPD      10      /* Xilinx fpga speeds */
  88 #define HYMOD_EEREC_XLXTMP      11      /* Xilinx fpga temperatures */
  89 #define HYMOD_EEREC_XLXGRD      12      /* Xilinx fpga grades */
  90 #define HYMOD_EEREC_CPUTYP      13      /* Motorola CPU type */
  91 #define HYMOD_EEREC_CPUSPD      14      /* CPU speed */
  92 #define HYMOD_EEREC_BUSSPD      15      /* bus speed */
  93 #define HYMOD_EEREC_CPMSPD      16      /* CPM speed */
  94 #define HYMOD_EEREC_HSTYPE      17      /* high-speed serial chip type */
  95 #define HYMOD_EEREC_HSCHIN      18      /* high-speed serial input channels */
  96 #define HYMOD_EEREC_HSCHOUT     19      /* high-speed serial output channels */
  97
  98 /* some dimensions */
  99 #define HYMOD_MAX_BATCH         32      /* max no. of bytes in batch id */
 100 #define HYMOD_MAX_SDRAM         4       /* max sdram "banks" on any board */
 101 #define HYMOD_MAX_FLASH         4       /* max flash "banks" on any board */
 102 #define HYMOD_MAX_ZBT           16      /* max ZBT rams on any board */
 103 #define HYMOD_MAX_XLX           4       /* max Xilinx fpgas on any board */
 104
 105 #define HYMOD_MAX_BYTES         16      /* enough to store any bytes array */
 106
 107 /* board types */
 108 #define HYMOD_BDTYPE_NONE       0       /* information not present */
 109 #define HYMOD_BDTYPE_IO         1       /* I/O main board */
 110 #define HYMOD_BDTYPE_CLP        2       /* CLP main board */
 111 #define HYMOD_BDTYPE_DSP        3       /* DSP main board */
 112 #define HYMOD_BDTYPE_INPUT      4       /* video input mezzanine board */
 113 #define HYMOD_BDTYPE_ALTINPUT   5       /* video input mezzanine board */
 114 #define HYMOD_BDTYPE_DISPLAY    6       /* video display mezzanine board */
 115 #define HYMOD_BDTYPE_MAX        7       /* first invalid value */
 116
 117 /* Xilinx fpga types */
 118 #define HYMOD_XTYP_NONE         0       /* information not present */
 119 #define HYMOD_XTYP_XCV300E      1       /* Xilinx Virtex 300 */
 120 #define HYMOD_XTYP_XCV400E      2       /* Xilinx Virtex 400 */
 121 #define HYMOD_XTYP_XCV600E      3       /* Xilinx Virtex 600 */
 122 #define HYMOD_XTYP_MAX          4       /* first invalid value */
 123
 124 /* Xilinx fpga speeds */
 125 #define HYMOD_XSPD_NONE         0       /* information not present */
 126 #define HYMOD_XSPD_SIX          1
 127 #define HYMOD_XSPD_SEVEN        2
 128 #define HYMOD_XSPD_EIGHT        3
 129 #define HYMOD_XSPD_MAX          4       /* first invalid value */
 130
 131 /* Xilinx fpga temperatures */
 132 #define HYMOD_XTMP_NONE         0       /* information not present */
 133 #define HYMOD_XTMP_COM          1
 134 #define HYMOD_XTMP_IND          2
 135 #define HYMOD_XTMP_MAX          3       /* first invalid value */
 136
 137 /* Xilinx fpga grades */
 138 #define HYMOD_XTMP_NONE         0       /* information not present */
 139 #define HYMOD_XTMP_NORMAL       1
 140 #define HYMOD_XTMP_ENGSAMP      2
 141 #define HYMOD_XTMP_MAX          3       /* first invalid value */
 142
 143 /* CPU types */
 144 #define HYMOD_CPUTYPE_NONE      0       /* information not present */
 145 #define HYMOD_CPUTYPE_MPC8260   1       /* Motorola MPC8260 embedded powerpc */
 146 #define HYMOD_CPUTYPE_MAX       2       /* first invalid value */
 147
 148 /* CPU/BUS/CPM clock speeds */
 149 #define HYMOD_CLKSPD_NONE       0       /* information not present */
 150 #define HYMOD_CLKSPD_33MHZ      1
 151 #define HYMOD_CLKSPD_66MHZ      2
 152 #define HYMOD_CLKSPD_100MHZ     3
 153 #define HYMOD_CLKSPD_133MHZ     4
 154 #define HYMOD_CLKSPD_166MHZ     5
 155 #define HYMOD_CLKSPD_200MHZ     6
 156 #define HYMOD_CLKSPD_MAX        7       /* first invalid value */
 157
 158 /* high speed serial chip types */
 159 #define HYMOD_HSSTYPE_NONE      0       /* information not present */
 160 #define HYMOD_HSSTYPE_AMCC52064 1
 161 #define HYMOD_HSSTYPE_MAX       2       /* first invalid value */
 162
 163 /* a date (yyyy-mm-dd) */
 164 typedef
 165     struct {
 166         unsigned short year;
 167         unsigned char month;
 168         unsigned char day;
 169     }
 170 hymod_date_t;
 171
 172 /* describes a Xilinx fpga */
 173 typedef
 174     struct {
 175         unsigned char type;             /* chip type */
 176         unsigned char speed;            /* chip speed rating */
 177         unsigned char temp;             /* chip temperature rating */
 178         unsigned char grade;            /* chip grade */
 179     }
 180 hymod_xlx_t;
 181
 182 /* describes a Motorola embedded processor */
 183 typedef
 184     struct {
 185         unsigned char type;             /* CPU type */
 186         unsigned char cpuspd;           /* speed of the PowerPC core */
 187         unsigned char busspd;           /* speed of the system and 60x bus */
 188         unsigned char cpmspd;           /* speed of the CPM co-processor */
 189     }
 190 hymod_mpc_t;
 191
 192 /* info about high-speed (1Gbit) serial interface */
 193 typedef
 194     struct {
 195         unsigned char type;             /* high-speed serial chip type */
 196         unsigned char nchin;            /* number of input channels mounted */
 197         unsigned char nchout;           /* number of output channels mounted */
 198     }
 199 hymod_hss_t;
 200
 201 /*
 202  * this defines the contents of the serial eeprom that exists on every
 203  * hymod board, including mezzanine boards (the serial eeprom will be
 204  * faked for early development boards that don't have one)
 205  */
 206
 207 typedef
 208     struct {
 209         unsigned char ver;              /* eeprom contents version */
 210         unsigned char bdtype;           /* board type */
 211         unsigned char bdrev;            /* board revision */
 212         unsigned char batchlen;         /* length of batch string below */
 213         unsigned long serno;            /* serial number */
 214         hymod_date_t date;              /* manufacture date */
 215         unsigned char batch[32];        /* manufacturer specific batch id */
 216         unsigned char nsdram;           /* # of ram "banks" */
 217         unsigned char nflash;           /* # of flash "banks" */
 218         unsigned char nzbt;             /* # of ZBT rams */
 219         unsigned char nxlx;             /* # of Xilinx fpgas */
 220         unsigned char sdramsz[HYMOD_MAX_SDRAM]; /* log2 of sdram size */
 221         unsigned char flashsz[HYMOD_MAX_FLASH]; /* log2 of flash size */
 222         unsigned char zbtsz[HYMOD_MAX_ZBT];     /* log2 of ZBT ram size */
 223         hymod_xlx_t xlx[HYMOD_MAX_XLX]; /* Xilinx fpga info */
 224         hymod_mpc_t mpc;                /* Motorola MPC CPU info */
 225         hymod_hss_t hss;                /* high-speed serial info */
 226     }
 227 hymod_eeprom_t;
 228
 229 /*
 230  * this defines a region in the processor's physical address space
 231  */
 232 typedef
 233     struct {
 234         unsigned long exists:1;         /* 1 if the region exists, 0 if not */
 235         unsigned long size:31;          /* size in bytes */
 236         unsigned long base;             /* base address */
 237     }
 238 xlx_prgn_t;
 239
 240 /*
 241  * this defines where the various Xilinx fpga access regions are mapped
 242  * into the physical address space of the processor
 243  */
 244 typedef
 245     struct {
 246         xlx_prgn_t prog;                /* program access region */
 247         xlx_prgn_t reg;                 /* register access region */
 248         xlx_prgn_t port;                /* port access region */
 249     }
 250 xlx_mmap_t;
 251
 252 /*
 253  * this defines which 8260 i/o port pins are connected to the various
 254  * signals required for programming a Xilinx fpga
 255  */
 256 typedef
 257     struct {
 258         iopin_t prog_pin;               /* assert for >= 300ns to program */
 259         iopin_t init_pin;               /* goes high when fpga is cleared */
 260         iopin_t done_pin;               /* goes high when program is done */
 261         iopin_t enable_pin;             /* some fpgas need enabling */
 262     }
 263 xlx_iopins_t;
 264
 265 /* all info about one hymod board */
 266 typedef
 267     struct {
 268         unsigned char eeprom_valid:1;
 269         hymod_eeprom_t eeprom;
 270         xlx_mmap_t mmap[HYMOD_MAX_XLX];
 271         xlx_iopins_t iopins[HYMOD_MAX_XLX];
 272     }
 273 hymod_board_t;
 274
 275 /*
 276  * this defines the configuration information of a hymod board-set
 277  * (main board + possible mezzanine board). In future, there may be
 278  * more than one mezzanine board (stackable?) - if so, add a "mezz2"
 279  * field, and so on... or make mezz an array?
 280  */
 281 typedef
 282     struct {
 283         hymod_board_t main;             /* main board info */
 284         hymod_board_t mezz;             /* mezzanine board info */
 285         unsigned long crc;              /* ensures kernel and boot prom agree */
 286     }
 287 hymod_conf_t;
 288
 289 #endif /* _ASM_HYMOD_H_ */