include/asm-sh/cpu_sh7785.h

   1 #ifndef _ASM_CPU_SH7785_H_
   2 #define _ASM_CPU_SH7785_H_
   3
   4 /*
   5  * Copyright (c) 2007,2008 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
   6  * Copyright (c) 2008 Yusuke Goda <goda.yusuke@renesas.com>
   7  * Copyright (c) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  *
  24  */
  25
  26 #define CACHE_OC_NUM_WAYS       1
  27 #define CCR_CACHE_INIT          0x0000090b
  28
  29 /*      Exceptions      */
  30 #define TRA             0xFF000020
  31 #define EXPEVT  0xFF000024
  32 #define INTEVT  0xFF000028
  33
  34 /* Cache Controller */
  35 #define CCR     0xFF00001C
  36 #define QACR0   0xFF000038
  37 #define QACR1   0xFF00003C
  38 #define RAMCR   0xFF000074
  39
  40 /* Watchdog Timer and Reset */
  41 #define WTCNT   WDTCNT
  42 #define WDTST   0xFFCC0000
  43 #define WDTCSR  0xFFCC0004
  44 #define WDTBST  0xFFCC0008
  45 #define WDTCNT  0xFFCC0010
  46 #define WDTBCNT 0xFFCC0018
  47
  48 /* Timer Unit */
  49 #define TSTR    TSTR0
  50 #define TOCR    0xFFD80000
  51 #define TSTR0   0xFFD80004
  52 #define TCOR0   0xFFD80008
  53 #define TCNT0   0xFFD8000C
  54 #define TCR0    0xFFD80010
  55 #define TCOR1   0xFFD80014
  56 #define TCNT1   0xFFD80018
  57 #define TCR1    0xFFD8001C
  58 #define TCOR2   0xFFD80020
  59 #define TCNT2   0xFFD80024
  60 #define TCR2    0xFFD80028
  61 #define TCPR2   0xFFD8002C
  62 #define TSTR1   0xFFDC0004
  63 #define TCOR3   0xFFDC0008
  64 #define TCNT3   0xFFDC000C
  65 #define TCR3    0xFFDC0010
  66 #define TCOR4   0xFFDC0014
  67 #define TCNT4   0xFFDC0018
  68 #define TCR4    0xFFDC001C
  69 #define TCOR5   0xFFDC0020
  70 #define TCNT5   0xFFDC0024
  71 #define TCR5    0xFFDC0028
  72
  73 /* Serial Communication Interface with FIFO */
  74 #define SCIF1_BASE      0xffeb0000
  75
  76 /* LBSC */
  77 #define MMSELR          0xfc400020
  78 #define LBSC_BASE       0xff800000
  79 #define BCR             (LBSC_BASE + 0x1000)
  80 #define CS0BCR          (LBSC_BASE + 0x2000)
  81 #define CS1BCR          (LBSC_BASE + 0x2010)
  82 #define CS2BCR          (LBSC_BASE + 0x2020)
  83 #define CS3BCR          (LBSC_BASE + 0x2030)
  84 #define CS4BCR          (LBSC_BASE + 0x2040)
  85 #define CS5BCR          (LBSC_BASE + 0x2050)
  86 #define CS6BCR          (LBSC_BASE + 0x2060)
  87 #define CS0WCR          (LBSC_BASE + 0x2008)
  88 #define CS1WCR          (LBSC_BASE + 0x2018)
  89 #define CS2WCR          (LBSC_BASE + 0x2028)
  90 #define CS3WCR          (LBSC_BASE + 0x2038)
  91 #define CS4WCR          (LBSC_BASE + 0x2048)
  92 #define CS5WCR          (LBSC_BASE + 0x2058)
  93 #define CS6WCR          (LBSC_BASE + 0x2068)
  94 #define CS5PCR          (LBSC_BASE + 0x2070)
  95 #define CS6PCR          (LBSC_BASE + 0x2080)
  96
  97 /* PCI  Controller */
  98 #define SH7780_PCIECR           0xFE000008
  99 #define SH7780_PCIVID           0xFE040000
 100 #define SH7780_PCIDID           0xFE040002
 101 #define SH7780_PCICMD           0xFE040004
 102 #define SH7780_PCISTATUS        0xFE040006
 103 #define SH7780_PCIRID           0xFE040008
 104 #define SH7780_PCIPIF           0xFE040009
 105 #define SH7780_PCISUB           0xFE04000A
 106 #define SH7780_PCIBCC           0xFE04000B
 107 #define SH7780_PCICLS           0xFE04000C
 108 #define SH7780_PCILTM           0xFE04000D
 109 #define SH7780_PCIHDR           0xFE04000E
 110 #define SH7780_PCIBIST          0xFE04000F
 111 #define SH7780_PCIIBAR          0xFE040010
 112 #define SH7780_PCIMBAR0         0xFE040014
 113 #define SH7780_PCIMBAR1         0xFE040018
 114 #define SH7780_PCISVID          0xFE04002C
 115 #define SH7780_PCISID           0xFE04002E
 116 #define SH7780_PCICP            0xFE040034
 117 #define SH7780_PCIINTLINE       0xFE04003C
 118 #define SH7780_PCIINTPIN        0xFE04003D
 119 #define SH7780_PCIMINGNT        0xFE04003E
 120 #define SH7780_PCIMAXLAT        0xFE04003F
 121 #define SH7780_PCICID           0xFE040040
 122 #define SH7780_PCINIP           0xFE040041
 123 #define SH7780_PCIPMC           0xFE040042
 124 #define SH7780_PCIPMCSR         0xFE040044
 125 #define SH7780_PCIPMCSRBSE      0xFE040046
 126 #define SH7780_PCI_CDD          0xFE040047
 127 #define SH7780_PCICR            0xFE040100
 128 #define SH7780_PCILSR0          0xFE040104
 129 #define SH7780_PCILSR1          0xFE040108
 130 #define SH7780_PCILAR0          0xFE04010C
 131 #define SH7780_PCILAR1          0xFE040110
 132 #define SH7780_PCIIR            0xFE040114
 133 #define SH7780_PCIIMR           0xFE040118
 134 #define SH7780_PCIAIR           0xFE04011C
 135 #define SH7780_PCICIR           0xFE040120
 136 #define SH7780_PCIAINT          0xFE040130
 137 #define SH7780_PCIAINTM         0xFE040134
 138 #define SH7780_PCIBMIR          0xFE040138
 139 #define SH7780_PCIPAR           0xFE0401C0
 140 #define SH7780_PCIPINT          0xFE0401CC
 141 #define SH7780_PCIPINTM         0xFE0401D0
 142 #define SH7780_PCIMBR0          0xFE0401E0
 143 #define SH7780_PCIMBMR0         0xFE0401E4
 144 #define SH7780_PCIMBR1          0xFE0401E8
 145 #define SH7780_PCIMBMR1         0xFE0401EC
 146 #define SH7780_PCIMBR2          0xFE0401F0
 147 #define SH7780_PCIMBMR2         0xFE0401F4
 148 #define SH7780_PCIIOBR          0xFE0401F8
 149 #define SH7780_PCIIOBMR         0xFE0401FC
 150 #define SH7780_PCICSCR0         0xFE040210
 151 #define SH7780_PCICSCR1         0xFE040214
 152 #define SH7780_PCICSAR0         0xFE040218
 153 #define SH7780_PCICSAR1         0xFE04021C
 154 #define SH7780_PCIPDR           0xFE040220
 155
 156 #endif  /* _ASM_CPU_SH7780_H_ */