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1 /* SPARC Processor specifics
2 * taken from the SPARC port of Linux (ptrace.h).
5 * Daniel Hellstrom, Gaisler Research, daniel@gaisler.com.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
24 #ifndef __ASM_SPARC_PROCESSOR_H
25 #define __ASM_SPARC_PROCESSOR_H
27 #include <asm/arch/asi.h>
31 /* All LEON processors supported */
35 /* other processors */
36 #error Unknown SPARC Processor
41 /* flush data cache */
42 static __inline__
void sparc_dcache_flush_all(void)
44 __asm__
__volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_DFLUSH
):"memory");
47 /* flush instruction cache */
48 static __inline__
void sparc_icache_flush_all(void)
50 __asm__
__volatile__("sta %%g0, [%%g0] %0\n\t"::"i"(ASI_IFLUSH
):"memory");
53 /* do a cache miss load */
54 static __inline__
unsigned long long sparc_load_reg_cachemiss_qword(unsigned
57 unsigned long long retval
;
58 __asm__
__volatile__("ldda [%1] %2, %0\n\t":
59 "=r"(retval
):"r"(paddr
), "i"(ASI_CACHEMISS
));
63 static __inline__
unsigned long sparc_load_reg_cachemiss(unsigned long paddr
)
66 __asm__
__volatile__("lda [%1] %2, %0\n\t":
67 "=r"(retval
):"r"(paddr
), "i"(ASI_CACHEMISS
));
71 static __inline__
unsigned short sparc_load_reg_cachemiss_word(unsigned long
74 unsigned short retval
;
75 __asm__
__volatile__("lduha [%1] %2, %0\n\t":
76 "=r"(retval
):"r"(paddr
), "i"(ASI_CACHEMISS
));
80 static __inline__
unsigned char sparc_load_reg_cachemiss_byte(unsigned long
84 __asm__
__volatile__("lduba [%1] %2, %0\n\t":
85 "=r"(retval
):"r"(paddr
), "i"(ASI_CACHEMISS
));
89 /* do a physical address bypass write, i.e. for 0x80000000 */
90 static __inline__
void sparc_store_reg_bypass(unsigned long paddr
,
93 __asm__
__volatile__("sta %0, [%1] %2\n\t"::"r"(value
), "r"(paddr
),
94 "i"(ASI_BYPASS
):"memory");
97 static __inline__
unsigned long sparc_load_reg_bypass(unsigned long paddr
)
100 __asm__
__volatile__("lda [%1] %2, %0\n\t":
101 "=r"(retval
):"r"(paddr
), "i"(ASI_BYPASS
));
105 /* Macros for bypassing cache when reading */
106 #define SPARC_NOCACHE_READ_DWORD(address) sparc_load_reg_cachemiss_qword((unsigned int)(address))
107 #define SPARC_NOCACHE_READ(address) sparc_load_reg_cachemiss((unsigned int)(address))
108 #define SPARC_NOCACHE_READ_HWORD(address) sparc_load_reg_cachemiss_word((unsigned int)(address))
109 #define SPARC_NOCACHE_READ_BYTE(address) sparc_load_reg_cachemiss_byte((unsigned int)(address))
111 #define SPARC_BYPASS_READ(address) sparc_load_reg_bypass((unsigned int)(address))
112 #define SPARC_BYPASS_WRITE(address,value) sparc_store_reg_bypass((unsigned int)(address),(unsigned int)(value))
116 #endif /* __ASM_SPARC_PROCESSOR_H */