include/commproc.h

   1 /*
   2  * MPC8xx Communication Processor Module.
   3  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
   4  *
   5  * (C) Copyright 2000-2006
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * This file contains structures and information for the communication
   9  * processor channels.  Some CPM control and status is available
  10  * through the MPC8xx internal memory map.  See immap.h for details.
  11  * This file only contains what I need for the moment, not the total
  12  * CPM capabilities.  I (or someone else) will add definitions as they
  13  * are needed.  -- Dan
  14  *
  15  */
  16 #ifndef __CPM_8XX__
  17 #define __CPM_8XX__
  18
  19 #include <asm/8xx_immap.h>
  20
  21 /* CPM Command register.
  22 */
  23 #define CPM_CR_RST              ((ushort)0x8000)
  24 #define CPM_CR_OPCODE           ((ushort)0x0f00)
  25 #define CPM_CR_CHAN             ((ushort)0x00f0)
  26 #define CPM_CR_FLG              ((ushort)0x0001)
  27
  28 /* Some commands (there are more...later)
  29 */
  30 #define CPM_CR_INIT_TRX         ((ushort)0x0000)
  31 #define CPM_CR_INIT_RX          ((ushort)0x0001)
  32 #define CPM_CR_INIT_TX          ((ushort)0x0002)
  33 #define CPM_CR_HUNT_MODE        ((ushort)0x0003)
  34 #define CPM_CR_STOP_TX          ((ushort)0x0004)
  35 #define CPM_CR_RESTART_TX       ((ushort)0x0006)
  36 #define CPM_CR_SET_GADDR        ((ushort)0x0008)
  37
  38 /* Channel numbers.
  39 */
  40 #define CPM_CR_CH_SCC1          ((ushort)0x0000)
  41 #define CPM_CR_CH_I2C           ((ushort)0x0001)    /* I2C and IDMA1 */
  42 #define CPM_CR_CH_SCC2          ((ushort)0x0004)
  43 #define CPM_CR_CH_SPI           ((ushort)0x0005)    /* SPI/IDMA2/Timers */
  44 #define CPM_CR_CH_SCC3          ((ushort)0x0008)
  45 #define CPM_CR_CH_SMC1          ((ushort)0x0009)    /* SMC1 / DSP1 */
  46 #define CPM_CR_CH_SCC4          ((ushort)0x000c)
  47 #define CPM_CR_CH_SMC2          ((ushort)0x000d)    /* SMC2 / DSP2 */
  48
  49 #define mk_cr_cmd(CH, CMD)      ((CMD << 8) | (CH << 4))
  50
  51 /*
  52  * DPRAM defines and allocation functions
  53  */
  54 #define CPM_SERIAL_BASE         0x0800
  55 #define CPM_I2C_BASE            0x0820
  56 #define CPM_SPI_BASE            0x0840
  57 #define CPM_FEC_BASE            0x0860
  58 #define CPM_SERIAL2_BASE        0x08E0
  59 #define CPM_SCC_BASE            0x0900
  60 #define CPM_POST_BASE           0x0980
  61 #define CPM_WLKBD_BASE          0x0a00
  62
  63 #define BD_IIC_START    ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
  64
  65 /* Export the base address of the communication processor registers
  66  * and dual port ram.
  67  */
  68 extern  cpm8xx_t        *cpmp;          /* Pointer to comm processor */
  69
  70 /* Buffer descriptors used by many of the CPM protocols.
  71 */
  72 typedef struct cpm_buf_desc {
  73         ushort  cbd_sc;         /* Status and Control */
  74         ushort  cbd_datlen;     /* Data length in buffer */
  75         uint    cbd_bufaddr;    /* Buffer address in host memory */
  76 } cbd_t;
  77
  78 #define BD_SC_EMPTY     ((ushort)0x8000)        /* Receive is empty */
  79 #define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
  80 #define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor */
  81 #define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
  82 #define BD_SC_LAST      ((ushort)0x0800)        /* Last buffer in frame */
  83 #define BD_SC_TC        ((ushort)0x0400)        /* Transmit CRC */
  84 #define BD_SC_CM        ((ushort)0x0200)        /* Continuous mode */
  85 #define BD_SC_ID        ((ushort)0x0100)        /* Rec'd too many idles */
  86 #define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
  87 #define BD_SC_BR        ((ushort)0x0020)        /* Break received */
  88 #define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
  89 #define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
  90 #define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
  91 #define BD_SC_CD        ((ushort)0x0001)        /* Carrier Detect lost */
  92
  93 /* Parameter RAM offsets.
  94 */
  95 #define PROFF_SCC1      ((uint)0x0000)
  96 #define PROFF_IIC       ((uint)0x0080)
  97 #define PROFF_REVNUM    ((uint)0x00b0)
  98 #define PROFF_SCC2      ((uint)0x0100)
  99 #define PROFF_SPI       ((uint)0x0180)
 100 #define PROFF_SCC3      ((uint)0x0200)
 101 #define PROFF_SMC1      ((uint)0x0280)
 102 #define PROFF_SCC4      ((uint)0x0300)
 103 #define PROFF_SMC2      ((uint)0x0380)
 104
 105 /* Define enough so I can at least use the serial port as a UART.
 106  */
 107 typedef struct smc_uart {
 108         ushort  smc_rbase;      /* Rx Buffer descriptor base address */
 109         ushort  smc_tbase;      /* Tx Buffer descriptor base address */
 110         u_char  smc_rfcr;       /* Rx function code */
 111         u_char  smc_tfcr;       /* Tx function code */
 112         ushort  smc_mrblr;      /* Max receive buffer length */
 113         uint    smc_rstate;     /* Internal */
 114         uint    smc_idp;        /* Internal */
 115         ushort  smc_rbptr;      /* Internal */
 116         ushort  smc_ibc;        /* Internal */
 117         uint    smc_rxtmp;      /* Internal */
 118         uint    smc_tstate;     /* Internal */
 119         uint    smc_tdp;        /* Internal */
 120         ushort  smc_tbptr;      /* Internal */
 121         ushort  smc_tbc;        /* Internal */
 122         uint    smc_txtmp;      /* Internal */
 123         ushort  smc_maxidl;     /* Maximum idle characters */
 124         ushort  smc_tmpidl;     /* Temporary idle counter */
 125         ushort  smc_brklen;     /* Last received break length */
 126         ushort  smc_brkec;      /* rcv'd break condition counter */
 127         ushort  smc_brkcr;      /* xmt break count register */
 128         ushort  smc_rmask;      /* Temporary bit mask */
 129         u_char  res1[8];
 130         ushort  smc_rpbase;     /* Relocation pointer */
 131 } smc_uart_t;
 132
 133 /* Function code bits.
 134 */
 135 #define SMC_EB  ((u_char)0x10)  /* Set big endian byte order */
 136
 137 /* SMC uart mode register.
 138 */
 139 #define SMCMR_REN       ((ushort)0x0001)
 140 #define SMCMR_TEN       ((ushort)0x0002)
 141 #define SMCMR_DM        ((ushort)0x000c)
 142 #define SMCMR_SM_GCI    ((ushort)0x0000)
 143 #define SMCMR_SM_UART   ((ushort)0x0020)
 144 #define SMCMR_SM_TRANS  ((ushort)0x0030)
 145 #define SMCMR_SM_MASK   ((ushort)0x0030)
 146 #define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
 147 #define SMCMR_REVD      SMCMR_PM_EVEN
 148 #define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
 149 #define SMCMR_BS        SMCMR_PEN
 150 #define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
 151 #define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
 152 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
 153
 154 /* SMC2 as Centronics parallel printer.  It is half duplex, in that
 155  * it can only receive or transmit.  The parameter ram values for
 156  * each direction are either unique or properly overlap, so we can
 157  * include them in one structure.
 158  */
 159 typedef struct smc_centronics {
 160         ushort  scent_rbase;
 161         ushort  scent_tbase;
 162         u_char  scent_cfcr;
 163         u_char  scent_smask;
 164         ushort  scent_mrblr;
 165         uint    scent_rstate;
 166         uint    scent_r_ptr;
 167         ushort  scent_rbptr;
 168         ushort  scent_r_cnt;
 169         uint    scent_rtemp;
 170         uint    scent_tstate;
 171         uint    scent_t_ptr;
 172         ushort  scent_tbptr;
 173         ushort  scent_t_cnt;
 174         uint    scent_ttemp;
 175         ushort  scent_max_sl;
 176         ushort  scent_sl_cnt;
 177         ushort  scent_character1;
 178         ushort  scent_character2;
 179         ushort  scent_character3;
 180         ushort  scent_character4;
 181         ushort  scent_character5;
 182         ushort  scent_character6;
 183         ushort  scent_character7;
 184         ushort  scent_character8;
 185         ushort  scent_rccm;
 186         ushort  scent_rccr;
 187 } smc_cent_t;
 188
 189 /* Centronics Status Mask Register.
 190 */
 191 #define SMC_CENT_F      ((u_char)0x08)
 192 #define SMC_CENT_PE     ((u_char)0x04)
 193 #define SMC_CENT_S      ((u_char)0x02)
 194
 195 /* SMC Event and Mask register.
 196 */
 197 #define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
 198 #define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
 199 #define SMCM_TXE        ((unsigned char)0x10)   /* When in Transparent Mode */
 200 #define SMCM_BSY        ((unsigned char)0x04)
 201 #define SMCM_TX         ((unsigned char)0x02)
 202 #define SMCM_RX         ((unsigned char)0x01)
 203
 204 /* Baud rate generators.
 205 */
 206 #define CPM_BRG_RST             ((uint)0x00020000)
 207 #define CPM_BRG_EN              ((uint)0x00010000)
 208 #define CPM_BRG_EXTC_INT        ((uint)0x00000000)
 209 #define CPM_BRG_EXTC_CLK2       ((uint)0x00004000)
 210 #define CPM_BRG_EXTC_CLK6       ((uint)0x00008000)
 211 #define CPM_BRG_ATB             ((uint)0x00002000)
 212 #define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
 213 #define CPM_BRG_DIV16           ((uint)0x00000001)
 214
 215 /* SI Clock Route Register
 216 */
 217 #define SICR_RCLK_SCC1_BRG1     ((uint)0x00000000)
 218 #define SICR_TCLK_SCC1_BRG1     ((uint)0x00000000)
 219 #define SICR_RCLK_SCC2_BRG2     ((uint)0x00000800)
 220 #define SICR_TCLK_SCC2_BRG2     ((uint)0x00000100)
 221 #define SICR_RCLK_SCC3_BRG3     ((uint)0x00100000)
 222 #define SICR_TCLK_SCC3_BRG3     ((uint)0x00020000)
 223 #define SICR_RCLK_SCC4_BRG4     ((uint)0x18000000)
 224 #define SICR_TCLK_SCC4_BRG4     ((uint)0x03000000)
 225
 226 /* SCCs.
 227 */
 228 #define SCC_GSMRH_IRP           ((uint)0x00040000)
 229 #define SCC_GSMRH_GDE           ((uint)0x00010000)
 230 #define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
 231 #define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
 232 #define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
 233 #define SCC_GSMRH_REVD          ((uint)0x00002000)
 234 #define SCC_GSMRH_TRX           ((uint)0x00001000)
 235 #define SCC_GSMRH_TTX           ((uint)0x00000800)
 236 #define SCC_GSMRH_CDP           ((uint)0x00000400)
 237 #define SCC_GSMRH_CTSP          ((uint)0x00000200)
 238 #define SCC_GSMRH_CDS           ((uint)0x00000100)
 239 #define SCC_GSMRH_CTSS          ((uint)0x00000080)
 240 #define SCC_GSMRH_TFL           ((uint)0x00000040)
 241 #define SCC_GSMRH_RFW           ((uint)0x00000020)
 242 #define SCC_GSMRH_TXSY          ((uint)0x00000010)
 243 #define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
 244 #define SCC_GSMRH_SYNL8         ((uint)0x00000008)
 245 #define SCC_GSMRH_SYNL4         ((uint)0x00000004)
 246 #define SCC_GSMRH_RTSM          ((uint)0x00000002)
 247 #define SCC_GSMRH_RSYN          ((uint)0x00000001)
 248
 249 #define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
 250 #define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
 251 #define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
 252 #define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
 253 #define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
 254 #define SCC_GSMRL_TCI           ((uint)0x10000000)
 255 #define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
 256 #define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
 257 #define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
 258 #define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
 259 #define SCC_GSMRL_RINV          ((uint)0x02000000)
 260 #define SCC_GSMRL_TINV          ((uint)0x01000000)
 261 #define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
 262 #define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
 263 #define SCC_GSMRL_TPL_48        ((uint)0x00800000)
 264 #define SCC_GSMRL_TPL_32        ((uint)0x00600000)
 265 #define SCC_GSMRL_TPL_16        ((uint)0x00400000)
 266 #define SCC_GSMRL_TPL_8         ((uint)0x00200000)
 267 #define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
 268 #define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
 269 #define SCC_GSMRL_TPP_01        ((uint)0x00100000)
 270 #define SCC_GSMRL_TPP_10        ((uint)0x00080000)
 271 #define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
 272 #define SCC_GSMRL_TEND          ((uint)0x00040000)
 273 #define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
 274 #define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
 275 #define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
 276 #define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
 277 #define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
 278 #define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
 279 #define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
 280 #define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
 281 #define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
 282 #define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
 283 #define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
 284 #define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
 285 #define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
 286 #define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
 287 #define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
 288 #define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
 289 #define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
 290 #define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
 291 #define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
 292 #define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
 293 #define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
 294 #define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
 295 #define SCC_GSMRL_ENR           ((uint)0x00000020)
 296 #define SCC_GSMRL_ENT           ((uint)0x00000010)
 297 #define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
 298 #define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
 299 #define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
 300 #define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
 301 #define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
 302 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
 303 #define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
 304 #define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
 305 #define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
 306 #define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
 307
 308 #define SCC_TODR_TOD            ((ushort)0x8000)
 309
 310 /* SCC Event and Mask register.
 311 */
 312 #define SCCM_TXE        ((unsigned char)0x10)
 313 #define SCCM_BSY        ((unsigned char)0x04)
 314 #define SCCM_TX         ((unsigned char)0x02)
 315 #define SCCM_RX         ((unsigned char)0x01)
 316
 317 typedef struct scc_param {
 318         ushort  scc_rbase;      /* Rx Buffer descriptor base address */
 319         ushort  scc_tbase;      /* Tx Buffer descriptor base address */
 320         u_char  scc_rfcr;       /* Rx function code */
 321         u_char  scc_tfcr;       /* Tx function code */
 322         ushort  scc_mrblr;      /* Max receive buffer length */
 323         uint    scc_rstate;     /* Internal */
 324         uint    scc_idp;        /* Internal */
 325         ushort  scc_rbptr;      /* Internal */
 326         ushort  scc_ibc;        /* Internal */
 327         uint    scc_rxtmp;      /* Internal */
 328         uint    scc_tstate;     /* Internal */
 329         uint    scc_tdp;        /* Internal */
 330         ushort  scc_tbptr;      /* Internal */
 331         ushort  scc_tbc;        /* Internal */
 332         uint    scc_txtmp;      /* Internal */
 333         uint    scc_rcrc;       /* Internal */
 334         uint    scc_tcrc;       /* Internal */
 335 } sccp_t;
 336
 337 /* Function code bits.
 338 */
 339 #define SCC_EB  ((u_char)0x10)  /* Set big endian byte order */
 340
 341 /* CPM Ethernet through SCCx.
 342  */
 343 typedef struct scc_enet {
 344         sccp_t  sen_genscc;
 345         uint    sen_cpres;      /* Preset CRC */
 346         uint    sen_cmask;      /* Constant mask for CRC */
 347         uint    sen_crcec;      /* CRC Error counter */
 348         uint    sen_alec;       /* alignment error counter */
 349         uint    sen_disfc;      /* discard frame counter */
 350         ushort  sen_pads;       /* Tx short frame pad character */
 351         ushort  sen_retlim;     /* Retry limit threshold */
 352         ushort  sen_retcnt;     /* Retry limit counter */
 353         ushort  sen_maxflr;     /* maximum frame length register */
 354         ushort  sen_minflr;     /* minimum frame length register */
 355         ushort  sen_maxd1;      /* maximum DMA1 length */
 356         ushort  sen_maxd2;      /* maximum DMA2 length */
 357         ushort  sen_maxd;       /* Rx max DMA */
 358         ushort  sen_dmacnt;     /* Rx DMA counter */
 359         ushort  sen_maxb;       /* Max BD byte count */
 360         ushort  sen_gaddr1;     /* Group address filter */
 361         ushort  sen_gaddr2;
 362         ushort  sen_gaddr3;
 363         ushort  sen_gaddr4;
 364         uint    sen_tbuf0data0; /* Save area 0 - current frame */
 365         uint    sen_tbuf0data1; /* Save area 1 - current frame */
 366         uint    sen_tbuf0rba;   /* Internal */
 367         uint    sen_tbuf0crc;   /* Internal */
 368         ushort  sen_tbuf0bcnt;  /* Internal */
 369         ushort  sen_paddrh;     /* physical address (MSB) */
 370         ushort  sen_paddrm;
 371         ushort  sen_paddrl;     /* physical address (LSB) */
 372         ushort  sen_pper;       /* persistence */
 373         ushort  sen_rfbdptr;    /* Rx first BD pointer */
 374         ushort  sen_tfbdptr;    /* Tx first BD pointer */
 375         ushort  sen_tlbdptr;    /* Tx last BD pointer */
 376         uint    sen_tbuf1data0; /* Save area 0 - current frame */
 377         uint    sen_tbuf1data1; /* Save area 1 - current frame */
 378         uint    sen_tbuf1rba;   /* Internal */
 379         uint    sen_tbuf1crc;   /* Internal */
 380         ushort  sen_tbuf1bcnt;  /* Internal */
 381         ushort  sen_txlen;      /* Tx Frame length counter */
 382         ushort  sen_iaddr1;     /* Individual address filter */
 383         ushort  sen_iaddr2;
 384         ushort  sen_iaddr3;
 385         ushort  sen_iaddr4;
 386         ushort  sen_boffcnt;    /* Backoff counter */
 387
 388         /* NOTE: Some versions of the manual have the following items
 389          * incorrectly documented.  Below is the proper order.
 390          */
 391         ushort  sen_taddrh;     /* temp address (MSB) */
 392         ushort  sen_taddrm;
 393         ushort  sen_taddrl;     /* temp address (LSB) */
 394 } scc_enet_t;
 395
 396 /*********************************************************************/
 397
 398 /* SCC Event register as used by Ethernet.
 399 */
 400 #define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
 401 #define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
 402 #define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
 403 #define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
 404 #define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
 405 #define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
 406
 407 /* SCC Mode Register (PSMR) as used by Ethernet.
 408 */
 409 #define SCC_PSMR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
 410 #define SCC_PSMR_FC     ((ushort)0x4000)        /* Force collision */
 411 #define SCC_PSMR_RSH    ((ushort)0x2000)        /* Receive short frames */
 412 #define SCC_PSMR_IAM    ((ushort)0x1000)        /* Check individual hash */
 413 #define SCC_PSMR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
 414 #define SCC_PSMR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
 415 #define SCC_PSMR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
 416 #define SCC_PSMR_SBT    ((ushort)0x0080)        /* Special backoff timer */
 417 #define SCC_PSMR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
 418 #define SCC_PSMR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
 419 #define SCC_PSMR_LCW    ((ushort)0x0010)        /* Late collision window */
 420 #define SCC_PSMR_NIB22  ((ushort)0x000a)        /* Start frame search */
 421 #define SCC_PSMR_FDE    ((ushort)0x0001)        /* Full duplex enable */
 422
 423 /* Buffer descriptor control/status used by Ethernet receive.
 424 */
 425 #define BD_ENET_RX_EMPTY        ((ushort)0x8000)
 426 #define BD_ENET_RX_WRAP         ((ushort)0x2000)
 427 #define BD_ENET_RX_INTR         ((ushort)0x1000)
 428 #define BD_ENET_RX_LAST         ((ushort)0x0800)
 429 #define BD_ENET_RX_FIRST        ((ushort)0x0400)
 430 #define BD_ENET_RX_MISS         ((ushort)0x0100)
 431 #define BD_ENET_RX_LG           ((ushort)0x0020)
 432 #define BD_ENET_RX_NO           ((ushort)0x0010)
 433 #define BD_ENET_RX_SH           ((ushort)0x0008)
 434 #define BD_ENET_RX_CR           ((ushort)0x0004)
 435 #define BD_ENET_RX_OV           ((ushort)0x0002)
 436 #define BD_ENET_RX_CL           ((ushort)0x0001)
 437 #define BD_ENET_RX_STATS        ((ushort)0x013f)        /* All status bits */
 438
 439 /* Buffer descriptor control/status used by Ethernet transmit.
 440 */
 441 #define BD_ENET_TX_READY        ((ushort)0x8000)
 442 #define BD_ENET_TX_PAD          ((ushort)0x4000)
 443 #define BD_ENET_TX_WRAP         ((ushort)0x2000)
 444 #define BD_ENET_TX_INTR         ((ushort)0x1000)
 445 #define BD_ENET_TX_LAST         ((ushort)0x0800)
 446 #define BD_ENET_TX_TC           ((ushort)0x0400)
 447 #define BD_ENET_TX_DEF          ((ushort)0x0200)
 448 #define BD_ENET_TX_HB           ((ushort)0x0100)
 449 #define BD_ENET_TX_LC           ((ushort)0x0080)
 450 #define BD_ENET_TX_RL           ((ushort)0x0040)
 451 #define BD_ENET_TX_RCMASK       ((ushort)0x003c)
 452 #define BD_ENET_TX_UN           ((ushort)0x0002)
 453 #define BD_ENET_TX_CSL          ((ushort)0x0001)
 454 #define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */
 455
 456 /* SCC as UART
 457 */
 458 typedef struct scc_uart {
 459         sccp_t  scc_genscc;
 460         uint    scc_res1;       /* Reserved */
 461         uint    scc_res2;       /* Reserved */
 462         ushort  scc_maxidl;     /* Maximum idle chars */
 463         ushort  scc_idlc;       /* temp idle counter */
 464         ushort  scc_brkcr;      /* Break count register */
 465         ushort  scc_parec;      /* receive parity error counter */
 466         ushort  scc_frmec;      /* receive framing error counter */
 467         ushort  scc_nosec;      /* receive noise counter */
 468         ushort  scc_brkec;      /* receive break condition counter */
 469         ushort  scc_brkln;      /* last received break length */
 470         ushort  scc_uaddr1;     /* UART address character 1 */
 471         ushort  scc_uaddr2;     /* UART address character 2 */
 472         ushort  scc_rtemp;      /* Temp storage */
 473         ushort  scc_toseq;      /* Transmit out of sequence char */
 474         ushort  scc_char1;      /* control character 1 */
 475         ushort  scc_char2;      /* control character 2 */
 476         ushort  scc_char3;      /* control character 3 */
 477         ushort  scc_char4;      /* control character 4 */
 478         ushort  scc_char5;      /* control character 5 */
 479         ushort  scc_char6;      /* control character 6 */
 480         ushort  scc_char7;      /* control character 7 */
 481         ushort  scc_char8;      /* control character 8 */
 482         ushort  scc_rccm;       /* receive control character mask */
 483         ushort  scc_rccr;       /* receive control character register */
 484         ushort  scc_rlbc;       /* receive last break character */
 485 } scc_uart_t;
 486
 487 /* SCC Event and Mask registers when it is used as a UART.
 488 */
 489 #define UART_SCCM_GLR           ((ushort)0x1000)
 490 #define UART_SCCM_GLT           ((ushort)0x0800)
 491 #define UART_SCCM_AB            ((ushort)0x0200)
 492 #define UART_SCCM_IDL           ((ushort)0x0100)
 493 #define UART_SCCM_GRA           ((ushort)0x0080)
 494 #define UART_SCCM_BRKE          ((ushort)0x0040)
 495 #define UART_SCCM_BRKS          ((ushort)0x0020)
 496 #define UART_SCCM_CCR           ((ushort)0x0008)
 497 #define UART_SCCM_BSY           ((ushort)0x0004)
 498 #define UART_SCCM_TX            ((ushort)0x0002)
 499 #define UART_SCCM_RX            ((ushort)0x0001)
 500
 501 /* The SCC PSMR when used as a UART.
 502 */
 503 #define SCU_PSMR_FLC            ((ushort)0x8000)
 504 #define SCU_PSMR_SL             ((ushort)0x4000)
 505 #define SCU_PSMR_CL             ((ushort)0x3000)
 506 #define SCU_PSMR_UM             ((ushort)0x0c00)
 507 #define SCU_PSMR_FRZ            ((ushort)0x0200)
 508 #define SCU_PSMR_RZS            ((ushort)0x0100)
 509 #define SCU_PSMR_SYN            ((ushort)0x0080)
 510 #define SCU_PSMR_DRT            ((ushort)0x0040)
 511 #define SCU_PSMR_PEN            ((ushort)0x0010)
 512 #define SCU_PSMR_RPM            ((ushort)0x000c)
 513 #define SCU_PSMR_REVP           ((ushort)0x0008)
 514 #define SCU_PSMR_TPM            ((ushort)0x0003)
 515 #define SCU_PSMR_TEVP           ((ushort)0x0003)
 516
 517 /* CPM Transparent mode SCC.
 518  */
 519 typedef struct scc_trans {
 520         sccp_t  st_genscc;
 521         uint    st_cpres;       /* Preset CRC */
 522         uint    st_cmask;       /* Constant mask for CRC */
 523 } scc_trans_t;
 524
 525 #define BD_SCC_TX_LAST          ((ushort)0x0800)
 526
 527 /* IIC parameter RAM.
 528 */
 529 typedef struct iic {
 530         ushort  iic_rbase;      /* Rx Buffer descriptor base address */
 531         ushort  iic_tbase;      /* Tx Buffer descriptor base address */
 532         u_char  iic_rfcr;       /* Rx function code */
 533         u_char  iic_tfcr;       /* Tx function code */
 534         ushort  iic_mrblr;      /* Max receive buffer length */
 535         uint    iic_rstate;     /* Internal */
 536         uint    iic_rdp;        /* Internal */
 537         ushort  iic_rbptr;      /* Internal */
 538         ushort  iic_rbc;        /* Internal */
 539         uint    iic_rxtmp;      /* Internal */
 540         uint    iic_tstate;     /* Internal */
 541         uint    iic_tdp;        /* Internal */
 542         ushort  iic_tbptr;      /* Internal */
 543         ushort  iic_tbc;        /* Internal */
 544         uint    iic_txtmp;      /* Internal */
 545         uint    iic_res;        /* reserved */
 546         ushort  iic_rpbase;     /* Relocation pointer */
 547         ushort  iic_res2;       /* reserved */
 548 } iic_t;
 549
 550 /* SPI parameter RAM.
 551 */
 552 typedef struct spi {
 553         ushort  spi_rbase;      /* Rx Buffer descriptor base address */
 554         ushort  spi_tbase;      /* Tx Buffer descriptor base address */
 555         u_char  spi_rfcr;       /* Rx function code */
 556         u_char  spi_tfcr;       /* Tx function code */
 557         ushort  spi_mrblr;      /* Max receive buffer length */
 558         uint    spi_rstate;     /* Internal */
 559         uint    spi_rdp;        /* Internal */
 560         ushort  spi_rbptr;      /* Internal */
 561         ushort  spi_rbc;        /* Internal */
 562         uint    spi_rxtmp;      /* Internal */
 563         uint    spi_tstate;     /* Internal */
 564         uint    spi_tdp;        /* Internal */
 565         ushort  spi_tbptr;      /* Internal */
 566         ushort  spi_tbc;        /* Internal */
 567         uint    spi_txtmp;      /* Internal */
 568         uint    spi_res;
 569         ushort  spi_rpbase;     /* Relocation pointer */
 570         ushort  spi_res2;
 571 } spi_t;
 572
 573 /* SPI Mode register.
 574 */
 575 #define SPMODE_LOOP     ((ushort)0x4000)        /* Loopback */
 576 #define SPMODE_CI       ((ushort)0x2000)        /* Clock Invert */
 577 #define SPMODE_CP       ((ushort)0x1000)        /* Clock Phase */
 578 #define SPMODE_DIV16    ((ushort)0x0800)        /* BRG/16 mode */
 579 #define SPMODE_REV      ((ushort)0x0400)        /* Reversed Data */
 580 #define SPMODE_MSTR     ((ushort)0x0200)        /* SPI Master */
 581 #define SPMODE_EN       ((ushort)0x0100)        /* Enable */
 582 #define SPMODE_LENMSK   ((ushort)0x00f0)        /* character length */
 583 #define SPMODE_PMMSK    ((ushort)0x000f)        /* prescale modulus */
 584
 585 #define SPMODE_LEN(x)   ((((x) - 1) & 0xF) << 4)
 586 #define SPMODE_PM(x)    ((x) & 0xF)
 587
 588 /* HDLC parameter RAM.
 589 */
 590
 591 typedef struct hdlc_pram_s {
 592         /*
 593          * SCC parameter RAM
 594          */
 595         ushort  rbase;          /* Rx Buffer descriptor base address */
 596         ushort  tbase;          /* Tx Buffer descriptor base address */
 597         uchar   rfcr;           /* Rx function code */
 598         uchar   tfcr;           /* Tx function code */
 599         ushort  mrblr;          /* Rx buffer length */
 600         ulong   rstate;         /* Rx internal state */
 601         ulong   rptr;           /* Rx internal data pointer */
 602         ushort  rbptr;          /* rb BD Pointer */
 603         ushort  rcount;         /* Rx internal byte count */
 604         ulong   rtemp;          /* Rx temp */
 605         ulong   tstate;         /* Tx internal state */
 606         ulong   tptr;           /* Tx internal data pointer */
 607         ushort  tbptr;          /* Tx BD pointer */
 608         ushort  tcount;         /* Tx byte count */
 609         ulong   ttemp;          /* Tx temp */
 610         ulong   rcrc;           /* temp receive CRC */
 611         ulong   tcrc;           /* temp transmit CRC */
 612         /*
 613          * HDLC specific parameter RAM
 614          */
 615         uchar   res[4];         /* reserved */
 616         ulong   c_mask;         /* CRC constant */
 617         ulong   c_pres;         /* CRC preset */
 618         ushort  disfc;          /* discarded frame counter */
 619         ushort  crcec;          /* CRC error counter */
 620         ushort  abtsc;          /* abort sequence counter */
 621         ushort  nmarc;          /* nonmatching address rx cnt */
 622         ushort  retrc;          /* frame retransmission cnt */
 623         ushort  mflr;           /* maximum frame length reg */
 624         ushort  max_cnt;        /* maximum length counter */
 625         ushort  rfthr;          /* received frames threshold */
 626         ushort  rfcnt;          /* received frames count */
 627         ushort  hmask;          /* user defined frm addr mask */
 628         ushort  haddr1;         /* user defined frm address 1 */
 629         ushort  haddr2;         /* user defined frm address 2 */
 630         ushort  haddr3;         /* user defined frm address 3 */
 631         ushort  haddr4;         /* user defined frm address 4 */
 632         ushort  tmp;            /* temp */
 633         ushort  tmp_mb;         /* temp */
 634 } hdlc_pram_t;
 635
 636 /* CPM interrupts.  There are nearly 32 interrupts generated by CPM
 637  * channels or devices.  All of these are presented to the PPC core
 638  * as a single interrupt.  The CPM interrupt handler dispatches its
 639  * own handlers, in a similar fashion to the PPC core handler.  We
 640  * use the table as defined in the manuals (i.e. no special high
 641  * priority and SCC1 == SCCa, etc...).
 642  */
 643 #define CPMVEC_NR               32
 644 #define CPMVEC_OFFSET           0x00010000
 645 #define CPMVEC_PIO_PC15         ((ushort)0x1f | CPMVEC_OFFSET)
 646 #define CPMVEC_SCC1             ((ushort)0x1e | CPMVEC_OFFSET)
 647 #define CPMVEC_SCC2             ((ushort)0x1d | CPMVEC_OFFSET)
 648 #define CPMVEC_SCC3             ((ushort)0x1c | CPMVEC_OFFSET)
 649 #define CPMVEC_SCC4             ((ushort)0x1b | CPMVEC_OFFSET)
 650 #define CPMVEC_PIO_PC14         ((ushort)0x1a | CPMVEC_OFFSET)
 651 #define CPMVEC_TIMER1           ((ushort)0x19 | CPMVEC_OFFSET)
 652 #define CPMVEC_PIO_PC13         ((ushort)0x18 | CPMVEC_OFFSET)
 653 #define CPMVEC_PIO_PC12         ((ushort)0x17 | CPMVEC_OFFSET)
 654 #define CPMVEC_SDMA_CB_ERR      ((ushort)0x16 | CPMVEC_OFFSET)
 655 #define CPMVEC_IDMA1            ((ushort)0x15 | CPMVEC_OFFSET)
 656 #define CPMVEC_IDMA2            ((ushort)0x14 | CPMVEC_OFFSET)
 657 #define CPMVEC_TIMER2           ((ushort)0x12 | CPMVEC_OFFSET)
 658 #define CPMVEC_RISCTIMER        ((ushort)0x11 | CPMVEC_OFFSET)
 659 #define CPMVEC_I2C              ((ushort)0x10 | CPMVEC_OFFSET)
 660 #define CPMVEC_PIO_PC11         ((ushort)0x0f | CPMVEC_OFFSET)
 661 #define CPMVEC_PIO_PC10         ((ushort)0x0e | CPMVEC_OFFSET)
 662 #define CPMVEC_TIMER3           ((ushort)0x0c | CPMVEC_OFFSET)
 663 #define CPMVEC_PIO_PC9          ((ushort)0x0b | CPMVEC_OFFSET)
 664 #define CPMVEC_PIO_PC8          ((ushort)0x0a | CPMVEC_OFFSET)
 665 #define CPMVEC_PIO_PC7          ((ushort)0x09 | CPMVEC_OFFSET)
 666 #define CPMVEC_TIMER4           ((ushort)0x07 | CPMVEC_OFFSET)
 667 #define CPMVEC_PIO_PC6          ((ushort)0x06 | CPMVEC_OFFSET)
 668 #define CPMVEC_SPI              ((ushort)0x05 | CPMVEC_OFFSET)
 669 #define CPMVEC_SMC1             ((ushort)0x04 | CPMVEC_OFFSET)
 670 #define CPMVEC_SMC2             ((ushort)0x03 | CPMVEC_OFFSET)
 671 #define CPMVEC_PIO_PC5          ((ushort)0x02 | CPMVEC_OFFSET)
 672 #define CPMVEC_PIO_PC4          ((ushort)0x01 | CPMVEC_OFFSET)
 673 #define CPMVEC_ERROR            ((ushort)0x00 | CPMVEC_OFFSET)
 674
 675 void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
 676
 677 /* CPM interrupt configuration vector.
 678 */
 679 #define CICR_SCD_SCC4           ((uint)0x00c00000)      /* SCC4 @ SCCd */
 680 #define CICR_SCC_SCC3           ((uint)0x00200000)      /* SCC3 @ SCCc */
 681 #define CICR_SCB_SCC2           ((uint)0x00040000)      /* SCC2 @ SCCb */
 682 #define CICR_SCA_SCC1           ((uint)0x00000000)      /* SCC1 @ SCCa */
 683 #define CICR_IRL_MASK           ((uint)0x0000e000)      /* Core interrupt */
 684 #define CICR_HP_MASK            ((uint)0x00001f00)      /* Hi-pri int. */
 685 #define CICR_IEN                ((uint)0x00000080)      /* Int. enable */
 686 #define CICR_SPS                ((uint)0x00000001)      /* SCC Spread */
 687 #endif /* __CPM_8XX__ */