include/commproc.h

   1 /*
   2  * MPC8xx Communication Processor Module.
   3  * Copyright (c) 1997 Dan Malek (dmalek@jlc.net)
   4  *
   5  * This file contains structures and information for the communication
   6  * processor channels.  Some CPM control and status is available
   7  * throught the MPC8xx internal memory map.  See immap.h for details.
   8  * This file only contains what I need for the moment, not the total
   9  * CPM capabilities.  I (or someone else) will add definitions as they
  10  * are needed.  -- Dan
  11  *
  12  * On the MBX board, EPPC-Bug loads CPM microcode into the first 512
  13  * bytes of the DP RAM and relocates the I2C parameter area to the
  14  * IDMA1 space.  The remaining DP RAM is available for buffer descriptors
  15  * or other use.
  16  */
  17 #ifndef __CPM_8XX__
  18 #define __CPM_8XX__
  19
  20 #include <linux/config.h>
  21 #include <asm/8xx_immap.h>
  22
  23 /* CPM Command register.
  24 */
  25 #define CPM_CR_RST      ((ushort)0x8000)
  26 #define CPM_CR_OPCODE   ((ushort)0x0f00)
  27 #define CPM_CR_CHAN     ((ushort)0x00f0)
  28 #define CPM_CR_FLG      ((ushort)0x0001)
  29
  30 /* Some commands (there are more...later)
  31 */
  32 #define CPM_CR_INIT_TRX         ((ushort)0x0000)
  33 #define CPM_CR_INIT_RX          ((ushort)0x0001)
  34 #define CPM_CR_INIT_TX          ((ushort)0x0002)
  35 #define CPM_CR_HUNT_MODE        ((ushort)0x0003)
  36 #define CPM_CR_STOP_TX          ((ushort)0x0004)
  37 #define CPM_CR_RESTART_TX       ((ushort)0x0006)
  38 #define CPM_CR_SET_GADDR        ((ushort)0x0008)
  39
  40 /* Channel numbers.
  41 */
  42 #define CPM_CR_CH_SCC1  ((ushort)0x0000)
  43 #define CPM_CR_CH_I2C   ((ushort)0x0001)        /* I2C and IDMA1 */
  44 #define CPM_CR_CH_SCC2  ((ushort)0x0004)
  45 #define CPM_CR_CH_SPI   ((ushort)0x0005)        /* SPI / IDMA2 / Timers */
  46 #define CPM_CR_CH_SCC3  ((ushort)0x0008)
  47 #define CPM_CR_CH_SMC1  ((ushort)0x0009)        /* SMC1 / DSP1 */
  48 #define CPM_CR_CH_SCC4  ((ushort)0x000c)
  49 #define CPM_CR_CH_SMC2  ((ushort)0x000d)        /* SMC2 / DSP2 */
  50
  51 #define mk_cr_cmd(CH, CMD)      ((CMD << 8) | (CH << 4))
  52
  53 /*
  54  * DPRAM defines and allocation functions
  55  */
  56
  57 /* The dual ported RAM is multi-functional.  Some areas can be (and are
  58  * being) used for microcode.  There is an area that can only be used
  59  * as data ram for buffer descriptors, which is all we use right now.
  60  * Currently the first 512 and last 256 bytes are used for microcode.
  61  */
  62 #ifdef  CFG_ALLOC_DPRAM
  63
  64 #define CPM_DATAONLY_BASE       ((uint)0x0800)
  65 #define CPM_DATAONLY_SIZE       ((uint)0x0700)
  66 #define CPM_DP_NOSPACE          ((uint)0x7fffffff)
  67
  68 #else
  69
  70 #define CPM_SERIAL_BASE         0x0800
  71 #define CPM_I2C_BASE            0x0820
  72 #define CPM_SPI_BASE            0x0840
  73 #define CPM_FEC_BASE            0x0860
  74 #define CPM_WLKBD_BASE          0x0880
  75 #define CPM_SCC_BASE            0x0900
  76 #define CPM_POST_BASE           0x0980
  77
  78 #endif
  79
  80 #define CPM_POST_WORD_ADDR      0x07FC
  81
  82 #define BD_IIC_START    ((uint) 0x0400) /* <- please use CPM_I2C_BASE !! */
  83
  84 /* Export the base address of the communication processor registers
  85  * and dual port ram.
  86  */
  87 extern  cpm8xx_t        *cpmp;          /* Pointer to comm processor */
  88
  89 /* Buffer descriptors used by many of the CPM protocols.
  90 */
  91 typedef struct cpm_buf_desc {
  92         ushort  cbd_sc;         /* Status and Control */
  93         ushort  cbd_datlen;     /* Data length in buffer */
  94         uint    cbd_bufaddr;    /* Buffer address in host memory */
  95 } cbd_t;
  96
  97 #define BD_SC_EMPTY     ((ushort)0x8000)        /* Recieve is empty */
  98 #define BD_SC_READY     ((ushort)0x8000)        /* Transmit is ready */
  99 #define BD_SC_WRAP      ((ushort)0x2000)        /* Last buffer descriptor */
 100 #define BD_SC_INTRPT    ((ushort)0x1000)        /* Interrupt on change */
 101 #define BD_SC_LAST      ((ushort)0x0800)        /* Last buffer in frame */
 102 #define BD_SC_TC        ((ushort)0x0400)        /* Transmit CRC */
 103 #define BD_SC_CM        ((ushort)0x0200)        /* Continous mode */
 104 #define BD_SC_ID        ((ushort)0x0100)        /* Rec'd too many idles */
 105 #define BD_SC_P         ((ushort)0x0100)        /* xmt preamble */
 106 #define BD_SC_BR        ((ushort)0x0020)        /* Break received */
 107 #define BD_SC_FR        ((ushort)0x0010)        /* Framing error */
 108 #define BD_SC_PR        ((ushort)0x0008)        /* Parity error */
 109 #define BD_SC_OV        ((ushort)0x0002)        /* Overrun */
 110 #define BD_SC_CD        ((ushort)0x0001)        /* Carrier Detect lost */
 111
 112 /* Parameter RAM offsets.
 113 */
 114 #define PROFF_SCC1      ((uint)0x0000)
 115 #define PROFF_IIC       ((uint)0x0080)
 116 #define PROFF_SCC2      ((uint)0x0100)
 117 #define PROFF_SPI       ((uint)0x0180)
 118 #define PROFF_SCC3      ((uint)0x0200)
 119 #define PROFF_SMC1      ((uint)0x0280)
 120 #define PROFF_SCC4      ((uint)0x0300)
 121 #define PROFF_SMC2      ((uint)0x0380)
 122
 123 /* Define enough so I can at least use the serial port as a UART.
 124  * The MBX uses SMC1 as the host serial port.
 125  */
 126 typedef struct smc_uart {
 127         ushort  smc_rbase;      /* Rx Buffer descriptor base address */
 128         ushort  smc_tbase;      /* Tx Buffer descriptor base address */
 129         u_char  smc_rfcr;       /* Rx function code */
 130         u_char  smc_tfcr;       /* Tx function code */
 131         ushort  smc_mrblr;      /* Max receive buffer length */
 132         uint    smc_rstate;     /* Internal */
 133         uint    smc_idp;        /* Internal */
 134         ushort  smc_rbptr;      /* Internal */
 135         ushort  smc_ibc;        /* Internal */
 136         uint    smc_rxtmp;      /* Internal */
 137         uint    smc_tstate;     /* Internal */
 138         uint    smc_tdp;        /* Internal */
 139         ushort  smc_tbptr;      /* Internal */
 140         ushort  smc_tbc;        /* Internal */
 141         uint    smc_txtmp;      /* Internal */
 142         ushort  smc_maxidl;     /* Maximum idle characters */
 143         ushort  smc_tmpidl;     /* Temporary idle counter */
 144         ushort  smc_brklen;     /* Last received break length */
 145         ushort  smc_brkec;      /* rcv'd break condition counter */
 146         ushort  smc_brkcr;      /* xmt break count register */
 147         ushort  smc_rmask;      /* Temporary bit mask */
 148 } smc_uart_t;
 149
 150 /* Function code bits.
 151 */
 152 #define SMC_EB  ((u_char)0x10)  /* Set big endian byte order */
 153
 154 /* SMC uart mode register.
 155 */
 156 #define SMCMR_REN       ((ushort)0x0001)
 157 #define SMCMR_TEN       ((ushort)0x0002)
 158 #define SMCMR_DM        ((ushort)0x000c)
 159 #define SMCMR_SM_GCI    ((ushort)0x0000)
 160 #define SMCMR_SM_UART   ((ushort)0x0020)
 161 #define SMCMR_SM_TRANS  ((ushort)0x0030)
 162 #define SMCMR_SM_MASK   ((ushort)0x0030)
 163 #define SMCMR_PM_EVEN   ((ushort)0x0100)        /* Even parity, else odd */
 164 #define SMCMR_REVD      SMCMR_PM_EVEN
 165 #define SMCMR_PEN       ((ushort)0x0200)        /* Parity enable */
 166 #define SMCMR_BS        SMCMR_PEN
 167 #define SMCMR_SL        ((ushort)0x0400)        /* Two stops, else one */
 168 #define SMCR_CLEN_MASK  ((ushort)0x7800)        /* Character length */
 169 #define smcr_mk_clen(C) (((C) << 11) & SMCR_CLEN_MASK)
 170
 171 /* SMC2 as Centronics parallel printer.  It is half duplex, in that
 172  * it can only receive or transmit.  The parameter ram values for
 173  * each direction are either unique or properly overlap, so we can
 174  * include them in one structure.
 175  */
 176 typedef struct smc_centronics {
 177         ushort  scent_rbase;
 178         ushort  scent_tbase;
 179         u_char  scent_cfcr;
 180         u_char  scent_smask;
 181         ushort  scent_mrblr;
 182         uint    scent_rstate;
 183         uint    scent_r_ptr;
 184         ushort  scent_rbptr;
 185         ushort  scent_r_cnt;
 186         uint    scent_rtemp;
 187         uint    scent_tstate;
 188         uint    scent_t_ptr;
 189         ushort  scent_tbptr;
 190         ushort  scent_t_cnt;
 191         uint    scent_ttemp;
 192         ushort  scent_max_sl;
 193         ushort  scent_sl_cnt;
 194         ushort  scent_character1;
 195         ushort  scent_character2;
 196         ushort  scent_character3;
 197         ushort  scent_character4;
 198         ushort  scent_character5;
 199         ushort  scent_character6;
 200         ushort  scent_character7;
 201         ushort  scent_character8;
 202         ushort  scent_rccm;
 203         ushort  scent_rccr;
 204 } smc_cent_t;
 205
 206 /* Centronics Status Mask Register.
 207 */
 208 #define SMC_CENT_F      ((u_char)0x08)
 209 #define SMC_CENT_PE     ((u_char)0x04)
 210 #define SMC_CENT_S      ((u_char)0x02)
 211
 212 /* SMC Event and Mask register.
 213 */
 214 #define SMCM_BRKE       ((unsigned char)0x40)   /* When in UART Mode */
 215 #define SMCM_BRK        ((unsigned char)0x10)   /* When in UART Mode */
 216 #define SMCM_TXE        ((unsigned char)0x10)   /* When in Transparent Mode */
 217 #define SMCM_BSY        ((unsigned char)0x04)
 218 #define SMCM_TX         ((unsigned char)0x02)
 219 #define SMCM_RX         ((unsigned char)0x01)
 220
 221 /* Baud rate generators.
 222 */
 223 #define CPM_BRG_RST             ((uint)0x00020000)
 224 #define CPM_BRG_EN              ((uint)0x00010000)
 225 #define CPM_BRG_EXTC_INT        ((uint)0x00000000)
 226 #define CPM_BRG_EXTC_CLK2       ((uint)0x00004000)
 227 #define CPM_BRG_EXTC_CLK6       ((uint)0x00008000)
 228 #define CPM_BRG_ATB             ((uint)0x00002000)
 229 #define CPM_BRG_CD_MASK         ((uint)0x00001ffe)
 230 #define CPM_BRG_DIV16           ((uint)0x00000001)
 231
 232 /* SI Clock Route Register
 233 */
 234 #define SICR_RCLK_SCC1_BRG1     ((uint)0x00000000)
 235 #define SICR_TCLK_SCC1_BRG1     ((uint)0x00000000)
 236 #define SICR_RCLK_SCC2_BRG2     ((uint)0x00000800)
 237 #define SICR_TCLK_SCC2_BRG2     ((uint)0x00000100)
 238 #define SICR_RCLK_SCC3_BRG3     ((uint)0x00100000)
 239 #define SICR_TCLK_SCC3_BRG3     ((uint)0x00020000)
 240 #define SICR_RCLK_SCC4_BRG4     ((uint)0x18000000)
 241 #define SICR_TCLK_SCC4_BRG4     ((uint)0x03000000)
 242
 243 /* SCCs.
 244 */
 245 #define SCC_GSMRH_IRP           ((uint)0x00040000)
 246 #define SCC_GSMRH_GDE           ((uint)0x00010000)
 247 #define SCC_GSMRH_TCRC_CCITT    ((uint)0x00008000)
 248 #define SCC_GSMRH_TCRC_BISYNC   ((uint)0x00004000)
 249 #define SCC_GSMRH_TCRC_HDLC     ((uint)0x00000000)
 250 #define SCC_GSMRH_REVD          ((uint)0x00002000)
 251 #define SCC_GSMRH_TRX           ((uint)0x00001000)
 252 #define SCC_GSMRH_TTX           ((uint)0x00000800)
 253 #define SCC_GSMRH_CDP           ((uint)0x00000400)
 254 #define SCC_GSMRH_CTSP          ((uint)0x00000200)
 255 #define SCC_GSMRH_CDS           ((uint)0x00000100)
 256 #define SCC_GSMRH_CTSS          ((uint)0x00000080)
 257 #define SCC_GSMRH_TFL           ((uint)0x00000040)
 258 #define SCC_GSMRH_RFW           ((uint)0x00000020)
 259 #define SCC_GSMRH_TXSY          ((uint)0x00000010)
 260 #define SCC_GSMRH_SYNL16        ((uint)0x0000000c)
 261 #define SCC_GSMRH_SYNL8         ((uint)0x00000008)
 262 #define SCC_GSMRH_SYNL4         ((uint)0x00000004)
 263 #define SCC_GSMRH_RTSM          ((uint)0x00000002)
 264 #define SCC_GSMRH_RSYN          ((uint)0x00000001)
 265
 266 #define SCC_GSMRL_SIR           ((uint)0x80000000)      /* SCC2 only */
 267 #define SCC_GSMRL_EDGE_NONE     ((uint)0x60000000)
 268 #define SCC_GSMRL_EDGE_NEG      ((uint)0x40000000)
 269 #define SCC_GSMRL_EDGE_POS      ((uint)0x20000000)
 270 #define SCC_GSMRL_EDGE_BOTH     ((uint)0x00000000)
 271 #define SCC_GSMRL_TCI           ((uint)0x10000000)
 272 #define SCC_GSMRL_TSNC_3        ((uint)0x0c000000)
 273 #define SCC_GSMRL_TSNC_4        ((uint)0x08000000)
 274 #define SCC_GSMRL_TSNC_14       ((uint)0x04000000)
 275 #define SCC_GSMRL_TSNC_INF      ((uint)0x00000000)
 276 #define SCC_GSMRL_RINV          ((uint)0x02000000)
 277 #define SCC_GSMRL_TINV          ((uint)0x01000000)
 278 #define SCC_GSMRL_TPL_128       ((uint)0x00c00000)
 279 #define SCC_GSMRL_TPL_64        ((uint)0x00a00000)
 280 #define SCC_GSMRL_TPL_48        ((uint)0x00800000)
 281 #define SCC_GSMRL_TPL_32        ((uint)0x00600000)
 282 #define SCC_GSMRL_TPL_16        ((uint)0x00400000)
 283 #define SCC_GSMRL_TPL_8         ((uint)0x00200000)
 284 #define SCC_GSMRL_TPL_NONE      ((uint)0x00000000)
 285 #define SCC_GSMRL_TPP_ALL1      ((uint)0x00180000)
 286 #define SCC_GSMRL_TPP_01        ((uint)0x00100000)
 287 #define SCC_GSMRL_TPP_10        ((uint)0x00080000)
 288 #define SCC_GSMRL_TPP_ZEROS     ((uint)0x00000000)
 289 #define SCC_GSMRL_TEND          ((uint)0x00040000)
 290 #define SCC_GSMRL_TDCR_32       ((uint)0x00030000)
 291 #define SCC_GSMRL_TDCR_16       ((uint)0x00020000)
 292 #define SCC_GSMRL_TDCR_8        ((uint)0x00010000)
 293 #define SCC_GSMRL_TDCR_1        ((uint)0x00000000)
 294 #define SCC_GSMRL_RDCR_32       ((uint)0x0000c000)
 295 #define SCC_GSMRL_RDCR_16       ((uint)0x00008000)
 296 #define SCC_GSMRL_RDCR_8        ((uint)0x00004000)
 297 #define SCC_GSMRL_RDCR_1        ((uint)0x00000000)
 298 #define SCC_GSMRL_RENC_DFMAN    ((uint)0x00003000)
 299 #define SCC_GSMRL_RENC_MANCH    ((uint)0x00002000)
 300 #define SCC_GSMRL_RENC_FM0      ((uint)0x00001000)
 301 #define SCC_GSMRL_RENC_NRZI     ((uint)0x00000800)
 302 #define SCC_GSMRL_RENC_NRZ      ((uint)0x00000000)
 303 #define SCC_GSMRL_TENC_DFMAN    ((uint)0x00000600)
 304 #define SCC_GSMRL_TENC_MANCH    ((uint)0x00000400)
 305 #define SCC_GSMRL_TENC_FM0      ((uint)0x00000200)
 306 #define SCC_GSMRL_TENC_NRZI     ((uint)0x00000100)
 307 #define SCC_GSMRL_TENC_NRZ      ((uint)0x00000000)
 308 #define SCC_GSMRL_DIAG_LE       ((uint)0x000000c0)      /* Loop and echo */
 309 #define SCC_GSMRL_DIAG_ECHO     ((uint)0x00000080)
 310 #define SCC_GSMRL_DIAG_LOOP     ((uint)0x00000040)
 311 #define SCC_GSMRL_DIAG_NORM     ((uint)0x00000000)
 312 #define SCC_GSMRL_ENR           ((uint)0x00000020)
 313 #define SCC_GSMRL_ENT           ((uint)0x00000010)
 314 #define SCC_GSMRL_MODE_ENET     ((uint)0x0000000c)
 315 #define SCC_GSMRL_MODE_DDCMP    ((uint)0x00000009)
 316 #define SCC_GSMRL_MODE_BISYNC   ((uint)0x00000008)
 317 #define SCC_GSMRL_MODE_V14      ((uint)0x00000007)
 318 #define SCC_GSMRL_MODE_AHDLC    ((uint)0x00000006)
 319 #define SCC_GSMRL_MODE_PROFIBUS ((uint)0x00000005)
 320 #define SCC_GSMRL_MODE_UART     ((uint)0x00000004)
 321 #define SCC_GSMRL_MODE_SS7      ((uint)0x00000003)
 322 #define SCC_GSMRL_MODE_ATALK    ((uint)0x00000002)
 323 #define SCC_GSMRL_MODE_HDLC     ((uint)0x00000000)
 324
 325 #define SCC_TODR_TOD            ((ushort)0x8000)
 326
 327 /* SCC Event and Mask register.
 328 */
 329 #define SCCM_TXE        ((unsigned char)0x10)
 330 #define SCCM_BSY        ((unsigned char)0x04)
 331 #define SCCM_TX         ((unsigned char)0x02)
 332 #define SCCM_RX         ((unsigned char)0x01)
 333
 334 typedef struct scc_param {
 335         ushort  scc_rbase;      /* Rx Buffer descriptor base address */
 336         ushort  scc_tbase;      /* Tx Buffer descriptor base address */
 337         u_char  scc_rfcr;       /* Rx function code */
 338         u_char  scc_tfcr;       /* Tx function code */
 339         ushort  scc_mrblr;      /* Max receive buffer length */
 340         uint    scc_rstate;     /* Internal */
 341         uint    scc_idp;        /* Internal */
 342         ushort  scc_rbptr;      /* Internal */
 343         ushort  scc_ibc;        /* Internal */
 344         uint    scc_rxtmp;      /* Internal */
 345         uint    scc_tstate;     /* Internal */
 346         uint    scc_tdp;        /* Internal */
 347         ushort  scc_tbptr;      /* Internal */
 348         ushort  scc_tbc;        /* Internal */
 349         uint    scc_txtmp;      /* Internal */
 350         uint    scc_rcrc;       /* Internal */
 351         uint    scc_tcrc;       /* Internal */
 352 } sccp_t;
 353
 354 /* Function code bits.
 355 */
 356 #define SCC_EB  ((u_char)0x10)  /* Set big endian byte order */
 357
 358 /* CPM Ethernet through SCCx.
 359  */
 360 typedef struct scc_enet {
 361         sccp_t  sen_genscc;
 362         uint    sen_cpres;      /* Preset CRC */
 363         uint    sen_cmask;      /* Constant mask for CRC */
 364         uint    sen_crcec;      /* CRC Error counter */
 365         uint    sen_alec;       /* alignment error counter */
 366         uint    sen_disfc;      /* discard frame counter */
 367         ushort  sen_pads;       /* Tx short frame pad character */
 368         ushort  sen_retlim;     /* Retry limit threshold */
 369         ushort  sen_retcnt;     /* Retry limit counter */
 370         ushort  sen_maxflr;     /* maximum frame length register */
 371         ushort  sen_minflr;     /* minimum frame length register */
 372         ushort  sen_maxd1;      /* maximum DMA1 length */
 373         ushort  sen_maxd2;      /* maximum DMA2 length */
 374         ushort  sen_maxd;       /* Rx max DMA */
 375         ushort  sen_dmacnt;     /* Rx DMA counter */
 376         ushort  sen_maxb;       /* Max BD byte count */
 377         ushort  sen_gaddr1;     /* Group address filter */
 378         ushort  sen_gaddr2;
 379         ushort  sen_gaddr3;
 380         ushort  sen_gaddr4;
 381         uint    sen_tbuf0data0; /* Save area 0 - current frame */
 382         uint    sen_tbuf0data1; /* Save area 1 - current frame */
 383         uint    sen_tbuf0rba;   /* Internal */
 384         uint    sen_tbuf0crc;   /* Internal */
 385         ushort  sen_tbuf0bcnt;  /* Internal */
 386         ushort  sen_paddrh;     /* physical address (MSB) */
 387         ushort  sen_paddrm;
 388         ushort  sen_paddrl;     /* physical address (LSB) */
 389         ushort  sen_pper;       /* persistence */
 390         ushort  sen_rfbdptr;    /* Rx first BD pointer */
 391         ushort  sen_tfbdptr;    /* Tx first BD pointer */
 392         ushort  sen_tlbdptr;    /* Tx last BD pointer */
 393         uint    sen_tbuf1data0; /* Save area 0 - current frame */
 394         uint    sen_tbuf1data1; /* Save area 1 - current frame */
 395         uint    sen_tbuf1rba;   /* Internal */
 396         uint    sen_tbuf1crc;   /* Internal */
 397         ushort  sen_tbuf1bcnt;  /* Internal */
 398         ushort  sen_txlen;      /* Tx Frame length counter */
 399         ushort  sen_iaddr1;     /* Individual address filter */
 400         ushort  sen_iaddr2;
 401         ushort  sen_iaddr3;
 402         ushort  sen_iaddr4;
 403         ushort  sen_boffcnt;    /* Backoff counter */
 404
 405         /* NOTE: Some versions of the manual have the following items
 406          * incorrectly documented.  Below is the proper order.
 407          */
 408         ushort  sen_taddrh;     /* temp address (MSB) */
 409         ushort  sen_taddrm;
 410         ushort  sen_taddrl;     /* temp address (LSB) */
 411 } scc_enet_t;
 412
 413 /**********************************************************************
 414  *
 415  * Board specific configuration settings.
 416  *
 417  * Please note that we use the presence of a #define SCC_ENET and/or
 418  * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers.
 419  **********************************************************************/
 420
 421
 422 /***  ADS  *************************************************************/
 423
 424 #if defined(CONFIG_MPC860) && defined(CONFIG_ADS)
 425 /* This ENET stuff is for the MPC860ADS with ethernet on SCC1.
 426  */
 427
 428 #define PROFF_ENET      PROFF_SCC1
 429 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 430 #define SCC_ENET        0
 431
 432 #define PA_ENET_RXD     ((ushort)0x0001)
 433 #define PA_ENET_TXD     ((ushort)0x0002)
 434 #define PA_ENET_TCLK    ((ushort)0x0100)
 435 #define PA_ENET_RCLK    ((ushort)0x0200)
 436
 437 #define PB_ENET_TENA    ((uint)0x00001000)
 438
 439 #define PC_ENET_CLSN    ((ushort)0x0010)
 440 #define PC_ENET_RENA    ((ushort)0x0020)
 441
 442 #define SICR_ENET_MASK  ((uint)0x000000ff)
 443 #define SICR_ENET_CLKRT ((uint)0x0000002c)
 444
 445 /* 68160 PHY control */
 446
 447 #define PC_ENET_ETHLOOP ((ushort)0x0800)
 448 #define PC_ENET_TPFLDL  ((ushort)0x0400)
 449 #define PC_ENET_TPSQEL  ((ushort)0x0200)
 450
 451 #endif  /* MPC860ADS */
 452
 453 /***  AMX860  **********************************************/
 454
 455 #if defined(CONFIG_AMX860)
 456
 457 /* This ENET stuff is for the AMX860 with ethernet on SCC1.
 458  */
 459
 460 #define PROFF_ENET      PROFF_SCC1
 461 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 462 #define SCC_ENET        0
 463
 464 #define PA_ENET_RXD     ((ushort)0x0001)
 465 #define PA_ENET_TXD     ((ushort)0x0002)
 466 #define PA_ENET_TCLK    ((ushort)0x0400)
 467 #define PA_ENET_RCLK    ((ushort)0x0800)
 468
 469 #define PB_ENET_TENA    ((uint)0x00001000)
 470
 471 #define PC_ENET_CLSN    ((ushort)0x0010)
 472 #define PC_ENET_RENA    ((ushort)0x0020)
 473
 474 #define SICR_ENET_MASK  ((uint)0x000000ff)
 475 #define SICR_ENET_CLKRT ((uint)0x0000003e)
 476
 477 /* 68160 PHY control */
 478
 479 #define PB_ENET_ETHLOOP ((uint)0x00020000)
 480 #define PB_ENET_TPFLDL  ((uint)0x00010000)
 481 #define PB_ENET_TPSQEL  ((uint)0x00008000)
 482 #define PD_ENET_ETH_EN  ((ushort)0x0004)
 483
 484 #endif  /* CONFIG_AMX860 */
 485
 486 /***  BSEIP  **********************************************************/
 487
 488 #ifdef CONFIG_BSEIP
 489 /* This ENET stuff is for the MPC823 with ethernet on SCC2.
 490  * This is unique to the BSE ip-Engine board.
 491  */
 492 #define PROFF_ENET      PROFF_SCC2
 493 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 494 #define SCC_ENET        1
 495 #define PA_ENET_RXD     ((ushort)0x0004)
 496 #define PA_ENET_TXD     ((ushort)0x0008)
 497 #define PA_ENET_TCLK    ((ushort)0x0100)
 498 #define PA_ENET_RCLK    ((ushort)0x0200)
 499 #define PB_ENET_TENA    ((uint)0x00002000)
 500 #define PC_ENET_CLSN    ((ushort)0x0040)
 501 #define PC_ENET_RENA    ((ushort)0x0080)
 502
 503 /* BSE uses port B and C bits for PHY control also.
 504 */
 505 #define PB_BSE_POWERUP  ((uint)0x00000004)
 506 #define PB_BSE_FDXDIS   ((uint)0x00008000)
 507 #define PC_BSE_LOOPBACK ((ushort)0x0800)
 508
 509 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 510 #define SICR_ENET_CLKRT ((uint)0x00002c00)
 511 #endif  /* CONFIG_BSEIP */
 512
 513 /***  BSEIP  **********************************************************/
 514
 515 #ifdef CONFIG_FLAGADM
 516 /* Enet configuration for the FLAGADM */
 517 /* Enet on SCC2 */
 518
 519 #define PROFF_ENET      PROFF_SCC2
 520 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 521 #define SCC_ENET        1
 522 #define PA_ENET_RXD             ((ushort)0x0004)
 523 #define PA_ENET_TXD             ((ushort)0x0008)
 524 #define PA_ENET_TCLK    ((ushort)0x0100)
 525 #define PA_ENET_RCLK    ((ushort)0x0400)
 526 #define PB_ENET_TENA    ((uint)0x00002000)
 527 #define PC_ENET_CLSN    ((ushort)0x0040)
 528 #define PC_ENET_RENA    ((ushort)0x0080)
 529
 530 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 531 #define SICR_ENET_CLKRT ((uint)0x00003400)
 532 #endif  /* CONFIG_FLAGADM */
 533
 534 /***  C2MON  **********************************************************/
 535
 536 #ifdef CONFIG_C2MON
 537
 538 # ifndef CONFIG_FEC_ENET        /* use SCC for 10Mbps Ethernet  */
 539 #  error "Ethernet on SCC not supported on C2MON Board!"
 540 # else                          /* Use FEC for Fast Ethernet */
 541
 542 #undef  SCC_ENET
 543 #define FEC_ENET
 544
 545 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
 546 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
 547 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
 548 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
 549 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
 550 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
 551 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
 552 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
 553 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
 554 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
 555 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
 556 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
 557 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
 558
 559 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
 560
 561 # endif /* CONFIG_FEC_ENET */
 562 #endif  /* CONFIG_C2MON */
 563
 564 /*********************************************************************/
 565
 566
 567 /***  CCM  and  PCU E  ***********************************************/
 568
 569 /* The PCU E  and  CCM  use the FEC on a MPC860T for Ethernet */
 570
 571 #if defined (CONFIG_PCU_E) || defined(CONFIG_CCM)
 572
 573 #define FEC_ENET        /* use FEC for EThernet */
 574 #undef  SCC_ENET
 575
 576 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
 577 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
 578 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
 579 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
 580 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
 581 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
 582 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
 583 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
 584 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
 585 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
 586 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
 587 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
 588 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
 589
 590 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
 591
 592 #endif  /* CONFIG_PCU_E, CONFIG_CCM */
 593
 594 /***  ESTEEM 192E  **************************************************/
 595 #ifdef CONFIG_ESTEEM192E
 596 /* ESTEEM192E
 597  * This ENET stuff is for the MPC850 with ethernet on SCC2. This
 598  * is very similar to the RPX-Lite configuration.
 599  * Note TENA , LOOPBACK , FDPLEX_DIS on Port B.
 600  */
 601
 602 #define PROFF_ENET      PROFF_SCC2
 603 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 604 #define SCC_ENET        1
 605
 606 #define PA_ENET_RXD     ((ushort)0x0004)
 607 #define PA_ENET_TXD     ((ushort)0x0008)
 608 #define PA_ENET_TCLK    ((ushort)0x0200)
 609 #define PA_ENET_RCLK    ((ushort)0x0800)
 610 #define PB_ENET_TENA    ((uint)0x00002000)
 611 #define PC_ENET_CLSN    ((ushort)0x0040)
 612 #define PC_ENET_RENA    ((ushort)0x0080)
 613
 614 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 615 #define SICR_ENET_CLKRT ((uint)0x00003d00)
 616
 617 #define PB_ENET_LOOPBACK ((uint)0x00004000)
 618 #define PB_ENET_FDPLEX_DIS ((uint)0x00008000)
 619
 620 #endif
 621
 622 /***  FADS823  ********************************************************/
 623
 624 #if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS)
 625 /* This ENET stuff is for the MPC823FADS with ethernet on SCC2.
 626  */
 627 #ifdef CONFIG_SCC2_ENET
 628 #define PROFF_ENET      PROFF_SCC2
 629 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 630 #define SCC_ENET        1
 631 #define CPMVEC_ENET     CPMVEC_SCC2
 632 #endif
 633
 634 #ifdef CONFIG_SCC1_ENET
 635 #define PROFF_ENET      PROFF_SCC1
 636 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 637 #define SCC_ENET        0
 638 #define CPMVEC_ENET     CPMVEC_SCC1
 639 #endif
 640
 641 #define PA_ENET_RXD     ((ushort)0x0004)
 642 #define PA_ENET_TXD     ((ushort)0x0008)
 643 #define PA_ENET_TCLK    ((ushort)0x0400)
 644 #define PA_ENET_RCLK    ((ushort)0x0200)
 645
 646 #define PB_ENET_TENA    ((uint)0x00002000)
 647
 648 #define PC_ENET_CLSN    ((ushort)0x0040)
 649 #define PC_ENET_RENA    ((ushort)0x0080)
 650
 651 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 652 #define SICR_ENET_CLKRT ((uint)0x00002e00)
 653
 654 #endif  /* CONFIG_FADS823FADS */
 655
 656 /***  FADS850SAR  ********************************************************/
 657
 658 #if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS)
 659 /* This ENET stuff is for the MPC850SAR with ethernet on SCC2.  Some of
 660  * this may be unique to the FADS850SAR configuration.
 661  * Note TENA is on Port B.
 662  */
 663 #define PROFF_ENET      PROFF_SCC2
 664 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 665 #define SCC_ENET        1
 666 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
 667 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
 668 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA 6 */
 669 #define PA_ENET_TCLK    ((ushort)0x0800)        /* PA 4 */
 670 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
 671 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC 9 */
 672 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC 8 */
 673
 674 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 675 #define SICR_ENET_CLKRT ((uint)0x00002f00)      /* RCLK-CLK2, TCLK-CLK4 */
 676 #endif  /* CONFIG_FADS850SAR */
 677
 678 /***  FADS860T********************************************************/
 679
 680 #if defined(CONFIG_MPC860T) && defined(CONFIG_FADS)
 681 /* This ENET stuff is for the MPC860TFADS with ethernet on SCC1.
 682  */
 683
 684 #ifdef CONFIG_SCC1_ENET
 685 #define SCC_ENET        0
 686 #endif  /* CONFIG_SCC1_ETHERNET */
 687 #define PROFF_ENET      PROFF_SCC1
 688 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 689
 690 #define PA_ENET_RXD     ((ushort)0x0001)
 691 #define PA_ENET_TXD     ((ushort)0x0002)
 692 #define PA_ENET_TCLK    ((ushort)0x0100)
 693 #define PA_ENET_RCLK    ((ushort)0x0200)
 694
 695 #define PB_ENET_TENA    ((uint)0x00001000)
 696
 697 #define PC_ENET_CLSN    ((ushort)0x0010)
 698 #define PC_ENET_RENA    ((ushort)0x0020)
 699
 700 #define SICR_ENET_MASK  ((uint)0x000000ff)
 701 #define SICR_ENET_CLKRT ((uint)0x0000002c)
 702
 703 /* This ENET stuff is for the MPC860TFADS with ethernet on FEC.
 704  */
 705
 706 #ifdef CONFIG_FEC_ENET
 707 #define FEC_ENET        /* use FEC for EThernet */
 708 #endif  /* CONFIG_FEC_ETHERNET */
 709
 710 #endif  /* CONFIG_FADS860T */
 711
 712 /***  FPS850L, FPS860L  ************************************************/
 713
 714 #if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L)
 715 /* Bits in parallel I/O port registers that have to be set/cleared
 716  * to configure the pins for SCC2 use.
 717  */
 718 #define PROFF_ENET      PROFF_SCC2
 719 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 720 #define SCC_ENET        1
 721 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
 722 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
 723 #define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
 724 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
 725
 726 #define PC_ENET_TENA    ((ushort)0x0002)        /* PC 14 */
 727 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
 728 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
 729
 730 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
 731  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 732  */
 733 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 734 #define SICR_ENET_CLKRT ((uint)0x00002600)
 735 #endif  /* CONFIG_FPS850L, CONFIG_FPS860L */
 736
 737 /*** GEN860T **********************************************************/
 738 #if defined(CONFIG_GEN860T)
 739 #undef  SCC_ENET
 740 #define FEC_ENET
 741
 742 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3        */
 743 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4        */
 744 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5        */
 745 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6        */
 746 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7        */
 747 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8        */
 748 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9        */
 749 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10        */
 750 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11        */
 751 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12        */
 752 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13        */
 753 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14        */
 754 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15        */
 755 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3-15      */
 756 #endif  /* CONFIG_GEN860T */
 757
 758 /***  GENIETV  ********************************************************/
 759
 760 #if defined(CONFIG_GENIETV)
 761 /* Ethernet is only on SCC2 */
 762
 763 #define CONFIG_SCC2_ENET
 764 #define PROFF_ENET      PROFF_SCC2
 765 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 766 #define SCC_ENET        1
 767 #define CPMVEC_ENET     CPMVEC_SCC2
 768
 769 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
 770 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
 771 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
 772 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA  6 */
 773
 774 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
 775
 776 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
 777 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
 778
 779 #define SICR_ENET_MASK  ((uint)0x0000ff00)
 780 #define SICR_ENET_CLKRT ((uint)0x00002e00)
 781
 782 #endif  /* CONFIG_GENIETV */
 783
 784 /*** GTH ******************************************************/
 785
 786 #ifdef CONFIG_GTH
 787 #ifdef CONFIG_FEC_ENET
 788 #define FEC_ENET        /* use FEC for EThernet */
 789 #endif  /* CONFIG_FEC_ETHERNET */
 790
 791 /* This ENET stuff is for GTH 10 Mbit ( SCC ) */
 792 #define PROFF_ENET      PROFF_SCC1
 793 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 794 #define SCC_ENET        0
 795
 796 #define PA_ENET_RXD     ((ushort)0x0001) /* PA15 */
 797 #define PA_ENET_TXD     ((ushort)0x0002) /* PA14 */
 798 #define PA_ENET_TCLK    ((ushort)0x0800) /* PA4 */
 799 #define PA_ENET_RCLK    ((ushort)0x0400) /* PA5 */
 800
 801 #define PB_ENET_TENA    ((uint)0x00001000) /* PB19 */
 802
 803 #define PC_ENET_CLSN    ((ushort)0x0010) /* PC11 */
 804 #define PC_ENET_RENA    ((ushort)0x0020) /* PC10 */
 805
 806 /* NOTE. This is reset for 10Mbit port only */
 807 #define PC_ENET_RESET   ((ushort)0x0100)        /* PC 7 */
 808
 809 #define SICR_ENET_MASK  ((uint)0x000000ff)
 810
 811 /* TCLK PA4 -->CLK4, RCLK PA5 -->CLK3 */
 812 #define SICR_ENET_CLKRT ((uint)0x00000037)
 813
 814 #endif  /* CONFIG_GTH */
 815
 816 /*** HERMES-PRO ******************************************************/
 817
 818 /* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */
 819
 820 #ifdef CONFIG_HERMES
 821
 822 #define FEC_ENET        /* use FEC for EThernet */
 823 #undef  SCC_ENET
 824
 825
 826 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
 827 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
 828 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
 829 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
 830 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
 831 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
 832 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
 833 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
 834 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
 835 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
 836 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
 837 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
 838 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
 839
 840 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
 841
 842 #endif  /* CONFIG_HERMES */
 843
 844 /***  IAD210  **********************************************************/
 845
 846 /* The IAD210 uses the FEC on a MPC860P for Ethernet */
 847
 848 #if defined(CONFIG_IAD210)
 849
 850 # define  FEC_ENET    /* use FEC for Ethernet */
 851 # undef   SCC_ENET
 852
 853 # define PD_MII_TXD1    ((ushort) 0x1000 )      /* PD  3 */
 854 # define PD_MII_TXD2    ((ushort) 0x0800 )      /* PD  4 */
 855 # define PD_MII_TXD3    ((ushort) 0x0400 )      /* PD  5 */
 856 # define PD_MII_RX_DV   ((ushort) 0x0200 )      /* PD  6 */
 857 # define PD_MII_RX_ERR  ((ushort) 0x0100 )      /* PD  7 */
 858 # define PD_MII_RX_CLK  ((ushort) 0x0080 )      /* PD  8 */
 859 # define PD_MII_TXD0    ((ushort) 0x0040 )      /* PD  9 */
 860 # define PD_MII_RXD0    ((ushort) 0x0020 )      /* PD 10 */
 861 # define PD_MII_TX_ERR  ((ushort) 0x0010 )      /* PD 11 */
 862 # define PD_MII_MDC     ((ushort) 0x0008 )      /* PD 12 */
 863 # define PD_MII_RXD1    ((ushort) 0x0004 )      /* PD 13 */
 864 # define PD_MII_RXD2    ((ushort) 0x0002 )      /* PD 14 */
 865 # define PD_MII_RXD3    ((ushort) 0x0001 )      /* PD 15 */
 866
 867 # define PD_MII_MASK    ((ushort) 0x1FFF )   /* PD 3...15 */
 868
 869 #endif  /* CONFIG_IAD210 */
 870
 871 /*** ICU862  **********************************************************/
 872
 873 #if defined(CONFIG_ICU862)
 874
 875 #ifdef CONFIG_FEC_ENET
 876 #define FEC_ENET        /* use FEC for EThernet */
 877 #endif  /* CONFIG_FEC_ETHERNET */
 878
 879 #endif /* CONFIG_ICU862 */
 880
 881 /***  IP860  **********************************************************/
 882
 883 #if defined(CONFIG_IP860)
 884 /* Bits in parallel I/O port registers that have to be set/cleared
 885  * to configure the pins for SCC1 use.
 886  */
 887 #define PROFF_ENET      PROFF_SCC1
 888 #define CPM_CR_ENET     CPM_CR_CH_SCC1
 889 #define SCC_ENET        0
 890 #define PA_ENET_RXD     ((ushort)0x0001)        /* PA 15 */
 891 #define PA_ENET_TXD     ((ushort)0x0002)        /* PA 14 */
 892 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA  6 */
 893 #define PA_ENET_TCLK    ((ushort)0x0100)        /* PA  7 */
 894
 895 #define PC_ENET_TENA    ((ushort)0x0001)        /* PC 15 */
 896 #define PC_ENET_CLSN    ((ushort)0x0010)        /* PC 11 */
 897 #define PC_ENET_RENA    ((ushort)0x0020)        /* PC 10 */
 898
 899 #define PB_ENET_RESET   (uint)0x00000008        /* PB 28 */
 900 #define PB_ENET_JABD    (uint)0x00000004        /* PB 29 */
 901
 902 /* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to
 903  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
 904  */
 905 #define SICR_ENET_MASK  ((uint)0x000000ff)
 906 #define SICR_ENET_CLKRT ((uint)0x0000002C)
 907 #endif  /* CONFIG_IP860 */
 908
 909 /*** IVMS8  **********************************************************/
 910
 911 /* The IVMS8 uses the FEC on a MPC860T for Ethernet */
 912
 913 #if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24)
 914
 915 #define FEC_ENET        /* use FEC for EThernet */
 916 #undef  SCC_ENET
 917
 918 #define PB_ENET_POWER   ((uint)0x00010000)      /* PB 15 */
 919
 920 #define PC_ENET_RESET   ((ushort)0x0010)        /* PC 11 */
 921
 922 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
 923 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
 924 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
 925 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
 926 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
 927 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
 928 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
 929 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
 930 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
 931 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
 932 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
 933 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
 934 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
 935
 936 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
 937
 938 #endif  /* CONFIG_IVMS8, CONFIG_IVML24 */
 939
 940 /***  KUP4K  *********************************************************/
 941 /* The KUP4K uses the FEC on a MPC855T for Ethernet */
 942
 943 #if defined(CONFIG_KUP4K)
 944
 945 #define FEC_ENET        /* use FEC for EThernet */
 946 #undef  SCC_ENET
 947
 948 #define PB_ENET_POWER   ((uint)0x00010000)      /* PB 15 */
 949
 950 #define PC_ENET_RESET   ((ushort)0x0010)        /* PC 11 */
 951
 952 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
 953 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
 954 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
 955 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
 956 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
 957 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
 958 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
 959 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
 960 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
 961 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
 962 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
 963 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
 964 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
 965
 966 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
 967
 968 #endif  /* CONFIG_KUP4K */
 969
 970
 971 /***  LANTEC  *********************************************************/
 972
 973 #if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2
 974 /* Bits in parallel I/O port registers that have to be set/cleared
 975  * to configure the pins for SCC2 use.
 976  */
 977 #define PROFF_ENET      PROFF_SCC2
 978 #define CPM_CR_ENET     CPM_CR_CH_SCC2
 979 #define SCC_ENET        1
 980 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
 981 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
 982 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA  6 */
 983 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
 984
 985 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
 986
 987 #define PC_ENET_LBK     ((ushort)0x0010)        /* PC 11 */
 988 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
 989 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
 990
 991 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
 992  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
 993  */
 994 #define SICR_ENET_MASK  ((uint)0x0000FF00)
 995 #define SICR_ENET_CLKRT ((uint)0x00002E00)
 996 #endif  /* CONFIG_LANTEC v2 */
 997
 998 /***  LWMON  **********************************************************/
 999
1000 #if defined(CONFIG_LWMON) && !defined(CONFIG_8xx_CONS_SCC2)
1001 /* Bits in parallel I/O port registers that have to be set/cleared
1002  * to configure the pins for SCC2 use.
1003  */
1004 #define PROFF_ENET      PROFF_SCC2
1005 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1006 #define SCC_ENET        1
1007 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
1008 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
1009 #define PA_ENET_RCLK    ((ushort)0x0800)        /* PA  4 */
1010 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
1011
1012 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
1013
1014 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
1015 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
1016
1017 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to
1018  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1019  */
1020 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1021 #define SICR_ENET_CLKRT ((uint)0x00003E00)
1022 #endif  /* CONFIG_LWMON */
1023
1024 /***  NX823  ***********************************************/
1025
1026 #if defined(CONFIG_NX823)
1027 /* Bits in parallel I/O port registers that have to be set/cleared
1028  * to configure the pins for SCC1 use.
1029  */
1030 #define PROFF_ENET      PROFF_SCC2
1031 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1032 #define SCC_ENET        1
1033 #define PA_ENET_RXD  ((ushort)0x0004)  /* PA 13 */
1034 #define PA_ENET_TXD  ((ushort)0x0008)  /* PA 12 */
1035 #define PA_ENET_RCLK ((ushort)0x0200)  /* PA  6 */
1036 #define PA_ENET_TCLK ((ushort)0x0800)  /* PA  4 */
1037
1038 #define PB_ENET_TENA ((uint)0x00002000)   /* PB 18 */
1039
1040 #define PC_ENET_CLSN ((ushort)0x0040)  /* PC  9 */
1041 #define PC_ENET_RENA ((ushort)0x0080)  /* PC  8 */
1042
1043 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1044  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1045  */
1046 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1047 #define SICR_ENET_CLKRT ((uint)0x00002f00)
1048
1049 #endif   /* CONFIG_NX823 */
1050
1051 /***  MBX  ************************************************************/
1052
1053 #ifdef CONFIG_MBX
1054 /* Bits in parallel I/O port registers that have to be set/cleared
1055  * to configure the pins for SCC1 use.  The TCLK and RCLK seem unique
1056  * to the MBX860 board.  Any two of the four available clocks could be
1057  * used, and the MPC860 cookbook manual has an example using different
1058  * clock pins.
1059  */
1060 #define PROFF_ENET      PROFF_SCC1
1061 #define CPM_CR_ENET     CPM_CR_CH_SCC1
1062 #define SCC_ENET        0
1063 #define PA_ENET_RXD     ((ushort)0x0001)
1064 #define PA_ENET_TXD     ((ushort)0x0002)
1065 #define PA_ENET_TCLK    ((ushort)0x0200)
1066 #define PA_ENET_RCLK    ((ushort)0x0800)
1067 #define PC_ENET_TENA    ((ushort)0x0001)
1068 #define PC_ENET_CLSN    ((ushort)0x0010)
1069 #define PC_ENET_RENA    ((ushort)0x0020)
1070
1071 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
1072  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1073  */
1074 #define SICR_ENET_MASK  ((uint)0x000000ff)
1075 #define SICR_ENET_CLKRT ((uint)0x0000003d)
1076 #endif  /* CONFIG_MBX */
1077
1078 /***  MHPC  ********************************************************/
1079
1080 #if defined(CONFIG_MHPC)
1081 /* This ENET stuff is for the MHPC with ethernet on SCC2.
1082  * Note TENA is on Port B.
1083  */
1084 #define PROFF_ENET      PROFF_SCC2
1085 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1086 #define SCC_ENET        1
1087 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
1088 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
1089 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA 6 */
1090 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA 5 */
1091 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
1092 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC 9 */
1093 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC 8 */
1094
1095 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1096 #define SICR_ENET_CLKRT ((uint)0x00002e00)      /* RCLK-CLK2, TCLK-CLK3 */
1097 #endif  /* CONFIG_MHPC */
1098
1099 /***  RPXCLASSIC  *****************************************************/
1100
1101 #ifdef CONFIG_RPXCLASSIC
1102
1103 #ifdef CONFIG_FEC_ENET
1104
1105 # define FEC_ENET                               /* use FEC for EThernet */
1106 # undef SCC_ENET
1107
1108 #else   /* ! CONFIG_FEC_ENET */
1109
1110 /* Bits in parallel I/O port registers that have to be set/cleared
1111  * to configure the pins for SCC1 use.
1112  */
1113 #define PROFF_ENET      PROFF_SCC1
1114 #define CPM_CR_ENET     CPM_CR_CH_SCC1
1115 #define SCC_ENET        0
1116 #define PA_ENET_RXD     ((ushort)0x0001)
1117 #define PA_ENET_TXD     ((ushort)0x0002)
1118 #define PA_ENET_TCLK    ((ushort)0x0200)
1119 #define PA_ENET_RCLK    ((ushort)0x0800)
1120 #define PB_ENET_TENA    ((uint)0x00001000)
1121 #define PC_ENET_CLSN    ((ushort)0x0010)
1122 #define PC_ENET_RENA    ((ushort)0x0020)
1123
1124 /* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to
1125  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1126  */
1127 #define SICR_ENET_MASK  ((uint)0x000000ff)
1128 #define SICR_ENET_CLKRT ((uint)0x0000003d)
1129
1130 #endif  /* CONFIG_FEC_ENET */
1131
1132 #endif  /* CONFIG_RPXCLASSIC */
1133
1134 /***  RPXLITE  ********************************************************/
1135
1136 #ifdef CONFIG_RPXLITE
1137 /* This ENET stuff is for the MPC850 with ethernet on SCC2.  Some of
1138  * this may be unique to the RPX-Lite configuration.
1139  * Note TENA is on Port B.
1140  */
1141 #define PROFF_ENET      PROFF_SCC2
1142 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1143 #define SCC_ENET        1
1144 #define PA_ENET_RXD     ((ushort)0x0004)
1145 #define PA_ENET_TXD     ((ushort)0x0008)
1146 #define PA_ENET_TCLK    ((ushort)0x0200)
1147 #define PA_ENET_RCLK    ((ushort)0x0800)
1148 #define PB_ENET_TENA    ((uint)0x00002000)
1149 #define PC_ENET_CLSN    ((ushort)0x0040)
1150 #define PC_ENET_RENA    ((ushort)0x0080)
1151
1152 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1153 #define SICR_ENET_CLKRT ((uint)0x00003d00)
1154 #endif  /* CONFIG_RPXLITE */
1155
1156 /***  SM850  *********************************************************/
1157
1158 /* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */
1159
1160 #ifdef CONFIG_SM850
1161 #define PROFF_ENET      PROFF_SCC3              /* Ethernet on SCC3 */
1162 #define CPM_CR_ENET     CPM_CR_CH_SCC3
1163 #define SCC_ENET        2
1164 #define PB_ENET_RXD     ((uint)0x00000004)      /* PB 29 */
1165 #define PB_ENET_TXD     ((uint)0x00000002)      /* PB 30 */
1166 #define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
1167 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
1168
1169 #define PC_ENET_LBK     ((ushort)0x0008)        /* PC 12 */
1170 #define PC_ENET_TENA    ((ushort)0x0004)        /* PC 13 */
1171
1172 #define PC_ENET_RENA    ((ushort)0x0800)        /* PC  4 */
1173 #define PC_ENET_CLSN    ((ushort)0x0400)        /* PC  5 */
1174
1175 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1176  * SCC3.  Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero.
1177  */
1178 #define SICR_ENET_MASK  ((uint)0x00FF0000)
1179 #define SICR_ENET_CLKRT ((uint)0x00260000)
1180 #endif  /* CONFIG_SM850 */
1181
1182 /***  SPD823TS  ******************************************************/
1183
1184 #ifdef CONFIG_SPD823TS
1185 /* Bits in parallel I/O port registers that have to be set/cleared
1186  * to configure the pins for SCC2 use.
1187  */
1188 #define PROFF_ENET      PROFF_SCC2              /* Ethernet on SCC2 */
1189 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1190 #define SCC_ENET        1
1191 #define PA_ENET_MDC     ((ushort)0x0001)        /* PA 15 !!! */
1192 #define PA_ENET_MDIO    ((ushort)0x0002)        /* PA 14 !!! */
1193 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
1194 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
1195 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA  6 */
1196 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
1197
1198 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
1199
1200 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
1201 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
1202 #define PC_ENET_RESET   ((ushort)0x0100)        /* PC  7 !!! */
1203
1204 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to
1205  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1206  */
1207 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1208 #define SICR_ENET_CLKRT ((uint)0x00002E00)
1209 #endif  /* CONFIG_SPD823TS */
1210
1211 /***  SXNI855T  ******************************************************/
1212
1213 #if defined(CONFIG_SXNI855T)
1214
1215 #ifdef CONFIG_FEC_ENET
1216 #define FEC_ENET        /* use FEC for Ethernet */
1217 #endif  /* CONFIG_FEC_ETHERNET */
1218
1219 #endif  /* CONFIG_SXNI855T */
1220
1221 /***  MVS1, TQM823L, TQM850L, ETX094, R360MPI  ***********************/
1222
1223 #if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \
1224     defined(CONFIG_R360MPI) || \
1225     defined(CONFIG_TQM823L) || \
1226     defined(CONFIG_TQM850L) || \
1227     defined(CONFIG_ETX094)  || \
1228     defined(CONFIG_RRVISION)|| \
1229    (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2)
1230 /* Bits in parallel I/O port registers that have to be set/cleared
1231  * to configure the pins for SCC2 use.
1232  */
1233 #define PROFF_ENET      PROFF_SCC2
1234 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1235 #define SCC_ENET        1
1236 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
1237 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
1238 #define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
1239 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
1240
1241 #define PB_ENET_TENA    ((uint)0x00002000)      /* PB 18 */
1242
1243 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
1244 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
1245 #if defined(CONFIG_R360MPI)
1246 #define PC_ENET_LBK     ((ushort)0x0008)        /* PC 12 */
1247 #endif   /* CONFIG_R360MPI */
1248
1249 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1250  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1251  */
1252 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1253 #define SICR_ENET_CLKRT ((uint)0x00002600)
1254 #endif  /* CONFIG_MVS v1, CONFIG_TQM823L, CONFIG_TQM850L, etc. */
1255
1256 /***  TQM860L, TQM855L ************************************************/
1257
1258 #if (defined(CONFIG_TQM860L) || defined(CONFIG_TQM855L))
1259
1260 # ifdef CONFIG_SCC1_ENET        /* use SCC for 10Mbps Ethernet  */
1261
1262 /* Bits in parallel I/O port registers that have to be set/cleared
1263  * to configure the pins for SCC1 use.
1264  */
1265 #define PROFF_ENET      PROFF_SCC1
1266 #define CPM_CR_ENET     CPM_CR_CH_SCC1
1267 #define SCC_ENET        0
1268 #define PA_ENET_RXD     ((ushort)0x0001)        /* PA 15 */
1269 #define PA_ENET_TXD     ((ushort)0x0002)        /* PA 14 */
1270 #define PA_ENET_RCLK    ((ushort)0x0100)        /* PA  7 */
1271 #define PA_ENET_TCLK    ((ushort)0x0400)        /* PA  5 */
1272
1273 #define PC_ENET_TENA    ((ushort)0x0001)        /* PC 15 */
1274 #define PC_ENET_CLSN    ((ushort)0x0010)        /* PC 11 */
1275 #define PC_ENET_RENA    ((ushort)0x0020)        /* PC 10 */
1276
1277 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1278  * SCC1.  Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero.
1279  */
1280 #define SICR_ENET_MASK  ((uint)0x000000ff)
1281 #define SICR_ENET_CLKRT ((uint)0x00000026)
1282
1283 # endif /* CONFIG_SCC1_ENET */
1284
1285 # ifdef CONFIG_FEC_ENET         /* Use FEC for Fast Ethernet */
1286
1287 #define FEC_ENET
1288
1289 #define PD_MII_TXD1     ((ushort)0x1000)        /* PD  3 */
1290 #define PD_MII_TXD2     ((ushort)0x0800)        /* PD  4 */
1291 #define PD_MII_TXD3     ((ushort)0x0400)        /* PD  5 */
1292 #define PD_MII_RX_DV    ((ushort)0x0200)        /* PD  6 */
1293 #define PD_MII_RX_ERR   ((ushort)0x0100)        /* PD  7 */
1294 #define PD_MII_RX_CLK   ((ushort)0x0080)        /* PD  8 */
1295 #define PD_MII_TXD0     ((ushort)0x0040)        /* PD  9 */
1296 #define PD_MII_RXD0     ((ushort)0x0020)        /* PD 10 */
1297 #define PD_MII_TX_ERR   ((ushort)0x0010)        /* PD 11 */
1298 #define PD_MII_MDC      ((ushort)0x0008)        /* PD 12 */
1299 #define PD_MII_RXD1     ((ushort)0x0004)        /* PD 13 */
1300 #define PD_MII_RXD2     ((ushort)0x0002)        /* PD 14 */
1301 #define PD_MII_RXD3     ((ushort)0x0001)        /* PD 15 */
1302
1303 #define PD_MII_MASK     ((ushort)0x1FFF)        /* PD 3...15 */
1304
1305 # endif /* CONFIG_FEC_ENET */
1306 #endif  /* CONFIG_TQM860L, CONFIG_TQM855L */
1307
1308 #if defined(CONFIG_NETVIA)
1309 /* Bits in parallel I/O port registers that have to be set/cleared
1310  * to configure the pins for SCC2 use.
1311  */
1312 #define PROFF_ENET      PROFF_SCC2
1313 #define CPM_CR_ENET     CPM_CR_CH_SCC2
1314 #define SCC_ENET        1
1315 #define PA_ENET_RXD     ((ushort)0x0004)        /* PA 13 */
1316 #define PA_ENET_TXD     ((ushort)0x0008)        /* PA 12 */
1317 #define PA_ENET_RCLK    ((ushort)0x0200)        /* PA  6 */
1318 #define PA_ENET_TCLK    ((ushort)0x0800)        /* PA  4 */
1319
1320 #define PB_ENET_PDN     ((ushort)0x4000)        /* PB 17 */
1321 #define PB_ENET_TENA    ((ushort)0x2000)        /* PB 18 */
1322
1323 #define PC_ENET_CLSN    ((ushort)0x0040)        /* PC  9 */
1324 #define PC_ENET_RENA    ((ushort)0x0080)        /* PC  8 */
1325
1326 /* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to
1327  * SCC2.  Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero.
1328  */
1329 #define SICR_ENET_MASK  ((uint)0x0000ff00)
1330 #define SICR_ENET_CLKRT ((uint)0x00002f00)
1331
1332 #endif  /* CONFIG_NETVIA */
1333
1334 /*********************************************************************/
1335
1336 /* SCC Event register as used by Ethernet.
1337 */
1338 #define SCCE_ENET_GRA   ((ushort)0x0080)        /* Graceful stop complete */
1339 #define SCCE_ENET_TXE   ((ushort)0x0010)        /* Transmit Error */
1340 #define SCCE_ENET_RXF   ((ushort)0x0008)        /* Full frame received */
1341 #define SCCE_ENET_BSY   ((ushort)0x0004)        /* All incoming buffers full */
1342 #define SCCE_ENET_TXB   ((ushort)0x0002)        /* A buffer was transmitted */
1343 #define SCCE_ENET_RXB   ((ushort)0x0001)        /* A buffer was received */
1344
1345 /* SCC Mode Register (PSMR) as used by Ethernet.
1346 */
1347 #define SCC_PSMR_HBC    ((ushort)0x8000)        /* Enable heartbeat */
1348 #define SCC_PSMR_FC     ((ushort)0x4000)        /* Force collision */
1349 #define SCC_PSMR_RSH    ((ushort)0x2000)        /* Receive short frames */
1350 #define SCC_PSMR_IAM    ((ushort)0x1000)        /* Check individual hash */
1351 #define SCC_PSMR_ENCRC  ((ushort)0x0800)        /* Ethernet CRC mode */
1352 #define SCC_PSMR_PRO    ((ushort)0x0200)        /* Promiscuous mode */
1353 #define SCC_PSMR_BRO    ((ushort)0x0100)        /* Catch broadcast pkts */
1354 #define SCC_PSMR_SBT    ((ushort)0x0080)        /* Special backoff timer */
1355 #define SCC_PSMR_LPB    ((ushort)0x0040)        /* Set Loopback mode */
1356 #define SCC_PSMR_SIP    ((ushort)0x0020)        /* Sample Input Pins */
1357 #define SCC_PSMR_LCW    ((ushort)0x0010)        /* Late collision window */
1358 #define SCC_PSMR_NIB22  ((ushort)0x000a)        /* Start frame search */
1359 #define SCC_PSMR_FDE    ((ushort)0x0001)        /* Full duplex enable */
1360
1361 /* Buffer descriptor control/status used by Ethernet receive.
1362 */
1363 #define BD_ENET_RX_EMPTY        ((ushort)0x8000)
1364 #define BD_ENET_RX_WRAP         ((ushort)0x2000)
1365 #define BD_ENET_RX_INTR         ((ushort)0x1000)
1366 #define BD_ENET_RX_LAST         ((ushort)0x0800)
1367 #define BD_ENET_RX_FIRST        ((ushort)0x0400)
1368 #define BD_ENET_RX_MISS         ((ushort)0x0100)
1369 #define BD_ENET_RX_LG           ((ushort)0x0020)
1370 #define BD_ENET_RX_NO           ((ushort)0x0010)
1371 #define BD_ENET_RX_SH           ((ushort)0x0008)
1372 #define BD_ENET_RX_CR           ((ushort)0x0004)
1373 #define BD_ENET_RX_OV           ((ushort)0x0002)
1374 #define BD_ENET_RX_CL           ((ushort)0x0001)
1375 #define BD_ENET_RX_STATS        ((ushort)0x013f)        /* All status bits */
1376
1377 /* Buffer descriptor control/status used by Ethernet transmit.
1378 */
1379 #define BD_ENET_TX_READY        ((ushort)0x8000)
1380 #define BD_ENET_TX_PAD          ((ushort)0x4000)
1381 #define BD_ENET_TX_WRAP         ((ushort)0x2000)
1382 #define BD_ENET_TX_INTR         ((ushort)0x1000)
1383 #define BD_ENET_TX_LAST         ((ushort)0x0800)
1384 #define BD_ENET_TX_TC           ((ushort)0x0400)
1385 #define BD_ENET_TX_DEF          ((ushort)0x0200)
1386 #define BD_ENET_TX_HB           ((ushort)0x0100)
1387 #define BD_ENET_TX_LC           ((ushort)0x0080)
1388 #define BD_ENET_TX_RL           ((ushort)0x0040)
1389 #define BD_ENET_TX_RCMASK       ((ushort)0x003c)
1390 #define BD_ENET_TX_UN           ((ushort)0x0002)
1391 #define BD_ENET_TX_CSL          ((ushort)0x0001)
1392 #define BD_ENET_TX_STATS        ((ushort)0x03ff)        /* All status bits */
1393
1394 /* SCC as UART
1395 */
1396 typedef struct scc_uart {
1397         sccp_t  scc_genscc;
1398         uint    scc_res1;       /* Reserved */
1399         uint    scc_res2;       /* Reserved */
1400         ushort  scc_maxidl;     /* Maximum idle chars */
1401         ushort  scc_idlc;       /* temp idle counter */
1402         ushort  scc_brkcr;      /* Break count register */
1403         ushort  scc_parec;      /* receive parity error counter */
1404         ushort  scc_frmec;      /* receive framing error counter */
1405         ushort  scc_nosec;      /* receive noise counter */
1406         ushort  scc_brkec;      /* receive break condition counter */
1407         ushort  scc_brkln;      /* last received break length */
1408         ushort  scc_uaddr1;     /* UART address character 1 */
1409         ushort  scc_uaddr2;     /* UART address character 2 */
1410         ushort  scc_rtemp;      /* Temp storage */
1411         ushort  scc_toseq;      /* Transmit out of sequence char */
1412         ushort  scc_char1;      /* control character 1 */
1413         ushort  scc_char2;      /* control character 2 */
1414         ushort  scc_char3;      /* control character 3 */
1415         ushort  scc_char4;      /* control character 4 */
1416         ushort  scc_char5;      /* control character 5 */
1417         ushort  scc_char6;      /* control character 6 */
1418         ushort  scc_char7;      /* control character 7 */
1419         ushort  scc_char8;      /* control character 8 */
1420         ushort  scc_rccm;       /* receive control character mask */
1421         ushort  scc_rccr;       /* receive control character register */
1422         ushort  scc_rlbc;       /* receive last break character */
1423 } scc_uart_t;
1424
1425 /* SCC Event and Mask registers when it is used as a UART.
1426 */
1427 #define UART_SCCM_GLR           ((ushort)0x1000)
1428 #define UART_SCCM_GLT           ((ushort)0x0800)
1429 #define UART_SCCM_AB            ((ushort)0x0200)
1430 #define UART_SCCM_IDL           ((ushort)0x0100)
1431 #define UART_SCCM_GRA           ((ushort)0x0080)
1432 #define UART_SCCM_BRKE          ((ushort)0x0040)
1433 #define UART_SCCM_BRKS          ((ushort)0x0020)
1434 #define UART_SCCM_CCR           ((ushort)0x0008)
1435 #define UART_SCCM_BSY           ((ushort)0x0004)
1436 #define UART_SCCM_TX            ((ushort)0x0002)
1437 #define UART_SCCM_RX            ((ushort)0x0001)
1438
1439 /* The SCC PSMR when used as a UART.
1440 */
1441 #define SCU_PSMR_FLC            ((ushort)0x8000)
1442 #define SCU_PSMR_SL             ((ushort)0x4000)
1443 #define SCU_PSMR_CL             ((ushort)0x3000)
1444 #define SCU_PSMR_UM             ((ushort)0x0c00)
1445 #define SCU_PSMR_FRZ            ((ushort)0x0200)
1446 #define SCU_PSMR_RZS            ((ushort)0x0100)
1447 #define SCU_PSMR_SYN            ((ushort)0x0080)
1448 #define SCU_PSMR_DRT            ((ushort)0x0040)
1449 #define SCU_PSMR_PEN            ((ushort)0x0010)
1450 #define SCU_PSMR_RPM            ((ushort)0x000c)
1451 #define SCU_PSMR_REVP           ((ushort)0x0008)
1452 #define SCU_PSMR_TPM            ((ushort)0x0003)
1453 #define SCU_PSMR_TEVP           ((ushort)0x0003)
1454
1455 /* CPM Transparent mode SCC.
1456  */
1457 typedef struct scc_trans {
1458         sccp_t  st_genscc;
1459         uint    st_cpres;       /* Preset CRC */
1460         uint    st_cmask;       /* Constant mask for CRC */
1461 } scc_trans_t;
1462
1463 #define BD_SCC_TX_LAST          ((ushort)0x0800)
1464
1465 /* IIC parameter RAM.
1466 */
1467 typedef struct iic {
1468         ushort  iic_rbase;      /* Rx Buffer descriptor base address */
1469         ushort  iic_tbase;      /* Tx Buffer descriptor base address */
1470         u_char  iic_rfcr;       /* Rx function code */
1471         u_char  iic_tfcr;       /* Tx function code */
1472         ushort  iic_mrblr;      /* Max receive buffer length */
1473         uint    iic_rstate;     /* Internal */
1474         uint    iic_rdp;        /* Internal */
1475         ushort  iic_rbptr;      /* Internal */
1476         ushort  iic_rbc;        /* Internal */
1477         uint    iic_rxtmp;      /* Internal */
1478         uint    iic_tstate;     /* Internal */
1479         uint    iic_tdp;        /* Internal */
1480         ushort  iic_tbptr;      /* Internal */
1481         ushort  iic_tbc;        /* Internal */
1482         uint    iic_txtmp;      /* Internal */
1483         uint    iic_res;        /* reserved */
1484         ushort  iic_rpbase;     /* Relocation pointer */
1485         ushort  iic_res2;       /* reserved */
1486 } iic_t;
1487
1488 /* SPI parameter RAM.
1489 */
1490 typedef struct spi {
1491         ushort  spi_rbase;      /* Rx Buffer descriptor base address */
1492         ushort  spi_tbase;      /* Tx Buffer descriptor base address */
1493         u_char  spi_rfcr;       /* Rx function code */
1494         u_char  spi_tfcr;       /* Tx function code */
1495         ushort  spi_mrblr;      /* Max receive buffer length */
1496         uint    spi_rstate;     /* Internal */
1497         uint    spi_rdp;        /* Internal */
1498         ushort  spi_rbptr;      /* Internal */
1499         ushort  spi_rbc;        /* Internal */
1500         uint    spi_rxtmp;      /* Internal */
1501         uint    spi_tstate;     /* Internal */
1502         uint    spi_tdp;        /* Internal */
1503         ushort  spi_tbptr;      /* Internal */
1504         ushort  spi_tbc;        /* Internal */
1505         uint    spi_txtmp;      /* Internal */
1506         uint    spi_res;
1507         ushort  spi_rpbase;     /* Relocation pointer */
1508         ushort  spi_res2;
1509 } spi_t;
1510
1511 /* SPI Mode register.
1512 */
1513 #define SPMODE_LOOP     ((ushort)0x4000)        /* Loopback */
1514 #define SPMODE_CI       ((ushort)0x2000)        /* Clock Invert */
1515 #define SPMODE_CP       ((ushort)0x1000)        /* Clock Phase */
1516 #define SPMODE_DIV16    ((ushort)0x0800)        /* BRG/16 mode */
1517 #define SPMODE_REV      ((ushort)0x0400)        /* Reversed Data */
1518 #define SPMODE_MSTR     ((ushort)0x0200)        /* SPI Master */
1519 #define SPMODE_EN       ((ushort)0x0100)        /* Enable */
1520 #define SPMODE_LENMSK   ((ushort)0x00f0)        /* character length */
1521 #define SPMODE_PMMSK    ((ushort)0x000f)        /* prescale modulus */
1522
1523 #define SPMODE_LEN(x)   ((((x)-1)&0xF)<<4)
1524 #define SPMODE_PM(x)    ((x) &0xF)
1525
1526 /* HDLC parameter RAM.
1527 */
1528
1529 typedef struct hdlc_pram_s {
1530         /*
1531          * SCC parameter RAM
1532          */
1533         ushort  rbase;          /* Rx Buffer descriptor base address */
1534         ushort  tbase;          /* Tx Buffer descriptor base address */
1535         uchar   rfcr;           /* Rx function code */
1536         uchar   tfcr;           /* Tx function code */
1537         ushort  mrblr;          /* Rx buffer length */
1538         ulong   rstate;         /* Rx internal state */
1539         ulong   rptr;           /* Rx internal data pointer */
1540         ushort  rbptr;          /* rb BD Pointer */
1541         ushort  rcount;         /* Rx internal byte count */
1542         ulong   rtemp;          /* Rx temp */
1543         ulong   tstate;         /* Tx internal state */
1544         ulong   tptr;           /* Tx internal data pointer */
1545         ushort  tbptr;          /* Tx BD pointer */
1546         ushort  tcount;         /* Tx byte count */
1547         ulong   ttemp;          /* Tx temp */
1548         ulong   rcrc;           /* temp receive CRC */
1549         ulong   tcrc;           /* temp transmit CRC */
1550         /*
1551          * HDLC specific parameter RAM
1552          */
1553         uchar   res[4];         /* reserved */
1554         ulong   c_mask;         /* CRC constant */
1555         ulong   c_pres;         /* CRC preset */
1556         ushort  disfc;          /* discarded frame counter */
1557         ushort  crcec;          /* CRC error counter */
1558         ushort  abtsc;          /* abort sequence counter */
1559         ushort  nmarc;          /* nonmatching address rx cnt */
1560         ushort  retrc;          /* frame retransmission cnt */
1561         ushort  mflr;           /* maximum frame length reg */
1562         ushort  max_cnt;        /* maximum length counter */
1563         ushort  rfthr;          /* received frames threshold */
1564         ushort  rfcnt;          /* received frames count */
1565         ushort  hmask;          /* user defined frm addr mask */
1566         ushort  haddr1;         /* user defined frm address 1 */
1567         ushort  haddr2;         /* user defined frm address 2 */
1568         ushort  haddr3;         /* user defined frm address 3 */
1569         ushort  haddr4;         /* user defined frm address 4 */
1570         ushort  tmp;            /* temp */
1571         ushort  tmp_mb;         /* temp */
1572 } hdlc_pram_t;
1573
1574 /* CPM interrupts.  There are nearly 32 interrupts generated by CPM
1575  * channels or devices.  All of these are presented to the PPC core
1576  * as a single interrupt.  The CPM interrupt handler dispatches its
1577  * own handlers, in a similar fashion to the PPC core handler.  We
1578  * use the table as defined in the manuals (i.e. no special high
1579  * priority and SCC1 == SCCa, etc...).
1580  */
1581 #define CPMVEC_NR               32
1582 #define CPMVEC_PIO_PC15         ((ushort)0x1f)
1583 #define CPMVEC_SCC1             ((ushort)0x1e)
1584 #define CPMVEC_SCC2             ((ushort)0x1d)
1585 #define CPMVEC_SCC3             ((ushort)0x1c)
1586 #define CPMVEC_SCC4             ((ushort)0x1b)
1587 #define CPMVEC_PIO_PC14         ((ushort)0x1a)
1588 #define CPMVEC_TIMER1           ((ushort)0x19)
1589 #define CPMVEC_PIO_PC13         ((ushort)0x18)
1590 #define CPMVEC_PIO_PC12         ((ushort)0x17)
1591 #define CPMVEC_SDMA_CB_ERR      ((ushort)0x16)
1592 #define CPMVEC_IDMA1            ((ushort)0x15)
1593 #define CPMVEC_IDMA2            ((ushort)0x14)
1594 #define CPMVEC_TIMER2           ((ushort)0x12)
1595 #define CPMVEC_RISCTIMER        ((ushort)0x11)
1596 #define CPMVEC_I2C              ((ushort)0x10)
1597 #define CPMVEC_PIO_PC11         ((ushort)0x0f)
1598 #define CPMVEC_PIO_PC10         ((ushort)0x0e)
1599 #define CPMVEC_TIMER3           ((ushort)0x0c)
1600 #define CPMVEC_PIO_PC9          ((ushort)0x0b)
1601 #define CPMVEC_PIO_PC8          ((ushort)0x0a)
1602 #define CPMVEC_PIO_PC7          ((ushort)0x09)
1603 #define CPMVEC_TIMER4           ((ushort)0x07)
1604 #define CPMVEC_PIO_PC6          ((ushort)0x06)
1605 #define CPMVEC_SPI              ((ushort)0x05)
1606 #define CPMVEC_SMC1             ((ushort)0x04)
1607 #define CPMVEC_SMC2             ((ushort)0x03)
1608 #define CPMVEC_PIO_PC5          ((ushort)0x02)
1609 #define CPMVEC_PIO_PC4          ((ushort)0x01)
1610 #define CPMVEC_ERROR            ((ushort)0x00)
1611
1612 extern void irq_install_handler(int vec, void (*handler)(void *), void *dev_id);
1613
1614 /* CPM interrupt configuration vector.
1615 */
1616 #define CICR_SCD_SCC4           ((uint)0x00c00000)      /* SCC4 @ SCCd */
1617 #define CICR_SCC_SCC3           ((uint)0x00200000)      /* SCC3 @ SCCc */
1618 #define CICR_SCB_SCC2           ((uint)0x00040000)      /* SCC2 @ SCCb */
1619 #define CICR_SCA_SCC1           ((uint)0x00000000)      /* SCC1 @ SCCa */
1620 #define CICR_IRL_MASK           ((uint)0x0000e000)      /* Core interrrupt */
1621 #define CICR_HP_MASK            ((uint)0x00001f00)      /* Hi-pri int. */
1622 #define CICR_IEN                ((uint)0x00000080)      /* Int. enable */
1623 #define CICR_SPS                ((uint)0x00000001)      /* SCC Spread */
1624 #endif /* __CPM_8XX__ */