include/configs/APC405.h

   1 /*
   2  * (C) Copyright 2005-2008
   3  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   4  *
   5  * (C) Copyright 2001-2004
   6  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /*
  28  * board/config.h - configuration options, board specific
  29  */
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  38 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  39 #define CONFIG_APCG405          1       /* ...on a APC405 board         */
  40
  41 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  42 #define CONFIG_BOARD_EARLY_INIT_R 1
  43 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  44
  45 #define CONFIG_SYS_CLK_FREQ     33333400 /* external frequency to pll   */
  46
  47 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  48
  49 #define CONFIG_BAUDRATE         115200
  50 #define CONFIG_BOOTDELAY        1       /* autoboot after 3 seconds     */
  51 #define CONFIG_BOOTCOUNT_LIMIT  1
  52
  53 #undef  CONFIG_BOOTARGS
  54
  55 #define CONFIG_SYS_USB_LOAD_COMMAND     "fatload usb 0 200000 pImage;"          \
  56                                 "fatload usb 0 300000 pImage.initrd"
  57 #define CONFIG_SYS_USB_SELF_COMMAND     "usb start;run usb_load;usb stop;"      \
  58                                 "run ramargs addip addcon usbargs;"     \
  59                                 "bootm 200000 300000"
  60 #define CONFIG_SYS_USB_ARGS             "setenv bootargs $(bootargs) usbboot=1"
  61 #define CONFIG_SYS_BOOTLIMIT            "3"
  62 #define CONFIG_SYS_ALT_BOOTCOMMAND      "run usb_self;reset"
  63
  64 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  65         "hostname=abg405\0"                                             \
  66         "bd_type=abg405\0"                                              \
  67         "serial#=AA0000\0"                                              \
  68         "kernel_addr=fe000000\0"                                        \
  69         "ramdisk_addr=fe100000\0"                                       \
  70         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  71         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  72         "nfsroot=$(serverip):$(rootpath)\0"                             \
  73         "addip=setenv bootargs $(bootargs) "                            \
  74                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
  75                 ":$(hostname)::off panic=1\0"                           \
  76         "addcon=setenv bootargs $(bootargs) console=ttyS0,$(baudrate)"  \
  77                 " $(optargs)\0"                                         \
  78         "flash_self=run ramargs addip addcon;"                          \
  79                 "bootm $(kernel_addr) $(ramdisk_addr)\0"                \
  80         "net_nfs=tftp 200000 $(img);run nfsargs addip addcon;"          \
  81                 "bootm\0"                                               \
  82         "rootpath=/tftpboot/abg405/target_root\0"                       \
  83         "img=/tftpboot/abg405/pImage\0"                                 \
  84         "load=tftp 100000 /tftpboot/abg405/u-boot.bin\0"                \
  85         "update=protect off fff80000 ffffffff;era fff80000 ffffffff;"   \
  86                 "cp.b 100000 fff80000 80000\0"                          \
  87         "ipaddr=10.0.111.111\0"                                         \
  88         "netmask=255.255.0.0\0"                                         \
  89         "serverip=10.0.0.190\0"                                         \
  90         "splashimage=ffe80000\0"                                        \
  91         "usb_load="CONFIG_SYS_USB_LOAD_COMMAND"\0"                              \
  92         "usb_self="CONFIG_SYS_USB_SELF_COMMAND"\0"                              \
  93         "usbargs="CONFIG_SYS_USB_ARGS"\0"                                       \
  94         "bootlimit="CONFIG_SYS_BOOTLIMIT"\0"                                    \
  95         "altbootcmd="CONFIG_SYS_ALT_BOOTCOMMAND"\0"                             \
  96         ""
  97 #define CONFIG_BOOTCOMMAND      "run flash_self;reset"
  98
  99 #define CONFIG_ETHADDR          00:02:27:8e:00:00
 100
 101 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 102 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 103
 104 #define CONFIG_NET_MULTI        1
 105 #undef  CONFIG_HAS_ETH1
 106
 107 #define CONFIG_MII              1       /* MII PHY management           */
 108 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
 109 #define CONFIG_LXT971_NO_SLEEP  1
 110 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() */
 111
 112 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
 113
 114 /*
 115  * BOOTP options
 116  */
 117 #define CONFIG_BOOTP_BOOTFILESIZE
 118 #define CONFIG_BOOTP_BOOTPATH
 119 #define CONFIG_BOOTP_GATEWAY
 120 #define CONFIG_BOOTP_HOSTNAME
 121
 122 /*
 123  * Command line configuration.
 124  */
 125 #include <config_cmd_default.h>
 126
 127 #define CONFIG_CMD_DHCP
 128 #define CONFIG_CMD_PCI
 129 #define CONFIG_CMD_IRQ
 130 #define CONFIG_CMD_IDE
 131 #define CONFIG_CMD_FAT
 132 #define CONFIG_CMD_ELF
 133 #define CONFIG_CMD_DATE
 134 #define CONFIG_CMD_I2C
 135 #define CONFIG_CMD_MII
 136 #define CONFIG_CMD_PING
 137 #define CONFIG_CMD_EEPROM
 138 #define CONFIG_CMD_USB
 139 #define CONFIG_CMD_AUTOSCRIPT
 140
 141 #define CONFIG_MAC_PARTITION
 142 #define CONFIG_DOS_PARTITION
 143
 144 #define CONFIG_SUPPORT_VFAT
 145
 146 #define CONFIG_AUTO_UPDATE      1       /* autoupdate via CF or USB */
 147
 148 #undef  CONFIG_WATCHDOG                 /* watchdog disabled */
 149
 150 #define CONFIG_RTC_MC146818             /* DS1685 is MC146818 compatible*/
 151 #define CONFIG_SYS_RTC_REG_BASE_ADDR 0xF0000500 /* RTC Base Address */
 152
 153 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
 154
 155 /*
 156  * Miscellaneous configurable options
 157  */
 158 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 159 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 160 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 161
 162 #if defined(CONFIG_CMD_KGDB)
 163 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 164 #else
 165 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 166 #endif
 167 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 168 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 169 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 170
 171 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device */
 172
 173 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 174
 175 #define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on */
 176 #define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM */
 177
 178 #define CONFIG_SYS_EXT_SERIAL_CLOCK    14745600 /* use external serial clock   */
 179
 180 /* The following table includes the supported baudrates */
 181 #define CONFIG_SYS_BAUDRATE_TABLE      \
 182         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
 183          57600, 115200, 230400, 460800, 921600 }
 184
 185 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 186 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 187
 188 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 189
 190 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 191
 192 /* Only interrupt boot if space is pressed */
 193 /* If a long serial cable is connected but */
 194 /* other end is dead, garbage will be read */
 195 #define CONFIG_AUTOBOOT_KEYED   1
 196 #define CONFIG_AUTOBOOT_PROMPT  \
 197         "Press SPACE to abort autoboot in %d seconds\n", bootdelay
 198 #undef CONFIG_AUTOBOOT_DELAY_STR
 199 #define CONFIG_AUTOBOOT_STOP_STR " "
 200
 201 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 202
 203 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 204
 205 /*
 206  * PCI stuff
 207  */
 208 #define PCI_HOST_ADAPTER        0       /* configure as pci adapter     */
 209 #define PCI_HOST_FORCE          1       /* configure as pci host        */
 210 #define PCI_HOST_AUTO           2       /* detected via arbiter enable  */
 211
 212 #define CONFIG_PCI                      /* include pci support          */
 213 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 214 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 215                                         /* resource configuration       */
 216
 217 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 218 #define CONFIG_PCI_SKIP_HOST_BRIDGE 1
 219 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 220 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 221 #define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 222 #define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
 223 #define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
 224 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 225 #define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
 226 #define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 227 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 228
 229 /*
 230  * IDE/ATA stuff
 231  */
 232 #undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
 233 #undef  CONFIG_IDE_LED                  /* no led for ide supported */
 234 #define CONFIG_IDE_RESET        1       /* reset for ide supported */
 235
 236 #define CONFIG_SYS_IDE_MAXBUS           1               /* max. 1 IDE busses */
 237 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS) /* max. 1 drives per IDE bus */
 238
 239 #define CONFIG_SYS_ATA_BASE_ADDR        0xF0100000
 240 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 241
 242 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* Offset for data I/O */
 243 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* Offset for normal register access */
 244 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0000  /* Offset for alternate registers */
 245
 246 /*
 247  * Start addresses for the final memory configuration
 248  * (Set up by the startup code)
 249  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 250  */
 251 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 252 #define CONFIG_SYS_MONITOR_BASE 0xFFF80000
 253 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)    /* Reserve 512 kB for Monitor */
 254 #define CONFIG_SYS_MALLOC_LEN           (2*1024*1024)   /* Reserve 2MB for malloc() */
 255
 256 /*
 257  * For booting Linux, the board info and command line data
 258  * have to be in the first 8 MB of memory, since this is
 259  * the maximum mapped by the Linux kernel during initialization.
 260  */
 261 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Init. Memory map for Linux */
 262
 263 /*
 264  * FLASH organization
 265  */
 266 #ifndef __ASSEMBLY__
 267 extern int flash_banks;
 268 #endif
 269
 270 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 271 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 272 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 273 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max num of sects on one chip */
 274 #define CONFIG_SYS_MAX_FLASH_BANKS      flash_banks /* max num of flash banks */
 275                                             /* updated in board_early_init_r */
 276 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
 277 #define CONFIG_SYS_FLASH_QUIET_TEST     1
 278 #define CONFIG_SYS_FLASH_INCREMENT      0x01000000
 279 #define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware protection */
 280 #define CONFIG_SYS_FLASH_AUTOPROTECT_LIST { \
 281                                 {0xfe000000, 0x500000}, \
 282                                 {0xffe80000, 0x180000} \
 283                                 }
 284 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster) */
 285 #define CONFIG_SYS_FLASH_BANKS_LIST     { \
 286                                 CONFIG_SYS_FLASH_BASE, \
 287                                 CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT \
 288                                 }
 289 #define CONFIG_SYS_FLASH_EMPTY_INFO     /* print 'E' for empty sector on flinfo */
 290
 291 /*
 292  * Environment Variable setup
 293  */
 294 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 295 #define CONFIG_ENV_OFFSET               0x000   /* environment starts at the */
 296                                         /* beginning of the EEPROM */
 297 #define CONFIG_ENV_SIZE         0x800   /* 2048 bytes may be used for env vars*/
 298 #define CONFIG_ENV_OVERWRITE    1       /* allow overwriting vendor vars */
 299
 300 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xF0000500      /* NVRAM base address */
 301 #define CONFIG_SYS_NVRAM_SIZE           242             /* NVRAM size */
 302
 303 /*
 304  * I2C EEPROM (CAT24WC16) for environment
 305  */
 306 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 307 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address */
 308 #define CONFIG_SYS_I2C_SLAVE            0x7F
 309
 310 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08 */
 311 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1       /* Bytes of address */
 312 /* mask of address bits that overflow into the "EEPROM chip address" */
 313 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 314 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has */
 315                                         /* 16 byte page write mode using*/
 316                                         /* last 4 bits of the address */
 317 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10 /* and takes up to 10 msec */
 318
 319 /*
 320  * External Bus Controller (EBC) Setup
 321  */
 322 #define FLASH0_BA       (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_INCREMENT) /* FLASH 0 BA */
 323 #define FLASH1_BA       CONFIG_SYS_FLASH_BASE      /* FLASH 1 Base Address          */
 324 #define CAN_BA          0xF0000000          /* CAN Base Address              */
 325 #define DUART0_BA       0xF0000400          /* DUART Base Address            */
 326 #define DUART1_BA       0xF0000408          /* DUART Base Address            */
 327 #define RTC_BA          0xF0000500          /* RTC Base Address              */
 328 #define PS2_BA          0xF0000600          /* PS/2 Base Address             */
 329 #define CF_BA           0xF0100000          /* CompactFlash Base Address     */
 330 #define FPGA_BA         0xF0100100          /* FPGA internal Base Address    */
 331 #define FUJI_BA         0xF0100200          /* Fuji internal Base Address    */
 332 #define PCMCIA1_BA      0x20000000          /* PCMCIA Slot 1 Base Address    */
 333 #define PCMCIA2_BA      0x28000000          /* PCMCIA Slot 2 Base Address    */
 334 #define VGA_BA          0xF1000000          /* Epson VGA Base Address        */
 335
 336 #define CONFIG_SYS_FPGA_BASE_ADDR      FPGA_BA     /* FPGA internal Base Address    */
 337
 338 /* Memory Bank 0 (Flash Bank 0) initialization                               */
 339 #define CONFIG_SYS_EBC_PB0AP   0x92015480
 340 #define CONFIG_SYS_EBC_PB0CR   FLASH0_BA | 0x9A000 /* BAS=0xFF0,BS=16MB,BU=R/W,BW=16bit*/
 341 #define CONFIG_SYS_EBC_PB0AP_HWREV8 CONFIG_SYS_EBC_PB0AP
 342 #define CONFIG_SYS_EBC_PB0CR_HWREV8 FLASH1_BA | 0xBA000 /* BS=32MB */
 343
 344 /* Memory Bank 1 (Flash Bank 1) initialization                               */
 345 #define CONFIG_SYS_EBC_PB1AP   0x92015480
 346 #define CONFIG_SYS_EBC_PB1CR   FLASH1_BA | 0x9A000 /* BAS=0xFE0,BS=16MB,BU=R/W,BW=16bit*/
 347
 348 /* Memory Bank 2 (CAN0, 1, RTC, Duart) initialization                           */
 349 #define CONFIG_SYS_EBC_PB2AP   0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 350 #define CONFIG_SYS_EBC_PB2CR   CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 351
 352 /* Memory Bank 3 (CompactFlash IDE, FPGA internal) initialization               */
 353 #define CONFIG_SYS_EBC_PB3AP   0x010059C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 354 #define CONFIG_SYS_EBC_PB3CR   CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 355
 356 /* Memory Bank 4 (PCMCIA Slot 1) initialization                                 */
 357 #define CONFIG_SYS_EBC_PB4AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 358 #define CONFIG_SYS_EBC_PB4CR   PCMCIA1_BA | 0xFA000 /*BAS=0x200,BS=128MB,BU=R/W,BW=16bit*/
 359
 360 /* Memory Bank 5 (Epson VGA) initialization                                     */
 361 #define CONFIG_SYS_EBC_PB5AP   0x03805380   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=0 */
 362 #define CONFIG_SYS_EBC_PB5CR   VGA_BA | 0x5A000    /* BAS=0xF10,BS=4MB,BU=R/W,BW=16bit */
 363
 364 /* Memory Bank 6 (PCMCIA Slot 2) initialization                                 */
 365 #define CONFIG_SYS_EBC_PB6AP   0x050007C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 366 #define CONFIG_SYS_EBC_PB6CR   PCMCIA2_BA | 0xFA000 /*BAS=0x280,BS=128MB,BU=R/W,BW=16bit*/
 367
 368 /*
 369  * FPGA stuff
 370  */
 371
 372 /* FPGA internal regs */
 373 #define CONFIG_SYS_FPGA_CTRL           0x008
 374 #define CONFIG_SYS_FPGA_CTRL2          0x00a
 375
 376 /* FPGA Control Reg */
 377 #define CONFIG_SYS_FPGA_CTRL_CF_RESET  0x0001
 378 #define CONFIG_SYS_FPGA_CTRL_WDI       0x0002
 379 #define CONFIG_SYS_FPGA_CTRL_PS2_RESET 0x0020
 380
 381 #define CONFIG_SYS_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
 382 #define CONFIG_SYS_FPGA_MAX_SIZE       80*1024     /* 80kByte is enough for XC2S50  */
 383
 384 /* FPGA program pin configuration */
 385 #define CONFIG_SYS_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
 386 #define CONFIG_SYS_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
 387 #define CONFIG_SYS_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
 388 #define CONFIG_SYS_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
 389 #define CONFIG_SYS_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
 390
 391 /*
 392  * LCD Setup
 393  */
 394 #define CONFIG_SYS_LCD_BIG_MEM          (VGA_BA + 0x200000) /* S1D13806 Mem Base */
 395 #define CONFIG_SYS_LCD_BIG_REG          VGA_BA /* S1D13806 Reg Base */
 396
 397 #define CONFIG_LCD_BIG          2 /* Epson S1D13806 used */
 398
 399 /* Image information... */
 400 #define CONFIG_LCD_USED         CONFIG_LCD_BIG
 401
 402 #define CONFIG_SYS_LCD_MEM              CONFIG_SYS_LCD_BIG_MEM
 403 #define CONFIG_SYS_LCD_REG              CONFIG_SYS_LCD_BIG_REG
 404
 405 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (1 << 20)
 406
 407 /*
 408  * Definitions for initial stack pointer and data area (in data cache)
 409  */
 410
 411 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 412 #define CONFIG_SYS_TEMP_STACK_OCM       1
 413
 414 /* On Chip Memory location */
 415 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 416 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 417
 418 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
 419 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
 420 #define CONFIG_SYS_GBL_DATA_SIZE        128 /* reserved bytes for initial data */
 421 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 422 /* reserve some memory for BOOT limit info */
 423 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 16)
 424
 425 #ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */
 426 #define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 8)
 427 #endif
 428
 429 /*
 430  * Internal Definitions
 431  *
 432  * Boot Flags
 433  */
 434 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 435 #define BOOTFLAG_WARM   0x02            /* Software reboot */
 436
 437 /*
 438  * PCI OHCI controller
 439  */
 440 #define CONFIG_USB_OHCI_NEW     1
 441 #define CONFIG_PCI_OHCI         1
 442 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1
 443 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
 444 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "ohci_pci"
 445 #define CONFIG_USB_STORAGE      1
 446 #define CONFIG_SYS_USB_OHCI_BOARD_INIT 1
 447
 448 #endif /* __CONFIG_H */