include/configs/B4860QDS.h

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_DISPLAY_BOARDINFO
  11
  12 /*
  13  * B4860 QDS board configuration file
  14  */
  15 #define CONFIG_B4860QDS
  16
  17 #ifdef CONFIG_RAMBOOT_PBL
  18 #define CONFIG_SYS_FSL_PBL_PBI  $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
  19 #define CONFIG_SYS_FSL_PBL_RCW  $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
  20 #ifndef CONFIG_NAND
  21 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  22 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  23 #else
  24 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  25 #define CONFIG_SPL_SERIAL_SUPPORT
  26 #define CONFIG_SPL_FLUSH_IMAGE
  27 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  28 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  29 #define CONFIG_FSL_LAW                 /* Use common FSL init code */
  30 #define CONFIG_SYS_TEXT_BASE            0x00201000
  31 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  32 #define CONFIG_SPL_PAD_TO               0x40000
  33 #define CONFIG_SPL_MAX_SIZE             0x28000
  34 #define RESET_VECTOR_OFFSET             0x27FFC
  35 #define BOOT_PAGE_OFFSET                0x27000
  36 #define CONFIG_SPL_NAND_SUPPORT
  37 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  38 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  39 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  40 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  41 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  42 #define CONFIG_SPL_NAND_BOOT
  43 #ifdef CONFIG_SPL_BUILD
  44 #define CONFIG_SPL_SKIP_RELOCATE
  45 #define CONFIG_SPL_COMMON_INIT_DDR
  46 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  47 #define CONFIG_SYS_NO_FLASH
  48 #endif
  49 #endif
  50 #endif
  51
  52 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  53 /* Set 1M boot space */
  54 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  55 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  56                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  57 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  58 #define CONFIG_SYS_NO_FLASH
  59 #endif
  60
  61 /* High Level Configuration Options */
  62 #define CONFIG_BOOKE
  63 #define CONFIG_E500                     /* BOOKE e500 family */
  64 #define CONFIG_E500MC                   /* BOOKE e500mc family */
  65 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  66 #define CONFIG_MP                       /* support multiple processors */
  67
  68 #ifndef CONFIG_SYS_TEXT_BASE
  69 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  70 #endif
  71
  72 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  73 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  74 #endif
  75
  76 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  77 #define CONFIG_SYS_NUM_CPC              CONFIG_NUM_DDR_CONTROLLERS
  78 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  79 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  80 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  81 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  82 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  83 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  84
  85 #ifndef CONFIG_PPC_B4420
  86 #define CONFIG_SYS_SRIO
  87 #define CONFIG_SRIO1                    /* SRIO port 1 */
  88 #define CONFIG_SRIO2                    /* SRIO port 2 */
  89 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  90 #endif
  91
  92 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  93
  94 /* I2C bus multiplexer */
  95 #define I2C_MUX_PCA_ADDR                0x77
  96
  97 /* VSC Crossbar switches */
  98 #define CONFIG_VSC_CROSSBAR
  99 #define I2C_CH_DEFAULT                  0x8
 100 #define I2C_CH_VSC3316                  0xc
 101 #define I2C_CH_VSC3308                  0xd
 102
 103 #define VSC3316_TX_ADDRESS              0x70
 104 #define VSC3316_RX_ADDRESS              0x71
 105 #define VSC3308_TX_ADDRESS              0x02
 106 #define VSC3308_RX_ADDRESS              0x03
 107
 108 /* IDT clock synthesizers */
 109 #define CONFIG_IDT8T49N222A
 110 #define I2C_CH_IDT                     0x9
 111
 112 #define IDT_SERDES1_ADDRESS            0x6E
 113 #define IDT_SERDES2_ADDRESS            0x6C
 114
 115 /* Voltage monitor on channel 2*/
 116 #define I2C_MUX_CH_VOL_MONITOR          0xa
 117 #define I2C_VOL_MONITOR_ADDR            0x40
 118 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 119 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 120 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 121
 122 #define CONFIG_ZM7300
 123 #define I2C_MUX_CH_DPM                  0xa
 124 #define I2C_DPM_ADDR                    0x28
 125
 126 #define CONFIG_ENV_OVERWRITE
 127
 128 #ifdef CONFIG_SYS_NO_FLASH
 129 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
 130 #define CONFIG_ENV_IS_NOWHERE
 131 #endif
 132 #else
 133 #define CONFIG_FLASH_CFI_DRIVER
 134 #define CONFIG_SYS_FLASH_CFI
 135 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 136 #endif
 137
 138 #if defined(CONFIG_SPIFLASH)
 139 #define CONFIG_SYS_EXTRA_ENV_RELOC
 140 #define CONFIG_ENV_IS_IN_SPI_FLASH
 141 #define CONFIG_ENV_SPI_BUS              0
 142 #define CONFIG_ENV_SPI_CS               0
 143 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 144 #define CONFIG_ENV_SPI_MODE             0
 145 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 146 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 147 #define CONFIG_ENV_SECT_SIZE            0x10000
 148 #elif defined(CONFIG_SDCARD)
 149 #define CONFIG_SYS_EXTRA_ENV_RELOC
 150 #define CONFIG_ENV_IS_IN_MMC
 151 #define CONFIG_SYS_MMC_ENV_DEV          0
 152 #define CONFIG_ENV_SIZE                 0x2000
 153 #define CONFIG_ENV_OFFSET               (512 * 1097)
 154 #elif defined(CONFIG_NAND)
 155 #define CONFIG_SYS_EXTRA_ENV_RELOC
 156 #define CONFIG_ENV_IS_IN_NAND
 157 #define CONFIG_ENV_SIZE                 0x2000
 158 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 159 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 160 #define CONFIG_ENV_IS_IN_REMOTE
 161 #define CONFIG_ENV_ADDR         0xffe20000
 162 #define CONFIG_ENV_SIZE         0x2000
 163 #elif defined(CONFIG_ENV_IS_NOWHERE)
 164 #define CONFIG_ENV_SIZE         0x2000
 165 #else
 166 #define CONFIG_ENV_IS_IN_FLASH
 167 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 168 #define CONFIG_ENV_SIZE         0x2000
 169 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 170 #endif
 171
 172 #ifndef __ASSEMBLY__
 173 unsigned long get_board_sys_clk(void);
 174 unsigned long get_board_ddr_clk(void);
 175 #endif
 176 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 177 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 178
 179 /*
 180  * These can be toggled for performance analysis, otherwise use default.
 181  */
 182 #define CONFIG_SYS_CACHE_STASHING
 183 #define CONFIG_BTB                      /* toggle branch predition */
 184 #define CONFIG_DDR_ECC
 185 #ifdef CONFIG_DDR_ECC
 186 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 187 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 188 #endif
 189
 190 #define CONFIG_ENABLE_36BIT_PHYS
 191
 192 #ifdef CONFIG_PHYS_64BIT
 193 #define CONFIG_ADDR_MAP
 194 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 195 #endif
 196
 197 #if 0
 198 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 199 #endif
 200 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 201 #define CONFIG_SYS_MEMTEST_END          0x00400000
 202 #define CONFIG_SYS_ALT_MEMTEST
 203 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 204
 205 /*
 206  *  Config the L3 Cache as L3 SRAM
 207  */
 208 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 209 #define CONFIG_SYS_L3_SIZE              256 << 10
 210 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 211 #ifdef CONFIG_NAND
 212 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 213 #endif
 214 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 215 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 216 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 217 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 218
 219 #ifdef CONFIG_PHYS_64BIT
 220 #define CONFIG_SYS_DCSRBAR              0xf0000000
 221 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 222 #endif
 223
 224 /* EEPROM */
 225 #define CONFIG_ID_EEPROM
 226 #define CONFIG_SYS_I2C_EEPROM_NXID
 227 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 228 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 229 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 230 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 231 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 232
 233 /*
 234  * DDR Setup
 235  */
 236 #define CONFIG_VERY_BIG_RAM
 237 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 238 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 239
 240 /* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
 241 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 242 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 243
 244 #define CONFIG_DDR_SPD
 245 #define CONFIG_SYS_DDR_RAW_TIMING
 246 #define CONFIG_SYS_FSL_DDR3
 247 #ifndef CONFIG_SPL_BUILD
 248 #define CONFIG_FSL_DDR_INTERACTIVE
 249 #endif
 250
 251 #define CONFIG_SYS_SPD_BUS_NUM  0
 252 #define SPD_EEPROM_ADDRESS1     0x51
 253 #define SPD_EEPROM_ADDRESS2     0x53
 254
 255 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 256 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 257
 258 /*
 259  * IFC Definitions
 260  */
 261 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 262 #ifdef CONFIG_PHYS_64BIT
 263 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 264 #else
 265 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 266 #endif
 267
 268 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 269 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 270                                 + 0x8000000) | \
 271                                 CSPR_PORT_SIZE_16 | \
 272                                 CSPR_MSEL_NOR | \
 273                                 CSPR_V)
 274 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 275 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 276                                 CSPR_PORT_SIZE_16 | \
 277                                 CSPR_MSEL_NOR | \
 278                                 CSPR_V)
 279 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128 * 1024 * 1024)
 280 /* NOR Flash Timing Params */
 281 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
 282 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) | \
 283                                 FTIM0_NOR_TEADC(0x04) | \
 284                                 FTIM0_NOR_TEAHC(0x20))
 285 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 286                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 287                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 288 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x01) | \
 289                                 FTIM2_NOR_TCH(0x0E) | \
 290                                 FTIM2_NOR_TWPH(0x0E) | \
 291                                 FTIM2_NOR_TWP(0x1c))
 292 #define CONFIG_SYS_NOR_FTIM3    0x0
 293
 294 #define CONFIG_SYS_FLASH_QUIET_TEST
 295 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 296
 297 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 298 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 299 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 300 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 301
 302 #define CONFIG_SYS_FLASH_EMPTY_INFO
 303 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 304                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 305
 306 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 307 #define CONFIG_FSL_QIXIS_V2
 308 #define QIXIS_BASE              0xffdf0000
 309 #ifdef CONFIG_PHYS_64BIT
 310 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 311 #else
 312 #define QIXIS_BASE_PHYS         QIXIS_BASE
 313 #endif
 314 #define QIXIS_LBMAP_SWITCH              0x01
 315 #define QIXIS_LBMAP_MASK                0x0f
 316 #define QIXIS_LBMAP_SHIFT               0
 317 #define QIXIS_LBMAP_DFLTBANK            0x00
 318 #define QIXIS_LBMAP_ALTBANK             0x02
 319 #define QIXIS_RST_CTL_RESET             0x31
 320 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 321 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 322 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 323
 324 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 325 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 326                                 | CSPR_PORT_SIZE_8 \
 327                                 | CSPR_MSEL_GPCM \
 328                                 | CSPR_V)
 329 #define CONFIG_SYS_AMASK3       IFC_AMASK(4 * 1024)
 330 #define CONFIG_SYS_CSOR3        0x0
 331 /* QIXIS Timing parameters for IFC CS3 */
 332 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 333                                         FTIM0_GPCM_TEADC(0x0e) | \
 334                                         FTIM0_GPCM_TEAHC(0x0e))
 335 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 336                                         FTIM1_GPCM_TRAD(0x1f))
 337 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 338                                         FTIM2_GPCM_TCH(0x8) | \
 339                                         FTIM2_GPCM_TWP(0x1f))
 340 #define CONFIG_SYS_CS3_FTIM3            0x0
 341
 342 /* NAND Flash on IFC */
 343 #define CONFIG_NAND_FSL_IFC
 344 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 345 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 346 #define CONFIG_SYS_NAND_BASE            0xff800000
 347 #ifdef CONFIG_PHYS_64BIT
 348 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 349 #else
 350 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 351 #endif
 352
 353 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 354 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 355                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 356                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 357                                 | CSPR_V)
 358 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 359
 360 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 361                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 362                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 363                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 364                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 365                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 366                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 367
 368 #define CONFIG_SYS_NAND_ONFI_DETECTION
 369
 370 /* ONFI NAND Flash mode0 Timing Params */
 371 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 372                                         FTIM0_NAND_TWP(0x18)   | \
 373                                         FTIM0_NAND_TWCHT(0x07) | \
 374                                         FTIM0_NAND_TWH(0x0a))
 375 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 376                                         FTIM1_NAND_TWBE(0x39)  | \
 377                                         FTIM1_NAND_TRR(0x0e)   | \
 378                                         FTIM1_NAND_TRP(0x18))
 379 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 380                                         FTIM2_NAND_TREH(0x0a) | \
 381                                         FTIM2_NAND_TWHRE(0x1e))
 382 #define CONFIG_SYS_NAND_FTIM3           0x0
 383
 384 #define CONFIG_SYS_NAND_DDR_LAW         11
 385
 386 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 387 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 388 #define CONFIG_CMD_NAND
 389
 390 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 391
 392 #if defined(CONFIG_NAND)
 393 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 394 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 395 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 396 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 397 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 398 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 399 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 400 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 401 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 402 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 403 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 404 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 405 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 406 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 407 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 408 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 409 #else
 410 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 411 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 412 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 413 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 414 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 415 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 416 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 417 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 418 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 419 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 420 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 421 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 422 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 423 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 424 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 425 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 426 #endif
 427 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 428 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 429 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 430 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 431 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 432 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 433 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 434 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 435
 436 #ifdef CONFIG_SPL_BUILD
 437 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 438 #else
 439 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 440 #endif
 441
 442 #if defined(CONFIG_RAMBOOT_PBL)
 443 #define CONFIG_SYS_RAMBOOT
 444 #endif
 445
 446 #define CONFIG_BOARD_EARLY_INIT_R
 447 #define CONFIG_MISC_INIT_R
 448
 449 #define CONFIG_HWCONFIG
 450
 451 /* define to use L1 as initial stack */
 452 #define CONFIG_L1_INIT_RAM
 453 #define CONFIG_SYS_INIT_RAM_LOCK
 454 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 455 #ifdef CONFIG_PHYS_64BIT
 456 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 457 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 458 /* The assembler doesn't like typecast */
 459 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 460         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 461           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 462 #else
 463 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 464 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 465 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 466 #endif
 467 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 468
 469 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 470                                         GENERATED_GBL_DATA_SIZE)
 471 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 472
 473 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 474 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 475
 476 /* Serial Port - controlled on board with jumper J8
 477  * open - index 2
 478  * shorted - index 1
 479  */
 480 #define CONFIG_CONS_INDEX       1
 481 #define CONFIG_SYS_NS16550_SERIAL
 482 #define CONFIG_SYS_NS16550_REG_SIZE     1
 483 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 484
 485 #define CONFIG_SYS_BAUDRATE_TABLE       \
 486         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 487
 488 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 489 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 490 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 491 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 492 #ifndef CONFIG_SPL_BUILD
 493 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 494 #endif
 495
 496 /* I2C */
 497 #define CONFIG_SYS_I2C
 498 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 499 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 500 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 501 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
 502 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 503 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 504 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
 505
 506 /*
 507  * RTC configuration
 508  */
 509 #define RTC
 510 #define CONFIG_RTC_DS3231               1
 511 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 512
 513 /*
 514  * RapidIO
 515  */
 516 #ifdef CONFIG_SYS_SRIO
 517 #ifdef CONFIG_SRIO1
 518 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 519 #ifdef CONFIG_PHYS_64BIT
 520 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 521 #else
 522 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 523 #endif
 524 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 525 #endif
 526
 527 #ifdef CONFIG_SRIO2
 528 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 529 #ifdef CONFIG_PHYS_64BIT
 530 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 531 #else
 532 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 533 #endif
 534 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 535 #endif
 536 #endif
 537
 538 /*
 539  * for slave u-boot IMAGE instored in master memory space,
 540  * PHYS must be aligned based on the SIZE
 541  */
 542 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 543 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 544 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 545 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 546 /*
 547  * for slave UCODE and ENV instored in master memory space,
 548  * PHYS must be aligned based on the SIZE
 549  */
 550 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 551 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 552 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 553
 554 /* slave core release by master*/
 555 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 556 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 557
 558 /*
 559  * SRIO_PCIE_BOOT - SLAVE
 560  */
 561 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 562 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 563 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 564                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 565 #endif
 566
 567 /*
 568  * eSPI - Enhanced SPI
 569  */
 570 #define CONFIG_SF_DEFAULT_SPEED         10000000
 571 #define CONFIG_SF_DEFAULT_MODE          0
 572
 573 /*
 574  * MAPLE
 575  */
 576 #ifdef CONFIG_PHYS_64BIT
 577 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
 578 #else
 579 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
 580 #endif
 581
 582 /*
 583  * General PCI
 584  * Memory space is mapped 1-1, but I/O space must start from 0.
 585  */
 586
 587 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 588 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 589 #ifdef CONFIG_PHYS_64BIT
 590 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 591 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 592 #else
 593 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 594 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 595 #endif
 596 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 597 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 598 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 599 #ifdef CONFIG_PHYS_64BIT
 600 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 601 #else
 602 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 603 #endif
 604 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 605
 606 /* Qman/Bman */
 607 #ifndef CONFIG_NOBQFMAN
 608 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 609 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
 610 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 611 #ifdef CONFIG_PHYS_64BIT
 612 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 613 #else
 614 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 615 #endif
 616 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 617 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 618 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 619 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 620 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 621 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 622                                         CONFIG_SYS_BMAN_CENA_SIZE)
 623 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 624 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 625 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
 626 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 627 #ifdef CONFIG_PHYS_64BIT
 628 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 629 #else
 630 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 631 #endif
 632 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 633 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 634 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 635 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 636 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 637 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 638                                         CONFIG_SYS_QMAN_CENA_SIZE)
 639 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 640 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 641
 642 #define CONFIG_SYS_DPAA_FMAN
 643
 644 #define CONFIG_SYS_DPAA_RMAN
 645
 646 /* Default address of microcode for the Linux Fman driver */
 647 #if defined(CONFIG_SPIFLASH)
 648 /*
 649  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 650  * env, so we got 0x110000.
 651  */
 652 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 653 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 654 #elif defined(CONFIG_SDCARD)
 655 /*
 656  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 657  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
 658  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
 659  */
 660 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 661 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
 662 #elif defined(CONFIG_NAND)
 663 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 664 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
 665 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 666 /*
 667  * Slave has no ucode locally, it can fetch this from remote. When implementing
 668  * in two corenet boards, slave's ucode could be stored in master's memory
 669  * space, the address can be mapped from slave TLB->slave LAW->
 670  * slave SRIO or PCIE outbound window->master inbound window->
 671  * master LAW->the ucode address in master's memory space.
 672  */
 673 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 674 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 675 #else
 676 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 677 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 678 #endif
 679 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 680 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 681 #endif /* CONFIG_NOBQFMAN */
 682
 683 #ifdef CONFIG_SYS_DPAA_FMAN
 684 #define CONFIG_FMAN_ENET
 685 #define CONFIG_PHYLIB_10G
 686 #define CONFIG_PHY_VITESSE
 687 #define CONFIG_PHY_TERANETICS
 688 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 689 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 690 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 691 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
 692 #endif
 693
 694 #ifdef CONFIG_PCI
 695 #define CONFIG_PCI_INDIRECT_BRIDGE
 696 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 697
 698 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 699 #define CONFIG_DOS_PARTITION
 700 #endif  /* CONFIG_PCI */
 701
 702 #ifdef CONFIG_FMAN_ENET
 703 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
 704 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
 705
 706 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
 707 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7       /*SLOT 1*/
 708 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6       /*SLOT 2*/
 709
 710 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 711 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 712 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 713 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 714
 715 #define CONFIG_MII              /* MII PHY management */
 716 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 717 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 718 #endif
 719
 720 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
 721
 722 /*
 723  * Environment
 724  */
 725 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 726 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 727
 728 /*
 729  * Command line configuration.
 730  */
 731 #define CONFIG_CMD_DATE
 732 #define CONFIG_CMD_EEPROM
 733 #define CONFIG_CMD_ERRATA
 734 #define CONFIG_CMD_IRQ
 735 #define CONFIG_CMD_REGINFO
 736
 737 #ifdef CONFIG_PCI
 738 #define CONFIG_CMD_PCI
 739 #endif
 740
 741 /* Hash command with SHA acceleration supported in hardware */
 742 #ifdef CONFIG_FSL_CAAM
 743 #define CONFIG_CMD_HASH
 744 #define CONFIG_SHA_HW_ACCEL
 745 #endif
 746
 747 /*
 748 * USB
 749 */
 750 #define CONFIG_HAS_FSL_DR_USB
 751
 752 #ifdef CONFIG_HAS_FSL_DR_USB
 753 #define CONFIG_USB_EHCI
 754
 755 #ifdef CONFIG_USB_EHCI
 756 #define CONFIG_USB_EHCI_FSL
 757 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 758 #endif
 759 #endif
 760
 761 /*
 762  * Miscellaneous configurable options
 763  */
 764 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 765 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 766 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 767 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 768 #ifdef CONFIG_CMD_KGDB
 769 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 770 #else
 771 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 772 #endif
 773 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 774 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 775 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 776
 777 /*
 778  * For booting Linux, the board info and command line data
 779  * have to be in the first 64 MB of memory, since this is
 780  * the maximum mapped by the Linux kernel during initialization.
 781  */
 782 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 783 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 784
 785 #ifdef CONFIG_CMD_KGDB
 786 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 787 #endif
 788
 789 /*
 790  * Environment Configuration
 791  */
 792 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 793 #define CONFIG_BOOTFILE         "uImage"
 794 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 795
 796 /* default location for tftp and bootm */
 797 #define CONFIG_LOADADDR         1000000
 798
 799
 800 #define CONFIG_BAUDRATE 115200
 801
 802 #define __USB_PHY_TYPE  ulpi
 803
 804 #ifdef CONFIG_PPC_B4860
 805 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,"     \
 806                         "bank_intlv=cs0_cs1;"   \
 807                         "en_cpc:cpc2;"
 808 #else
 809 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
 810 #endif
 811
 812 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 813         HWCONFIG                                                \
 814         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 815         "netdev=eth0\0"                                         \
 816         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 817         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
 818         "tftpflash=tftpboot $loadaddr $uboot && "               \
 819         "protect off $ubootaddr +$filesize && "                 \
 820         "erase $ubootaddr +$filesize && "                       \
 821         "cp.b $loadaddr $ubootaddr $filesize && "               \
 822         "protect on $ubootaddr +$filesize && "                  \
 823         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 824         "consoledev=ttyS0\0"                                    \
 825         "ramdiskaddr=2000000\0"                                 \
 826         "ramdiskfile=b4860qds/ramdisk.uboot\0"                  \
 827         "fdtaddr=1e00000\0"                                     \
 828         "fdtfile=b4860qds/b4860qds.dtb\0"                               \
 829         "bdev=sda3\0"
 830
 831 /* For emulation this causes u-boot to jump to the start of the proof point
 832    app code automatically */
 833 #define CONFIG_PROOF_POINTS                     \
 834  "setenv bootargs root=/dev/$bdev rw "          \
 835  "console=$consoledev,$baudrate $othbootargs;"  \
 836  "cpu 1 release 0x29000000 - - -;"              \
 837  "cpu 2 release 0x29000000 - - -;"              \
 838  "cpu 3 release 0x29000000 - - -;"              \
 839  "cpu 4 release 0x29000000 - - -;"              \
 840  "cpu 5 release 0x29000000 - - -;"              \
 841  "cpu 6 release 0x29000000 - - -;"              \
 842  "cpu 7 release 0x29000000 - - -;"              \
 843  "go 0x29000000"
 844
 845 #define CONFIG_HVBOOT   \
 846  "setenv bootargs config-addr=0x60000000; "     \
 847  "bootm 0x01000000 - 0x00f00000"
 848
 849 #define CONFIG_ALU                              \
 850  "setenv bootargs root=/dev/$bdev rw "          \
 851  "console=$consoledev,$baudrate $othbootargs;"  \
 852  "cpu 1 release 0x01000000 - - -;"              \
 853  "cpu 2 release 0x01000000 - - -;"              \
 854  "cpu 3 release 0x01000000 - - -;"              \
 855  "cpu 4 release 0x01000000 - - -;"              \
 856  "cpu 5 release 0x01000000 - - -;"              \
 857  "cpu 6 release 0x01000000 - - -;"              \
 858  "cpu 7 release 0x01000000 - - -;"              \
 859  "go 0x01000000"
 860
 861 #define CONFIG_LINUX                            \
 862  "setenv bootargs root=/dev/ram rw "            \
 863  "console=$consoledev,$baudrate $othbootargs;"  \
 864  "setenv ramdiskaddr 0x02000000;"               \
 865  "setenv fdtaddr 0x01e00000;"                   \
 866  "setenv loadaddr 0x1000000;"                   \
 867  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 868
 869 #define CONFIG_HDBOOT                                   \
 870         "setenv bootargs root=/dev/$bdev rw "           \
 871         "console=$consoledev,$baudrate $othbootargs;"   \
 872         "tftp $loadaddr $bootfile;"                     \
 873         "tftp $fdtaddr $fdtfile;"                       \
 874         "bootm $loadaddr - $fdtaddr"
 875
 876 #define CONFIG_NFSBOOTCOMMAND                   \
 877         "setenv bootargs root=/dev/nfs rw "     \
 878         "nfsroot=$serverip:$rootpath "          \
 879         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 880         "console=$consoledev,$baudrate $othbootargs;"   \
 881         "tftp $loadaddr $bootfile;"             \
 882         "tftp $fdtaddr $fdtfile;"               \
 883         "bootm $loadaddr - $fdtaddr"
 884
 885 #define CONFIG_RAMBOOTCOMMAND                           \
 886         "setenv bootargs root=/dev/ram rw "             \
 887         "console=$consoledev,$baudrate $othbootargs;"   \
 888         "tftp $ramdiskaddr $ramdiskfile;"               \
 889         "tftp $loadaddr $bootfile;"                     \
 890         "tftp $fdtaddr $fdtfile;"                       \
 891         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 892
 893 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 894
 895 #include <asm/fsl_secure_boot.h>
 896
 897 #endif  /* __CONFIG_H */