include/configs/B4860QDS.h

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 /*
  11  * B4860 QDS board configuration file
  12  */
  13 #ifdef CONFIG_RAMBOOT_PBL
  14 #define CONFIG_SYS_FSL_PBL_PBI  $(SRCTREE)/board/freescale/b4860qds/b4_pbi.cfg
  15 #define CONFIG_SYS_FSL_PBL_RCW  $(SRCTREE)/board/freescale/b4860qds/b4_rcw.cfg
  16 #ifndef CONFIG_NAND
  17 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  18 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  19 #else
  20 #define CONFIG_SPL_FLUSH_IMAGE
  21 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  22 #define CONFIG_SYS_TEXT_BASE            0x00201000
  23 #define CONFIG_SPL_TEXT_BASE            0xFFFD8000
  24 #define CONFIG_SPL_PAD_TO               0x40000
  25 #define CONFIG_SPL_MAX_SIZE             0x28000
  26 #define RESET_VECTOR_OFFSET             0x27FFC
  27 #define BOOT_PAGE_OFFSET                0x27000
  28 #define CONFIG_SYS_NAND_U_BOOT_SIZE     (768 << 10)
  29 #define CONFIG_SYS_NAND_U_BOOT_DST      0x00200000
  30 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  31 #define CONFIG_SYS_NAND_U_BOOT_OFFS     (256 << 10)
  32 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  33 #define CONFIG_SPL_NAND_BOOT
  34 #ifdef CONFIG_SPL_BUILD
  35 #define CONFIG_SPL_SKIP_RELOCATE
  36 #define CONFIG_SPL_COMMON_INIT_DDR
  37 #define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
  38 #define CONFIG_SYS_NO_FLASH
  39 #endif
  40 #endif
  41 #endif
  42
  43 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
  44 /* Set 1M boot space */
  45 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000)
  46 #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \
  47                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR)
  48 #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
  49 #define CONFIG_SYS_NO_FLASH
  50 #endif
  51
  52 /* High Level Configuration Options */
  53 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  54 #define CONFIG_MP                       /* support multiple processors */
  55
  56 #ifndef CONFIG_SYS_TEXT_BASE
  57 #define CONFIG_SYS_TEXT_BASE    0xeff40000
  58 #endif
  59
  60 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  61 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  62 #endif
  63
  64 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  65 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  66 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  67 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  68 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  69 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  70 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  71
  72 #ifndef CONFIG_ARCH_B4420
  73 #define CONFIG_SYS_SRIO
  74 #define CONFIG_SRIO1                    /* SRIO port 1 */
  75 #define CONFIG_SRIO2                    /* SRIO port 2 */
  76 #define CONFIG_SRIO_PCIE_BOOT_MASTER
  77 #endif
  78
  79 /* I2C bus multiplexer */
  80 #define I2C_MUX_PCA_ADDR                0x77
  81
  82 /* VSC Crossbar switches */
  83 #define CONFIG_VSC_CROSSBAR
  84 #define I2C_CH_DEFAULT                  0x8
  85 #define I2C_CH_VSC3316                  0xc
  86 #define I2C_CH_VSC3308                  0xd
  87
  88 #define VSC3316_TX_ADDRESS              0x70
  89 #define VSC3316_RX_ADDRESS              0x71
  90 #define VSC3308_TX_ADDRESS              0x02
  91 #define VSC3308_RX_ADDRESS              0x03
  92
  93 /* IDT clock synthesizers */
  94 #define CONFIG_IDT8T49N222A
  95 #define I2C_CH_IDT                     0x9
  96
  97 #define IDT_SERDES1_ADDRESS            0x6E
  98 #define IDT_SERDES2_ADDRESS            0x6C
  99
 100 /* Voltage monitor on channel 2*/
 101 #define I2C_MUX_CH_VOL_MONITOR          0xa
 102 #define I2C_VOL_MONITOR_ADDR            0x40
 103 #define I2C_VOL_MONITOR_BUS_V_OFFSET    0x2
 104 #define I2C_VOL_MONITOR_BUS_V_OVF       0x1
 105 #define I2C_VOL_MONITOR_BUS_V_SHIFT     3
 106
 107 #define CONFIG_ZM7300
 108 #define I2C_MUX_CH_DPM                  0xa
 109 #define I2C_DPM_ADDR                    0x28
 110
 111 #define CONFIG_ENV_OVERWRITE
 112
 113 #ifdef CONFIG_SYS_NO_FLASH
 114 #if !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) && !defined(CONFIG_RAMBOOT_PBL)
 115 #define CONFIG_ENV_IS_NOWHERE
 116 #endif
 117 #else
 118 #define CONFIG_FLASH_CFI_DRIVER
 119 #define CONFIG_SYS_FLASH_CFI
 120 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 121 #endif
 122
 123 #if defined(CONFIG_SPIFLASH)
 124 #define CONFIG_SYS_EXTRA_ENV_RELOC
 125 #define CONFIG_ENV_IS_IN_SPI_FLASH
 126 #define CONFIG_ENV_SPI_BUS              0
 127 #define CONFIG_ENV_SPI_CS               0
 128 #define CONFIG_ENV_SPI_MAX_HZ           10000000
 129 #define CONFIG_ENV_SPI_MODE             0
 130 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
 131 #define CONFIG_ENV_OFFSET               0x100000        /* 1MB */
 132 #define CONFIG_ENV_SECT_SIZE            0x10000
 133 #elif defined(CONFIG_SDCARD)
 134 #define CONFIG_SYS_EXTRA_ENV_RELOC
 135 #define CONFIG_ENV_IS_IN_MMC
 136 #define CONFIG_SYS_MMC_ENV_DEV          0
 137 #define CONFIG_ENV_SIZE                 0x2000
 138 #define CONFIG_ENV_OFFSET               (512 * 1097)
 139 #elif defined(CONFIG_NAND)
 140 #define CONFIG_SYS_EXTRA_ENV_RELOC
 141 #define CONFIG_ENV_IS_IN_NAND
 142 #define CONFIG_ENV_SIZE                 0x2000
 143 #define CONFIG_ENV_OFFSET               (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
 144 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 145 #define CONFIG_ENV_IS_IN_REMOTE
 146 #define CONFIG_ENV_ADDR         0xffe20000
 147 #define CONFIG_ENV_SIZE         0x2000
 148 #elif defined(CONFIG_ENV_IS_NOWHERE)
 149 #define CONFIG_ENV_SIZE         0x2000
 150 #else
 151 #define CONFIG_ENV_IS_IN_FLASH
 152 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 153 #define CONFIG_ENV_SIZE         0x2000
 154 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K (one sector) */
 155 #endif
 156
 157 #ifndef __ASSEMBLY__
 158 unsigned long get_board_sys_clk(void);
 159 unsigned long get_board_ddr_clk(void);
 160 #endif
 161 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk() /* sysclk for MPC85xx */
 162 #define CONFIG_DDR_CLK_FREQ     get_board_ddr_clk()
 163
 164 /*
 165  * These can be toggled for performance analysis, otherwise use default.
 166  */
 167 #define CONFIG_SYS_CACHE_STASHING
 168 #define CONFIG_BTB                      /* toggle branch predition */
 169 #define CONFIG_DDR_ECC
 170 #ifdef CONFIG_DDR_ECC
 171 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 172 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 173 #endif
 174
 175 #define CONFIG_ENABLE_36BIT_PHYS
 176
 177 #ifdef CONFIG_PHYS_64BIT
 178 #define CONFIG_ADDR_MAP
 179 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
 180 #endif
 181
 182 #if 0
 183 #define CONFIG_POST CONFIG_SYS_POST_MEMORY      /* test POST memory test */
 184 #endif
 185 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest works on */
 186 #define CONFIG_SYS_MEMTEST_END          0x00400000
 187 #define CONFIG_SYS_ALT_MEMTEST
 188 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 189
 190 /*
 191  *  Config the L3 Cache as L3 SRAM
 192  */
 193 #define CONFIG_SYS_INIT_L3_ADDR         0xFFFC0000
 194 #define CONFIG_SYS_L3_SIZE              256 << 10
 195 #define CONFIG_SPL_GD_ADDR              (CONFIG_SYS_INIT_L3_ADDR + 32 * 1024)
 196 #ifdef CONFIG_NAND
 197 #define CONFIG_ENV_ADDR                 (CONFIG_SPL_GD_ADDR + 4 * 1024)
 198 #endif
 199 #define CONFIG_SPL_RELOC_MALLOC_ADDR    (CONFIG_SPL_GD_ADDR + 12 * 1024)
 200 #define CONFIG_SPL_RELOC_MALLOC_SIZE    (30 << 10)
 201 #define CONFIG_SPL_RELOC_STACK          (CONFIG_SPL_GD_ADDR + 64 * 1024)
 202 #define CONFIG_SPL_RELOC_STACK_SIZE     (22 << 10)
 203
 204 #ifdef CONFIG_PHYS_64BIT
 205 #define CONFIG_SYS_DCSRBAR              0xf0000000
 206 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
 207 #endif
 208
 209 /* EEPROM */
 210 #define CONFIG_ID_EEPROM
 211 #define CONFIG_SYS_I2C_EEPROM_NXID
 212 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 213 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 214 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 215 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 216 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 217
 218 /*
 219  * DDR Setup
 220  */
 221 #define CONFIG_VERY_BIG_RAM
 222 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 223 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 224
 225 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 226 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
 227
 228 #define CONFIG_DDR_SPD
 229 #define CONFIG_SYS_DDR_RAW_TIMING
 230 #ifndef CONFIG_SPL_BUILD
 231 #define CONFIG_FSL_DDR_INTERACTIVE
 232 #endif
 233
 234 #define CONFIG_SYS_SPD_BUS_NUM  0
 235 #define SPD_EEPROM_ADDRESS1     0x51
 236 #define SPD_EEPROM_ADDRESS2     0x53
 237
 238 #define SPD_EEPROM_ADDRESS      SPD_EEPROM_ADDRESS1
 239 #define CONFIG_SYS_SDRAM_SIZE   2048    /* for fixed parameter use */
 240
 241 /*
 242  * IFC Definitions
 243  */
 244 #define CONFIG_SYS_FLASH_BASE   0xe0000000
 245 #ifdef CONFIG_PHYS_64BIT
 246 #define CONFIG_SYS_FLASH_BASE_PHYS      (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
 247 #else
 248 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 249 #endif
 250
 251 #define CONFIG_SYS_NOR0_CSPR_EXT        (0xf)
 252 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 253                                 + 0x8000000) | \
 254                                 CSPR_PORT_SIZE_16 | \
 255                                 CSPR_MSEL_NOR | \
 256                                 CSPR_V)
 257 #define CONFIG_SYS_NOR1_CSPR_EXT        (0xf)
 258 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 259                                 CSPR_PORT_SIZE_16 | \
 260                                 CSPR_MSEL_NOR | \
 261                                 CSPR_V)
 262 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128 * 1024 * 1024)
 263 /* NOR Flash Timing Params */
 264 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(4)
 265 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) | \
 266                                 FTIM0_NOR_TEADC(0x04) | \
 267                                 FTIM0_NOR_TEAHC(0x20))
 268 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x35) | \
 269                                 FTIM1_NOR_TRAD_NOR(0x1A) |\
 270                                 FTIM1_NOR_TSEQRAD_NOR(0x13))
 271 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x01) | \
 272                                 FTIM2_NOR_TCH(0x0E) | \
 273                                 FTIM2_NOR_TWPH(0x0E) | \
 274                                 FTIM2_NOR_TWP(0x1c))
 275 #define CONFIG_SYS_NOR_FTIM3    0x0
 276
 277 #define CONFIG_SYS_FLASH_QUIET_TEST
 278 #define CONFIG_FLASH_SHOW_PROGRESS      45 /* count down from 45/5: 9..1 */
 279
 280 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 281 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 282 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 283 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 284
 285 #define CONFIG_SYS_FLASH_EMPTY_INFO
 286 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS \
 287                                         + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
 288
 289 #define CONFIG_FSL_QIXIS        /* use common QIXIS code */
 290 #define CONFIG_FSL_QIXIS_V2
 291 #define QIXIS_BASE              0xffdf0000
 292 #ifdef CONFIG_PHYS_64BIT
 293 #define QIXIS_BASE_PHYS         (0xf00000000ull | QIXIS_BASE)
 294 #else
 295 #define QIXIS_BASE_PHYS         QIXIS_BASE
 296 #endif
 297 #define QIXIS_LBMAP_SWITCH              0x01
 298 #define QIXIS_LBMAP_MASK                0x0f
 299 #define QIXIS_LBMAP_SHIFT               0
 300 #define QIXIS_LBMAP_DFLTBANK            0x00
 301 #define QIXIS_LBMAP_ALTBANK             0x02
 302 #define QIXIS_RST_CTL_RESET             0x31
 303 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 304 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 305 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 306
 307 #define CONFIG_SYS_CSPR3_EXT    (0xf)
 308 #define CONFIG_SYS_CSPR3        (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) \
 309                                 | CSPR_PORT_SIZE_8 \
 310                                 | CSPR_MSEL_GPCM \
 311                                 | CSPR_V)
 312 #define CONFIG_SYS_AMASK3       IFC_AMASK(4 * 1024)
 313 #define CONFIG_SYS_CSOR3        0x0
 314 /* QIXIS Timing parameters for IFC CS3 */
 315 #define CONFIG_SYS_CS3_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 316                                         FTIM0_GPCM_TEADC(0x0e) | \
 317                                         FTIM0_GPCM_TEAHC(0x0e))
 318 #define CONFIG_SYS_CS3_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 319                                         FTIM1_GPCM_TRAD(0x1f))
 320 #define CONFIG_SYS_CS3_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 321                                         FTIM2_GPCM_TCH(0x8) | \
 322                                         FTIM2_GPCM_TWP(0x1f))
 323 #define CONFIG_SYS_CS3_FTIM3            0x0
 324
 325 /* NAND Flash on IFC */
 326 #define CONFIG_NAND_FSL_IFC
 327 #define CONFIG_SYS_NAND_MAX_ECCPOS      256
 328 #define CONFIG_SYS_NAND_MAX_OOBFREE     2
 329 #define CONFIG_SYS_NAND_BASE            0xff800000
 330 #ifdef CONFIG_PHYS_64BIT
 331 #define CONFIG_SYS_NAND_BASE_PHYS       (0xf00000000ull | CONFIG_SYS_NAND_BASE)
 332 #else
 333 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 334 #endif
 335
 336 #define CONFIG_SYS_NAND_CSPR_EXT        (0xf)
 337 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 338                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 339                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 340                                 | CSPR_V)
 341 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64 * 1024)
 342
 343 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 344                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 345                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 346                                 | CSOR_NAND_RAL_3       /* RAL = 2Byes */ \
 347                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 348                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 349                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 350
 351 #define CONFIG_SYS_NAND_ONFI_DETECTION
 352
 353 /* ONFI NAND Flash mode0 Timing Params */
 354 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x07) | \
 355                                         FTIM0_NAND_TWP(0x18)   | \
 356                                         FTIM0_NAND_TWCHT(0x07) | \
 357                                         FTIM0_NAND_TWH(0x0a))
 358 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 359                                         FTIM1_NAND_TWBE(0x39)  | \
 360                                         FTIM1_NAND_TRR(0x0e)   | \
 361                                         FTIM1_NAND_TRP(0x18))
 362 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x0f) | \
 363                                         FTIM2_NAND_TREH(0x0a) | \
 364                                         FTIM2_NAND_TWHRE(0x1e))
 365 #define CONFIG_SYS_NAND_FTIM3           0x0
 366
 367 #define CONFIG_SYS_NAND_DDR_LAW         11
 368
 369 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 370 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 371 #define CONFIG_CMD_NAND
 372
 373 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 374
 375 #if defined(CONFIG_NAND)
 376 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NAND_CSPR_EXT
 377 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 378 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 379 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 380 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 381 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 382 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 383 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 384 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 385 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NOR0_CSPR
 386 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NOR_AMASK
 387 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NOR_CSOR
 388 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NOR_FTIM0
 389 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NOR_FTIM1
 390 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NOR_FTIM2
 391 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NOR_FTIM3
 392 #else
 393 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 394 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 395 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 396 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 397 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 398 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 399 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 400 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 401 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 402 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 403 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 404 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 405 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 406 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 407 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 408 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 409 #endif
 410 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 411 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 412 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 413 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 414 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 415 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 416 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 417 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 418
 419 #ifdef CONFIG_SPL_BUILD
 420 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 421 #else
 422 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 423 #endif
 424
 425 #if defined(CONFIG_RAMBOOT_PBL)
 426 #define CONFIG_SYS_RAMBOOT
 427 #endif
 428
 429 #define CONFIG_BOARD_EARLY_INIT_R
 430 #define CONFIG_MISC_INIT_R
 431
 432 #define CONFIG_HWCONFIG
 433
 434 /* define to use L1 as initial stack */
 435 #define CONFIG_L1_INIT_RAM
 436 #define CONFIG_SYS_INIT_RAM_LOCK
 437 #define CONFIG_SYS_INIT_RAM_ADDR        0xfdd00000      /* Initial L1 address */
 438 #ifdef CONFIG_PHYS_64BIT
 439 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH      0xf
 440 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW       0xfe03c000
 441 /* The assembler doesn't like typecast */
 442 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 443         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 444           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 445 #else
 446 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   0xfe03c000 /* Initial L1 address */
 447 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 448 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 449 #endif
 450 #define CONFIG_SYS_INIT_RAM_SIZE                0x00004000
 451
 452 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 453                                         GENERATED_GBL_DATA_SIZE)
 454 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 455
 456 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 457 #define CONFIG_SYS_MALLOC_LEN           (4 * 1024 * 1024)
 458
 459 /* Serial Port - controlled on board with jumper J8
 460  * open - index 2
 461  * shorted - index 1
 462  */
 463 #define CONFIG_CONS_INDEX       1
 464 #define CONFIG_SYS_NS16550_SERIAL
 465 #define CONFIG_SYS_NS16550_REG_SIZE     1
 466 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0)/2)
 467
 468 #define CONFIG_SYS_BAUDRATE_TABLE       \
 469         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 470
 471 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
 472 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
 473 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
 474 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
 475
 476 /* I2C */
 477 #define CONFIG_SYS_I2C
 478 #define CONFIG_SYS_I2C_FSL              /* Use FSL common I2C driver */
 479 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C speed in Hz */
 480 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 481 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C speed in Hz */
 482 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 483 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 484 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x119000
 485
 486 /*
 487  * RTC configuration
 488  */
 489 #define RTC
 490 #define CONFIG_RTC_DS3231               1
 491 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 492
 493 /*
 494  * RapidIO
 495  */
 496 #ifdef CONFIG_SYS_SRIO
 497 #ifdef CONFIG_SRIO1
 498 #define CONFIG_SYS_SRIO1_MEM_VIRT       0xa0000000
 499 #ifdef CONFIG_PHYS_64BIT
 500 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xc20000000ull
 501 #else
 502 #define CONFIG_SYS_SRIO1_MEM_PHYS       0xa0000000
 503 #endif
 504 #define CONFIG_SYS_SRIO1_MEM_SIZE       0x10000000      /* 256M */
 505 #endif
 506
 507 #ifdef CONFIG_SRIO2
 508 #define CONFIG_SYS_SRIO2_MEM_VIRT       0xb0000000
 509 #ifdef CONFIG_PHYS_64BIT
 510 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xc30000000ull
 511 #else
 512 #define CONFIG_SYS_SRIO2_MEM_PHYS       0xb0000000
 513 #endif
 514 #define CONFIG_SYS_SRIO2_MEM_SIZE       0x10000000      /* 256M */
 515 #endif
 516 #endif
 517
 518 /*
 519  * for slave u-boot IMAGE instored in master memory space,
 520  * PHYS must be aligned based on the SIZE
 521  */
 522 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_PHYS 0xfef200000ull
 523 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS1 0xfff00000ull
 524 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_SIZE 0x100000       /* 1M */
 525 #define CONFIG_SRIO_PCIE_BOOT_IMAGE_MEM_BUS2 0x3fff00000ull
 526 /*
 527  * for slave UCODE and ENV instored in master memory space,
 528  * PHYS must be aligned based on the SIZE
 529  */
 530 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_PHYS 0xfef100000ull
 531 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_MEM_BUS 0x3ffe00000ull
 532 #define CONFIG_SRIO_PCIE_BOOT_UCODE_ENV_SIZE 0x40000    /* 256K */
 533
 534 /* slave core release by master*/
 535 #define CONFIG_SRIO_PCIE_BOOT_BRR_OFFSET 0xe00e4
 536 #define CONFIG_SRIO_PCIE_BOOT_RELEASE_MASK 0x00000001 /* release core 0 */
 537
 538 /*
 539  * SRIO_PCIE_BOOT - SLAVE
 540  */
 541 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 542 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR 0xFFE00000
 543 #define CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS \
 544                 (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR)
 545 #endif
 546
 547 /*
 548  * eSPI - Enhanced SPI
 549  */
 550 #define CONFIG_SF_DEFAULT_SPEED         10000000
 551 #define CONFIG_SF_DEFAULT_MODE          0
 552
 553 /*
 554  * MAPLE
 555  */
 556 #ifdef CONFIG_PHYS_64BIT
 557 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xFA0000000ull
 558 #else
 559 #define CONFIG_SYS_MAPLE_MEM_PHYS      0xA0000000
 560 #endif
 561
 562 /*
 563  * General PCI
 564  * Memory space is mapped 1-1, but I/O space must start from 0.
 565  */
 566
 567 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 568 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 569 #ifdef CONFIG_PHYS_64BIT
 570 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 571 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 572 #else
 573 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 574 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 575 #endif
 576 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 577 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 578 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 579 #ifdef CONFIG_PHYS_64BIT
 580 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 581 #else
 582 #define CONFIG_SYS_PCIE1_IO_PHYS        0xf8000000
 583 #endif
 584 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 585
 586 /* Qman/Bman */
 587 #ifndef CONFIG_NOBQFMAN
 588 #define CONFIG_SYS_DPAA_QBMAN           /* Support Q/Bman */
 589 #define CONFIG_SYS_BMAN_NUM_PORTALS     25
 590 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 591 #ifdef CONFIG_PHYS_64BIT
 592 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 593 #else
 594 #define CONFIG_SYS_BMAN_MEM_PHYS        CONFIG_SYS_BMAN_MEM_BASE
 595 #endif
 596 #define CONFIG_SYS_BMAN_MEM_SIZE        0x02000000
 597 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 598 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 599 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 600 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 601 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 602                                         CONFIG_SYS_BMAN_CENA_SIZE)
 603 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 604 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 605 #define CONFIG_SYS_QMAN_NUM_PORTALS     25
 606 #define CONFIG_SYS_QMAN_MEM_BASE        0xf6000000
 607 #ifdef CONFIG_PHYS_64BIT
 608 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff6000000ull
 609 #else
 610 #define CONFIG_SYS_QMAN_MEM_PHYS        CONFIG_SYS_QMAN_MEM_BASE
 611 #endif
 612 #define CONFIG_SYS_QMAN_MEM_SIZE        0x02000000
 613 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 614 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 615 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 616 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 617 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 618                                         CONFIG_SYS_QMAN_CENA_SIZE)
 619 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 620 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 621
 622 #define CONFIG_SYS_DPAA_FMAN
 623
 624 #define CONFIG_SYS_DPAA_RMAN
 625
 626 /* Default address of microcode for the Linux Fman driver */
 627 #if defined(CONFIG_SPIFLASH)
 628 /*
 629  * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
 630  * env, so we got 0x110000.
 631  */
 632 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
 633 #define CONFIG_SYS_FMAN_FW_ADDR 0x110000
 634 #elif defined(CONFIG_SDCARD)
 635 /*
 636  * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
 637  * about 545KB (1089 blocks), Env is stored after the image, and the env size is
 638  * 0x2000 (16 blocks), 8 + 1089 + 16 = 1113, enlarge it to 1130.
 639  */
 640 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
 641 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1130)
 642 #elif defined(CONFIG_NAND)
 643 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
 644 #define CONFIG_SYS_FMAN_FW_ADDR (13 * CONFIG_SYS_NAND_BLOCK_SIZE)
 645 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
 646 /*
 647  * Slave has no ucode locally, it can fetch this from remote. When implementing
 648  * in two corenet boards, slave's ucode could be stored in master's memory
 649  * space, the address can be mapped from slave TLB->slave LAW->
 650  * slave SRIO or PCIE outbound window->master inbound window->
 651  * master LAW->the ucode address in master's memory space.
 652  */
 653 #define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE
 654 #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000
 655 #else
 656 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 657 #define CONFIG_SYS_FMAN_FW_ADDR         0xEFF00000
 658 #endif
 659 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 660 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 661 #endif /* CONFIG_NOBQFMAN */
 662
 663 #ifdef CONFIG_SYS_DPAA_FMAN
 664 #define CONFIG_FMAN_ENET
 665 #define CONFIG_PHYLIB_10G
 666 #define CONFIG_PHY_VITESSE
 667 #define CONFIG_PHY_TERANETICS
 668 #define SGMII_CARD_PORT1_PHY_ADDR 0x1C
 669 #define SGMII_CARD_PORT2_PHY_ADDR 0x10
 670 #define SGMII_CARD_PORT3_PHY_ADDR 0x1E
 671 #define SGMII_CARD_PORT4_PHY_ADDR 0x11
 672 #endif
 673
 674 #ifdef CONFIG_PCI
 675 #define CONFIG_PCI_INDIRECT_BRIDGE
 676
 677 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 678 #define CONFIG_DOS_PARTITION
 679 #endif  /* CONFIG_PCI */
 680
 681 #ifdef CONFIG_FMAN_ENET
 682 #define CONFIG_SYS_FM1_ONBOARD_PHY1_ADDR 0x10
 683 #define CONFIG_SYS_FM1_ONBOARD_PHY2_ADDR 0x11
 684
 685 /*B4860 QDS AMC2PEX-2S default PHY_ADDR */
 686 #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0x7       /*SLOT 1*/
 687 #define CONFIG_SYS_FM1_10GEC2_PHY_ADDR 0x6       /*SLOT 2*/
 688
 689 #define CONFIG_SYS_FM1_DTSEC1_RISER_PHY_ADDR    0x1c
 690 #define CONFIG_SYS_FM1_DTSEC2_RISER_PHY_ADDR    0x1d
 691 #define CONFIG_SYS_FM1_DTSEC3_RISER_PHY_ADDR    0x1e
 692 #define CONFIG_SYS_FM1_DTSEC4_RISER_PHY_ADDR    0x1f
 693
 694 #define CONFIG_MII              /* MII PHY management */
 695 #define CONFIG_ETHPRIME         "FM1@DTSEC1"
 696 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 697 #endif
 698
 699 #define CONFIG_SYS_FSL_B4860QDS_XFI_ERR
 700
 701 /*
 702  * Environment
 703  */
 704 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 705 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 706
 707 /*
 708  * Command line configuration.
 709  */
 710 #define CONFIG_CMD_DATE
 711 #define CONFIG_CMD_EEPROM
 712 #define CONFIG_CMD_ERRATA
 713 #define CONFIG_CMD_IRQ
 714 #define CONFIG_CMD_REGINFO
 715
 716 #ifdef CONFIG_PCI
 717 #define CONFIG_CMD_PCI
 718 #endif
 719
 720 /* Hash command with SHA acceleration supported in hardware */
 721 #ifdef CONFIG_FSL_CAAM
 722 #define CONFIG_CMD_HASH
 723 #define CONFIG_SHA_HW_ACCEL
 724 #endif
 725
 726 /*
 727 * USB
 728 */
 729 #define CONFIG_HAS_FSL_DR_USB
 730
 731 #ifdef CONFIG_HAS_FSL_DR_USB
 732 #define CONFIG_USB_EHCI
 733
 734 #ifdef CONFIG_USB_EHCI
 735 #define CONFIG_USB_EHCI_FSL
 736 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 737 #endif
 738 #endif
 739
 740 /*
 741  * Miscellaneous configurable options
 742  */
 743 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 744 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 745 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 746 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 747 #ifdef CONFIG_CMD_KGDB
 748 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 749 #else
 750 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 751 #endif
 752 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 753 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 754 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 755
 756 /*
 757  * For booting Linux, the board info and command line data
 758  * have to be in the first 64 MB of memory, since this is
 759  * the maximum mapped by the Linux kernel during initialization.
 760  */
 761 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial map for Linux*/
 762 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 763
 764 #ifdef CONFIG_CMD_KGDB
 765 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 766 #endif
 767
 768 /*
 769  * Environment Configuration
 770  */
 771 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 772 #define CONFIG_BOOTFILE         "uImage"
 773 #define CONFIG_UBOOTPATH        "u-boot.bin"    /* U-Boot image on TFTP server*/
 774
 775 /* default location for tftp and bootm */
 776 #define CONFIG_LOADADDR         1000000
 777
 778
 779 #define CONFIG_BAUDRATE 115200
 780
 781 #define __USB_PHY_TYPE  ulpi
 782
 783 #ifdef CONFIG_ARCH_B4860
 784 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,"     \
 785                         "bank_intlv=cs0_cs1;"   \
 786                         "en_cpc:cpc2;"
 787 #else
 788 #define HWCONFIG        "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=cs0_cs1;"
 789 #endif
 790
 791 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 792         HWCONFIG                                                \
 793         "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
 794         "netdev=eth0\0"                                         \
 795         "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"                     \
 796         "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"                     \
 797         "tftpflash=tftpboot $loadaddr $uboot && "               \
 798         "protect off $ubootaddr +$filesize && "                 \
 799         "erase $ubootaddr +$filesize && "                       \
 800         "cp.b $loadaddr $ubootaddr $filesize && "               \
 801         "protect on $ubootaddr +$filesize && "                  \
 802         "cmp.b $loadaddr $ubootaddr $filesize\0"                \
 803         "consoledev=ttyS0\0"                                    \
 804         "ramdiskaddr=2000000\0"                                 \
 805         "ramdiskfile=b4860qds/ramdisk.uboot\0"                  \
 806         "fdtaddr=1e00000\0"                                     \
 807         "fdtfile=b4860qds/b4860qds.dtb\0"                               \
 808         "bdev=sda3\0"
 809
 810 /* For emulation this causes u-boot to jump to the start of the proof point
 811    app code automatically */
 812 #define CONFIG_PROOF_POINTS                     \
 813  "setenv bootargs root=/dev/$bdev rw "          \
 814  "console=$consoledev,$baudrate $othbootargs;"  \
 815  "cpu 1 release 0x29000000 - - -;"              \
 816  "cpu 2 release 0x29000000 - - -;"              \
 817  "cpu 3 release 0x29000000 - - -;"              \
 818  "cpu 4 release 0x29000000 - - -;"              \
 819  "cpu 5 release 0x29000000 - - -;"              \
 820  "cpu 6 release 0x29000000 - - -;"              \
 821  "cpu 7 release 0x29000000 - - -;"              \
 822  "go 0x29000000"
 823
 824 #define CONFIG_HVBOOT   \
 825  "setenv bootargs config-addr=0x60000000; "     \
 826  "bootm 0x01000000 - 0x00f00000"
 827
 828 #define CONFIG_ALU                              \
 829  "setenv bootargs root=/dev/$bdev rw "          \
 830  "console=$consoledev,$baudrate $othbootargs;"  \
 831  "cpu 1 release 0x01000000 - - -;"              \
 832  "cpu 2 release 0x01000000 - - -;"              \
 833  "cpu 3 release 0x01000000 - - -;"              \
 834  "cpu 4 release 0x01000000 - - -;"              \
 835  "cpu 5 release 0x01000000 - - -;"              \
 836  "cpu 6 release 0x01000000 - - -;"              \
 837  "cpu 7 release 0x01000000 - - -;"              \
 838  "go 0x01000000"
 839
 840 #define CONFIG_LINUX                            \
 841  "setenv bootargs root=/dev/ram rw "            \
 842  "console=$consoledev,$baudrate $othbootargs;"  \
 843  "setenv ramdiskaddr 0x02000000;"               \
 844  "setenv fdtaddr 0x01e00000;"                   \
 845  "setenv loadaddr 0x1000000;"                   \
 846  "bootm $loadaddr $ramdiskaddr $fdtaddr"
 847
 848 #define CONFIG_HDBOOT                                   \
 849         "setenv bootargs root=/dev/$bdev rw "           \
 850         "console=$consoledev,$baudrate $othbootargs;"   \
 851         "tftp $loadaddr $bootfile;"                     \
 852         "tftp $fdtaddr $fdtfile;"                       \
 853         "bootm $loadaddr - $fdtaddr"
 854
 855 #define CONFIG_NFSBOOTCOMMAND                   \
 856         "setenv bootargs root=/dev/nfs rw "     \
 857         "nfsroot=$serverip:$rootpath "          \
 858         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 859         "console=$consoledev,$baudrate $othbootargs;"   \
 860         "tftp $loadaddr $bootfile;"             \
 861         "tftp $fdtaddr $fdtfile;"               \
 862         "bootm $loadaddr - $fdtaddr"
 863
 864 #define CONFIG_RAMBOOTCOMMAND                           \
 865         "setenv bootargs root=/dev/ram rw "             \
 866         "console=$consoledev,$baudrate $othbootargs;"   \
 867         "tftp $ramdiskaddr $ramdiskfile;"               \
 868         "tftp $loadaddr $bootfile;"                     \
 869         "tftp $fdtaddr $fdtfile;"                       \
 870         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 871
 872 #define CONFIG_BOOTCOMMAND              CONFIG_LINUX
 873
 874 #include <asm/fsl_secure_boot.h>
 875
 876 #endif  /* __CONFIG_H */