include/configs/BC3450.h

   1 /*
   2  * -- Version 1.1 --
   3  *
   4  * (C) Copyright 2003-2005
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * (C) Copyright 2004-2005
   8  * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de
   9  *
  10  * (C) Copyright 2005
  11  * Stefan Strobl, GERSYS GmbH, stefan.strobl@gersys.de.
  12  *
  13  * History:
  14  *      1.1 - add define CONFIG_ZERO_BOOTDELAY_CHECK
  15  *
  16  * See file CREDITS for list of people who contributed to this
  17  * project.
  18  *
  19  * This program is free software; you can redistribute it and/or
  20  * modify it under the terms of the GNU General Public License as
  21  * published by the Free Software Foundation; either version 2 of
  22  * the License, or (at your option) any later version.
  23  *
  24  * This program is distributed in the hope that it will be useful,
  25  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  26  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  27  * GNU General Public License for more details.
  28  *
  29  * You should have received a copy of the GNU General Public License
  30  * along with this program; if not, write to the Free Software
  31  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  32  * MA 02111-1307 USA
  33  */
  34
  35 #ifndef __CONFIG_H
  36 #define __CONFIG_H
  37
  38 /*
  39  * High Level Configuration Options
  40  */
  41 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU           */
  42 #define CONFIG_MPC5200          1       /* (more precisely a MPC5200 CPU)   */
  43 #define CONFIG_TQM5200          1       /* ... on a TQM5200 module          */
  44
  45 #define CONFIG_BC3450           1       /* ... on a BC3450 mainboard        */
  46 #define CONFIG_BC3450_PS2       1       /*  + a PS/2 converter onboard      */
  47 #define CONFIG_BC3450_IDE       1       /*  + IDE drives (Compact Flash)    */
  48 #define CONFIG_BC3450_USB       1       /*  + USB support                   */
  49 # define CONFIG_FAT             1       /*    + FAT support                 */
  50 # define CONFIG_EXT2            1       /*    + EXT2 support                */
  51 #undef CONFIG_BC3450_BUZZER             /*  + Buzzer onboard                */
  52 #undef CONFIG_BC3450_CAN                /*  + CAN transceiver               */
  53 #undef CONFIG_BC3450_DS1340             /*  + a RTC DS1340 onboard          */
  54 #undef CONFIG_BC3450_DS3231             /*  + a RTC DS3231 onboard      tbd */
  55 #undef CONFIG_BC3450_AC97               /*  + AC97 on PSC2,             tbd */
  56 #define CONFIG_BC3450_FP        1       /*  + enable FP O/P                 */
  57 #undef CONFIG_BC3450_CRT                /*  + enable CRT O/P (Debug only!)  */
  58
  59 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz     */
  60
  61 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
  62 #define BOOTFLAG_WARM           0x02    /* Software reboot                  */
  63
  64 #define CONFIG_HIGH_BATS        1       /* High BATs supported              */
  65
  66 /*
  67  * Serial console configuration
  68  */
  69 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1           */
  70 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps            */
  71 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  72
  73 /*
  74  * AT-PS/2 Multiplexer
  75  */
  76 #ifdef CONFIG_BC3450_PS2
  77 # define CONFIG_PS2KBD                  /* AT-PS/2 Keyboard             */
  78 # define CONFIG_PS2MULT                 /* .. on PS/2 Multiplexer       */
  79 # define CONFIG_PS2SERIAL       6               /* .. on PSC6           */
  80 # define CONFIG_PS2MULT_DELAY   (CONFIG_SYS_HZ/2)       /* Initial delay        */
  81 # define CONFIG_BOARD_EARLY_INIT_R
  82 #endif /* CONFIG_BC3450_PS2 */
  83
  84 /*
  85  * PCI Mapping:
  86  * 0x40000000 - 0x4fffffff - PCI Memory
  87  * 0x50000000 - 0x50ffffff - PCI IO Space
  88  */
  89 # define CONFIG_PCI             1
  90 # define CONFIG_PCI_PNP         1
  91 /* #define CONFIG_PCI_SCAN_SHOW 1 */
  92 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  93
  94 #define CONFIG_PCI_MEM_BUS      0x40000000
  95 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  96 #define CONFIG_PCI_MEM_SIZE     0x10000000
  97
  98 #define CONFIG_PCI_IO_BUS       0x50000000
  99 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
 100 #define CONFIG_PCI_IO_SIZE      0x01000000
 101
 102 #define CONFIG_NET_MULTI        1
 103 /*#define CONFIG_EEPRO100       XXX - FIXME: conflicts when CONFIG_MII is enabled */
 104 #define CONFIG_SYS_RX_ETH_BUFFER        8       /* use 8 rx buffer on eepro100  */
 105 #define CONFIG_NS8382X          1
 106
 107 /*
 108  * Video console
 109  */
 110 # define CONFIG_VIDEO
 111 # define CONFIG_VIDEO_SM501
 112 # define CONFIG_VIDEO_SM501_32BPP
 113 # define CONFIG_CFB_CONSOLE
 114 # define CONFIG_VIDEO_LOGO
 115 # define CONFIG_VGA_AS_SINGLE_DEVICE
 116 # define CONFIG_CONSOLE_EXTRA_INFO      /* display Board/Device-Infos */
 117 # define CONFIG_VIDEO_SW_CURSOR
 118 # define CONFIG_SPLASH_SCREEN
 119 # define CONFIG_SYS_CONSOLE_IS_IN_ENV
 120
 121 /*
 122  * Partitions
 123  */
 124 #define CONFIG_MAC_PARTITION
 125 #define CONFIG_DOS_PARTITION
 126 #define CONFIG_ISO_PARTITION
 127
 128 /*
 129  * USB
 130  */
 131 #ifdef CONFIG_BC3450_USB
 132 # define CONFIG_USB_OHCI
 133 # define CONFIG_USB_STORAGE
 134 #endif /* CONFIG_BC3450_USB */
 135
 136 /*
 137  * POST support
 138  */
 139 #define CONFIG_POST             (CONFIG_SYS_POST_MEMORY   | \
 140                                  CONFIG_SYS_POST_CPU       | \
 141                                  CONFIG_SYS_POST_I2C)
 142
 143 #ifdef CONFIG_POST
 144 /* preserve space for the post_word at end of on-chip SRAM */
 145 # define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4
 146 #endif /* CONFIG_POST */
 147
 148
 149 /*
 150  * BOOTP options
 151  */
 152 #define CONFIG_BOOTP_BOOTFILESIZE
 153 #define CONFIG_BOOTP_BOOTPATH
 154 #define CONFIG_BOOTP_GATEWAY
 155 #define CONFIG_BOOTP_HOSTNAME
 156
 157
 158 /*
 159  * Command line configuration.
 160  */
 161 #include <config_cmd_default.h>
 162
 163 #define CONFIG_CMD_ASKENV
 164 #define CONFIG_CMD_DATE
 165 #define CONFIG_CMD_DHCP
 166 #define CONFIG_CMD_ECHO
 167 #define CONFIG_CMD_EEPROM
 168 #define CONFIG_CMD_I2C
 169 #define CONFIG_CMD_JFFS2
 170 #define CONFIG_CMD_MII
 171 #define CONFIG_CMD_NFS
 172 #define CONFIG_CMD_PING
 173 #define CONFIG_CMD_REGINFO
 174 #define CONFIG_CMD_SNTP
 175 #define CONFIG_CMD_BSP
 176
 177 #ifdef CONFIG_VIDEO
 178     #define CONFIG_CMD_BMP
 179 #endif
 180
 181 #ifdef CONFIG_BC3450_IDE
 182     #define CONFIG_CMD_IDE
 183 #endif
 184
 185 #if defined(CONFIG_BC3450_IDE) || defined(CONFIG_BC3450_USB)
 186     #ifdef CONFIG_FAT
 187         #define CONFIG_CMD_FAT
 188     #endif
 189
 190     #ifdef CONFIG_EXT2
 191         #define CONFIG_CMD_EXT2
 192     #endif
 193 #endif
 194
 195 #ifdef CONFIG_BC3450_USB
 196     #define CONFIG_CMD_USB
 197 #endif
 198
 199 #ifdef CONFIG_PCI
 200     #define CONFIG_CMD_PCI
 201 #endif
 202
 203 #ifdef CONFIG_POST
 204     #define CONFIG_CMD_DIAG
 205 #endif
 206
 207
 208 #define CONFIG_TIMESTAMP                /* display image timestamps */
 209
 210 #if (TEXT_BASE == 0xFC000000)           /* Boot low */
 211 #   define CONFIG_SYS_LOWBOOT           1
 212 #endif
 213
 214 /*
 215  * Autobooting
 216  */
 217 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 218 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 219
 220 #define CONFIG_PREBOOT  "echo;" \
 221         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 222         "echo;"
 223
 224 #undef  CONFIG_BOOTARGS
 225
 226 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 227         "netdev=eth0\0"                                                 \
 228         "ipaddr=192.168.1.10\0"                                         \
 229         "serverip=192.168.1.3\0"                                        \
 230         "netmask=255.255.255.0\0"                                       \
 231         "hostname=bc3450\0"                                             \
 232         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 233         "kernel_addr=fc0a0000\0"                                        \
 234         "ramdisk_addr=fc1c0000\0"                                       \
 235         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 236         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 237                 "nfsroot=$(serverip):$(rootpath)\0"                     \
 238         "ideargs=setenv bootargs root=/dev/hda2 ro\0"                   \
 239         "addip=setenv bootargs $(bootargs) "                            \
 240                 "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"      \
 241                 ":$(hostname):$(netdev):off panic=1\0"                  \
 242         "addcons=setenv bootargs $(bootargs) "                          \
 243                 "console=ttyS0,$(baudrate) console=tty0\0"              \
 244         "flash_self=run ramargs addip addcons;"                         \
 245                 "bootm $(kernel_addr) $(ramdisk_addr)\0"                \
 246         "flash_nfs=run nfsargs addip addcons; bootm $(kernel_addr)\0"   \
 247         "net_nfs=tftp 200000 $(bootfile); "                             \
 248                 "run nfsargs addip addcons; bootm\0"                    \
 249         "ide_nfs=run nfsargs addip addcons; "                           \
 250                 "disk 200000 0:1; bootm\0"                              \
 251         "ide_ide=run ideargs addip addcons; "                           \
 252                 "disk 200000 0:1; bootm\0"                              \
 253         "usb_self=run usbload; run ramargs addip addcons; "             \
 254                 "bootm 200000 400000\0"                                 \
 255         "usbload=usb reset; usb scan; usbboot 200000 0:1; "             \
 256                 "usbboot 400000 0:2\0"                                  \
 257         "bootfile=uImage\0"                                             \
 258         "load=tftp 200000 $(u-boot)\0"                                  \
 259         "u-boot=u-boot.bin\0"                                           \
 260         "update=protect off FC000000 FC05FFFF;"                         \
 261                 "erase FC000000 FC05FFFF;"                              \
 262                 "cp.b 200000 FC000000 $(filesize);"                     \
 263                 "protect on FC000000 FC05FFFF\0"                        \
 264         ""
 265
 266 #define CONFIG_BOOTCOMMAND      "run flash_self"
 267
 268 /*
 269  * IPB Bus clocking configuration.
 270  */
 271 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 272
 273 /*
 274  * PCI Bus clocking configuration
 275  *
 276  * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if
 277  * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock
 278  *  of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz.
 279  */
 280 #if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK)
 281 # define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2   /* define for 66MHz speed */
 282 #endif
 283
 284 /*
 285  * I2C configuration
 286  */
 287 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 288 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #2 */
 289
 290 /*
 291  * I2C clock frequency
 292  *
 293  * Please notice, that the resulting clock frequency could differ from the
 294  * configured value. This is because the I2C clock is derived from system
 295  * clock over a frequency divider with only a few divider values. U-boot
 296  * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated
 297  * approximation allways lies below the configured value, never above.
 298  */
 299 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 300 #define CONFIG_SYS_I2C_SLAVE            0x7F
 301
 302 /*
 303  * EEPROM configuration for I²C EEPROM M24C32
 304  * M24C64 should work also. For other EEPROMs config should be verified.
 305  *
 306  * The TQM5200 module may hold an EEPROM at address 0x50.
 307  */
 308 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x (TQM) */
 309 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 310 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* =32 Bytes per write */
 311 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   70
 312
 313 /*
 314  * RTC configuration
 315  */
 316 #if defined (CONFIG_BC3450_DS1340) && !defined (CONFIG_BC3450_DS3231)
 317 # define CONFIG_RTC_M41T11      1
 318 # define CONFIG_SYS_I2C_RTC_ADDR        0x68
 319 #else
 320 # define CONFIG_RTC_MPC5200     1       /* use MPC5200 internal RTC */
 321 # define CONFIG_BOARD_EARLY_INIT_R
 322 #endif
 323
 324 /*
 325  * Flash configuration
 326  */
 327 #define CONFIG_SYS_FLASH_BASE           TEXT_BASE /* 0xFC000000 */
 328
 329 /* use CFI flash driver if no module variant is spezified */
 330 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 331 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 332 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_BOOTCS_START }
 333 #define CONFIG_SYS_FLASH_EMPTY_INFO
 334 #define CONFIG_SYS_FLASH_SIZE           0x04000000 /* 64 MByte */
 335 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sects on one chip */
 336 #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE        /* not supported yet for AMD */
 337
 338 #if !defined(CONFIG_SYS_LOWBOOT)
 339 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000)
 340 #else   /* CONFIG_SYS_LOWBOOT */
 341 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00060000)
 342 #endif  /* CONFIG_SYS_LOWBOOT */
 343 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks
 344                                            (= chip selects) */
 345 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 346 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 347
 348 /* Dynamic MTD partition support */
 349 #define CONFIG_CMD_MTDPARTS
 350 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 351 #define CONFIG_FLASH_CFI_MTD
 352 #define MTDIDS_DEFAULT          "nor0=TQM5200-0"
 353 #define MTDPARTS_DEFAULT        "mtdparts=TQM5200-0:640k(firmware),"    \
 354                                                 "1408k(kernel),"        \
 355                                                 "2m(initrd),"           \
 356                                                 "4m(small-fs),"         \
 357                                                 "16m(big-fs),"          \
 358                                                 "8m(misc)"
 359
 360 /*
 361  * Environment settings
 362  */
 363 #define CONFIG_ENV_IS_IN_FLASH  1
 364 #define CONFIG_ENV_SIZE         0x10000
 365 #define CONFIG_ENV_SECT_SIZE    0x20000
 366 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 367 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 368
 369 /*
 370  * Memory map
 371  */
 372 #define CONFIG_SYS_MBAR         0xF0000000
 373 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 374 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 375
 376 /* Use ON-Chip SRAM until RAM will be available */
 377 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 378 #ifdef CONFIG_POST
 379 /* preserve space for the post_word at end of on-chip SRAM */
 380 # define CONFIG_SYS_INIT_RAM_END        MPC5XXX_SRAM_POST_SIZE
 381 #else
 382 # define CONFIG_SYS_INIT_RAM_END        MPC5XXX_SRAM_SIZE
 383 #endif /*CONFIG_POST*/
 384
 385 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* Bytes reserved for initial data  */
 386 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 387 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 388
 389 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
 390 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 391 #   define CONFIG_SYS_RAMBOOT           1
 392 #endif
 393
 394 #define CONFIG_SYS_MONITOR_LEN          (384 << 10) /* Reserve 384 kB for Monitor   */
 395 #define CONFIG_SYS_MALLOC_LEN           (128 << 10) /* Reserve 128 kB for malloc()  */
 396 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)   /* Initial Memory map for Linux */
 397
 398 /*
 399  * Ethernet configuration
 400  *
 401  * Define CONFIG_MPC5xxx_MII10 to force FEC at 10MBIT
 402  */
 403 #define CONFIG_MPC5xxx_FEC      1
 404 #define CONFIG_MPC5xxx_FEC_MII100
 405 #undef CONFIG_MPC5xxx_MII10
 406 #define CONFIG_PHY_ADDR         0x00
 407
 408 /*
 409  * GPIO configuration on BC3450
 410  *
 411  *  PSC1:   UART1 (Service-UART)         [0x xxxxxxx4]
 412  *  PSC2:   UART2                        [0x xxxxxx4x]
 413  *    or:   AC/97 if CONFIG_BC3450_AC97  [0x xxxxxx2x]
 414  *  PSC3:   USB2                         [0x xxxxx1xx]
 415  *  USB:    UART4(ext.)/UART5(int.)      [0x xxxx2xxx]
 416  *            (this has to match
 417  *            CONFIG_USB_CONFIG which is
 418  *            used by usb_ohci.c to set
 419  *            the USB ports)
 420  *  Eth:    10/100Mbit Ethernet          [0x xxx0xxxx]
 421  *            (this is reset to '5'
 422  *            in FEC driver: fec.c)
 423  *  PSC6:   UART6 (int. to PS/2 contr.)  [0x xx5xxxxx]
 424  *  ATA/CS: ???                          [0x x1xxxxxx]
 425  *          FIXME! UM Fig 2-10 suggests  [0x x0xxxxxx]
 426  *  CS1:    Use Pin gpio_wkup_6 as second
 427  *          SDRAM chip select (mem_cs1)
 428  *  Timer:  CAN2 / SPI
 429  *  I2C:    CAN1 / I²C2                  [0x bxxxxxxx]
 430  */
 431 #ifdef CONFIG_BC3450_AC97
 432 # define CONFIG_SYS_GPS_PORT_CONFIG     0xb1502124
 433 #else /* PSC2=UART2 */
 434 # define CONFIG_SYS_GPS_PORT_CONFIG     0xb1502144
 435 #endif
 436
 437 /*
 438  * Miscellaneous configurable options
 439  */
 440 #define CONFIG_SYS_LONGHELP                             /* undef to save memory     */
 441 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt   */
 442 #if defined(CONFIG_CMD_KGDB)
 443 #define CONFIG_SYS_CBSIZE               1024            /* Console I/O Buffer Size  */
 444 #else
 445 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size  */
 446 #endif
 447 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size  */
 448 #define CONFIG_SYS_MAXARGS              16              /* max no of command args   */
 449 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Arg. Buffer Size    */
 450
 451 #define CONFIG_SYS_ALT_MEMTEST                          /* Enable an alternative,   */
 452                                                 /*  more extensive mem test */
 453
 454 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on         */
 455 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM      */
 456
 457 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address     */
 458
 459 #define CONFIG_SYS_HZ                   1000            /* dec freq: 1ms ticks      */
 460
 461 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs                 */
 462 #if defined(CONFIG_CMD_KGDB)
 463 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value    */
 464 #endif
 465
 466 /*
 467  * Enable loopw command.
 468  */
 469 #define CONFIG_LOOPW
 470
 471 /*
 472  * Various low-level settings
 473  */
 474 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 475 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 476
 477 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 478 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 479 #ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2
 480 # define CONFIG_SYS_BOOTCS_CFG          0x0008DF30      /* for pci_clk  = 66 MHz */
 481 #else
 482 # define CONFIG_SYS_BOOTCS_CFG          0x0004DF30      /* for pci_clk = 33 MHz  */
 483 #endif
 484 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 485 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 486
 487 /* automatic configuration of chip selects */
 488 #ifdef CONFIG_TQM5200
 489 # define CONFIG_LAST_STAGE_INIT
 490 #endif /* CONFIG_TQM5200 */
 491
 492 /*
 493  * SRAM - Do not map below 2 GB in address space, because this area is used
 494  * for SDRAM autosizing.
 495  */
 496 #ifdef CONFIG_TQM5200
 497 # define CONFIG_SYS_CS2_START           0xE5000000
 498 # define CONFIG_SYS_CS2_SIZE            0x100000        /* 1 MByte */
 499 # define CONFIG_SYS_CS2_CFG             0x0004D930
 500 #endif /* CONFIG_TQM5200 */
 501
 502 /*
 503  * Grafic controller - Do not map below 2 GB in address space, because this
 504  * area is used for SDRAM autosizing.
 505  */
 506 #ifdef CONFIG_TQM5200
 507 # define SM501_FB_BASE          0xE0000000
 508 # define CONFIG_SYS_CS1_START           (SM501_FB_BASE)
 509 # define CONFIG_SYS_CS1_SIZE            0x4000000       /* 64 MByte */
 510 # define CONFIG_SYS_CS1_CFG             0x8F48FF70
 511 # define SM501_MMIO_BASE        CONFIG_SYS_CS1_START + 0x03E00000
 512 #endif /* CONFIG_TQM5200 */
 513
 514 #define CONFIG_SYS_CS_BURST             0x00000000
 515 #define CONFIG_SYS_CS_DEADCYCLE 0x33333311      /* 1 dead cycle for     */
 516                                                 /*  flash and SM501     */
 517
 518 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 519
 520 /*
 521  * USB stuff
 522  */
 523 #define CONFIG_USB_CLOCK        0x0001BBBB
 524 #define CONFIG_USB_CONFIG       0x00002000      /* we're using Port 2   */
 525
 526 /*
 527  * IDE/ATA stuff Supports IDE harddisk
 528  */
 529 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 530
 531 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE     not supported */
 532 #undef  CONFIG_IDE_LED                  /* LED for ide    not supported */
 533
 534 #define CONFIG_IDE_RESET                /* reset for ide      supported */
 535 #define CONFIG_IDE_PREINIT
 536
 537 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 538 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 2 drives per IDE bus    */
 539
 540 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 541
 542 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 543
 544 /* Offset for data I/O */
 545 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 546
 547 /* Offset for normal register accesses */
 548 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 549
 550 /* Offset for alternate registers */
 551 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 552
 553 /* Interval between registers */
 554 #define CONFIG_SYS_ATA_STRIDE           4
 555
 556 #endif /* __CONFIG_H */