include/configs/BMW.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  *
  26  * Configuration settings for the CU824 board.
  27  *
  28  */
  29
  30 /* ------------------------------------------------------------------------- */
  31
  32 /*
  33  * board/config.h - configuration options, board specific
  34  */
  35
  36 #ifndef __CONFIG_H
  37 #define __CONFIG_H
  38
  39 /*
  40  * High Level Configuration Options
  41  * (easy to change)
  42  */
  43
  44 #define CONFIG_MPC824X          1
  45 #define CONFIG_MPC8245          1
  46 #define CONFIG_BMW              1
  47
  48 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  49
  50 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()                    */
  51
  52 #define CONFIG_BCM570x          1       /* Use Broadcom BCM570x Ethernet Driver */
  53 #define CONFIG_TIGON3           1
  54
  55 #define CONFIG_CONS_INDEX       1
  56 #define CONFIG_BAUDRATE         9600
  57 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  58
  59 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz       */
  60
  61 #define CONFIG_BOOTCOMMAND      "bootm FF820000"        /* autoboot command     */
  62 #define CONFIG_BOOTDELAY        5
  63
  64 #define CONFIG_SYS_MAX_DOC_DEVICE      1 /* Only use Onboard TSOP-16MB device */
  65 #define DOC_PASSIVE_PROBE       1
  66 #define CONFIG_SYS_DOC_SUPPORT_2000    1
  67 #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM 1
  68 #define CONFIG_SYS_DOC_SHORT_TIMEOUT    1
  69
  70
  71 /*
  72  * BOOTP options
  73  */
  74 #define CONFIG_BOOTP_BOOTFILESIZE
  75 #define CONFIG_BOOTP_BOOTPATH
  76 #define CONFIG_BOOTP_GATEWAY
  77 #define CONFIG_BOOTP_HOSTNAME
  78
  79
  80 /*
  81  * Command line configuration.
  82  */
  83 #include <config_cmd_default.h>
  84
  85 #define CONFIG_CMD_DATE
  86 #define CONFIG_CMD_ELF
  87
  88
  89 #if 0
  90 #define CONFIG_PCI              1
  91 #define CONFIG_PCI_PNP          1       /* PCI plug-and-play */
  92 #endif
  93
  94 /*
  95  * Miscellaneous configurable options
  96  */
  97 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  98 #define CONFIG_SYS_PROMPT       "=>"            /* Monitor Command Prompt       */
  99 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 100
 101 /* Print Buffer Size
 102  */
 103 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 104
 105 #define CONFIG_SYS_MAXARGS      8               /* Max number of command args   */
 106 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 107 #define CONFIG_SYS_LOAD_ADDR    0x00100000      /* Default load address         */
 108
 109 /*-----------------------------------------------------------------------
 110  * Start addresses for the final memory configuration
 111  * (Set up by the startup code)
 112  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 113  */
 114 #define CONFIG_SYS_SDRAM_BASE       0x00000000
 115
 116 #define CONFIG_SYS_FLASH_BASE0_PRELIM      0xFFF00000      /* FLASH bank on RCS#0 */
 117 #define CONFIG_SYS_FLASH_BASE1_PRELIM      0xFF800000      /* FLASH bank on RCS#1 */
 118 #define CONFIG_SYS_FLASH_BASE  CONFIG_SYS_MONITOR_BASE
 119 #define CONFIG_SYS_FLASH_BANKS          { CONFIG_SYS_FLASH_BASE0_PRELIM , CONFIG_SYS_FLASH_BASE1_PRELIM }
 120
 121 /* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
 122  * reset vector is actually located at FFB00100, but the 8245
 123  * takes care of us.
 124  */
 125 #define CONFIG_SYS_RESET_ADDRESS   0xFFF00100
 126
 127 #define CONFIG_SYS_EUMB_ADDR        0xFC000000
 128
 129 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 130
 131 #define CONFIG_SYS_MONITOR_LEN      (256 << 10) /* Reserve 256 kB for Monitor   */
 132 #define CONFIG_SYS_MALLOC_LEN       (2048 << 10) /* Reserve 2MB for malloc()    */
 133
 134 #define CONFIG_SYS_MEMTEST_START   0x00004000   /* memtest works on             */
 135 #define CONFIG_SYS_MEMTEST_END      0x04000000  /* 0 ... 32 MB in DRAM          */
 136
 137         /* Maximum amount of RAM.
 138          */
 139 #define CONFIG_SYS_MAX_RAM_SIZE    0x04000000   /* 0 .. 64 MB of (S)DRAM */
 140
 141
 142 #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
 143 #undef CONFIG_SYS_RAMBOOT
 144 #else
 145 #define CONFIG_SYS_RAMBOOT
 146 #endif
 147
 148
 149 /*-----------------------------------------------------------------------
 150  * Definitions for initial stack pointer and data area
 151  */
 152 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
 153 #define CONFIG_SYS_INIT_RAM_SIZE   0x2F00  /* Size of used area in DPRAM  */
 154 #define CONFIG_SYS_GBL_DATA_OFFSET  (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 155 #define CONFIG_SYS_INIT_SP_OFFSET  CONFIG_SYS_GBL_DATA_OFFSET
 156
 157 /*
 158  * Low Level Configuration Settings
 159  * (address mappings, register initial values, etc.)
 160  * You should know what you are doing if you make changes here.
 161  * For the detail description refer to the MPC8240 user's manual.
 162  */
 163
 164 #define CONFIG_SYS_CLK_FREQ  33000000   /* external frequency to pll */
 165 #define CONFIG_SYS_HZ                1000
 166
 167 #define CONFIG_SYS_ETH_DEV_FN        0x7800
 168 #define CONFIG_SYS_ETH_IOBASE        0x00104000
 169
 170         /* Bit-field values for MCCR1.
 171          */
 172 #define CONFIG_SYS_ROMNAL           0xf
 173 #define CONFIG_SYS_ROMFAL           0x1f
 174 #define CONFIG_SYS_DBUS_SIZE       0x3
 175
 176         /* Bit-field values for MCCR2.
 177          */
 178 #define CONFIG_SYS_TSWAIT           0x5             /* Transaction Start Wait States timer */
 179 #define CONFIG_SYS_REFINT           0x400           /* Refresh interval FIXME: was 0t430                */
 180
 181         /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
 182          */
 183 #define CONFIG_SYS_BSTOPRE          0           /* FIXME: was 192 */
 184
 185         /* Bit-field values for MCCR3.
 186          */
 187 #define CONFIG_SYS_REFREC           2       /* Refresh to activate interval */
 188
 189         /* Bit-field values for MCCR4.
 190          */
 191 #define CONFIG_SYS_PRETOACT         2       /* Precharge to activate interval FIXME: was 2      */
 192 #define CONFIG_SYS_ACTTOPRE         5       /* Activate to Precharge interval FIXME: was 5      */
 193 #define CONFIG_SYS_SDMODE_CAS_LAT  3        /* SDMODE CAS latancy */
 194 #define CONFIG_SYS_SDMODE_WRAP      0       /* SDMODE wrap type */
 195 #define CONFIG_SYS_SDMODE_BURSTLEN 3        /* SDMODE Burst length */
 196 #define CONFIG_SYS_ACTORW           0xa         /* FIXME was 2 */
 197 #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
 198
 199 #define CONFIG_SYS_PGMAX           0x0 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
 200
 201 #define CONFIG_SYS_SDRAM_DSCD   0x20    /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
 202
 203 /* Memory bank settings.
 204  * Only bits 20-29 are actually used from these vales to set the
 205  * start/end addresses. The upper two bits will always be 0, and the lower
 206  * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
 207  * address. Refer to the MPC8240 book.
 208  */
 209
 210 #define CONFIG_SYS_BANK0_START      0x00000000
 211 #define CONFIG_SYS_BANK0_END        (CONFIG_SYS_MAX_RAM_SIZE - 1)
 212 #define CONFIG_SYS_BANK0_ENABLE    1
 213 #define CONFIG_SYS_BANK1_START      0x3ff00000
 214 #define CONFIG_SYS_BANK1_END        0x3fffffff
 215 #define CONFIG_SYS_BANK1_ENABLE    0
 216 #define CONFIG_SYS_BANK2_START      0x3ff00000
 217 #define CONFIG_SYS_BANK2_END        0x3fffffff
 218 #define CONFIG_SYS_BANK2_ENABLE    0
 219 #define CONFIG_SYS_BANK3_START      0x3ff00000
 220 #define CONFIG_SYS_BANK3_END        0x3fffffff
 221 #define CONFIG_SYS_BANK3_ENABLE    0
 222 #define CONFIG_SYS_BANK4_START      0x3ff00000
 223 #define CONFIG_SYS_BANK4_END        0x3fffffff
 224 #define CONFIG_SYS_BANK4_ENABLE    0
 225 #define CONFIG_SYS_BANK5_START      0x3ff00000
 226 #define CONFIG_SYS_BANK5_END        0x3fffffff
 227 #define CONFIG_SYS_BANK5_ENABLE    0
 228 #define CONFIG_SYS_BANK6_START      0x3ff00000
 229 #define CONFIG_SYS_BANK6_END        0x3fffffff
 230 #define CONFIG_SYS_BANK6_ENABLE    0
 231 #define CONFIG_SYS_BANK7_START      0x3ff00000
 232 #define CONFIG_SYS_BANK7_END        0x3fffffff
 233 #define CONFIG_SYS_BANK7_ENABLE    0
 234
 235 #define CONFIG_SYS_ODCR     0xff
 236
 237 #define CONFIG_PCI              1 /* Include PCI support */
 238 #undef CONFIG_PCI_PNP
 239
 240 /* PCI Memory space(s) */
 241 #define PCI_MEM_SPACE1_START    0x80000000
 242 #define PCI_MEM_SPACE2_START    0xfd000000
 243
 244 /* ROM Spaces */
 245 #include "../board/bmw/bmw.h"
 246
 247 /* BAT configuration */
 248 #define CONFIG_SYS_IBAT0L  (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 249 #define CONFIG_SYS_IBAT0U  (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 250
 251 #define CONFIG_SYS_IBAT1L  (0x70000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 252 #define CONFIG_SYS_IBAT1U  (0x70000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 253
 254 #define CONFIG_SYS_IBAT2L  (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 255 #define CONFIG_SYS_IBAT2U  (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 256
 257 #define CONFIG_SYS_IBAT3L  (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 258 #define CONFIG_SYS_IBAT3U  (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 259
 260 #define CONFIG_SYS_DBAT0L  CONFIG_SYS_IBAT0L
 261 #define CONFIG_SYS_DBAT0U  CONFIG_SYS_IBAT0U
 262 #define CONFIG_SYS_DBAT1L  CONFIG_SYS_IBAT1L
 263 #define CONFIG_SYS_DBAT1U  CONFIG_SYS_IBAT1U
 264 #define CONFIG_SYS_DBAT2L  CONFIG_SYS_IBAT2L
 265 #define CONFIG_SYS_DBAT2U  CONFIG_SYS_IBAT2U
 266 #define CONFIG_SYS_DBAT3L  CONFIG_SYS_IBAT3L
 267 #define CONFIG_SYS_DBAT3U  CONFIG_SYS_IBAT3U
 268
 269 /*
 270  * For booting Linux, the board info and command line data
 271  * have to be in the first 8 MB of memory, since this is
 272  * the maximum mapped by the Linux kernel during initialization.
 273  */
 274 #define CONFIG_SYS_BOOTMAPSZ        (8 << 20)   /* Initial Memory map for Linux */
 275
 276 /*
 277  * FLASH organization
 278  */
 279 #define CONFIG_SYS_MAX_FLASH_BANKS      0       /* Max number of flash banks        */
 280 #define CONFIG_SYS_MAX_FLASH_SECT       64      /* Max number of sectors per  flash */
 281
 282 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms) */
 283 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms) */
 284
 285 /*
 286  * Warining: environment is not EMBEDDED in the U-Boot code.
 287  * It's stored in flash separately.
 288  */
 289 #define CONFIG_ENV_IS_IN_NVRAM      1
 290 #define CONFIG_ENV_OVERWRITE     1
 291 #define CONFIG_SYS_NVRAM_ACCESS_ROUTINE 1
 292 #define CONFIG_ENV_ADDR         0x7c004000 /* right at the start of NVRAM  */
 293 #define CONFIG_ENV_SIZE         0x1ff0  /* Size of the Environment - 8K    */
 294 #define CONFIG_ENV_OFFSET               0       /* starting right at the beginning */
 295
 296 /*
 297  * Cache Configuration
 298  */
 299 #define CONFIG_SYS_CACHELINE_SIZE       32
 300 #if defined(CONFIG_CMD_KGDB)
 301 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value   */
 302 #endif
 303
 304 #endif  /* __CONFIG_H */