include/configs/BSC9131RDB.h

   1 /*
   2  * Copyright 2011-2012 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * BSC9131 RDB board configuration file
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #ifdef CONFIG_BSC9131RDB
  31 #define CONFIG_BSC9131
  32 #define CONFIG_NAND_FSL_IFC
  33 #endif
  34
  35 #ifdef CONFIG_SPIFLASH
  36 #define CONFIG_RAMBOOT_SPIFLASH
  37 #define CONFIG_SYS_RAMBOOT
  38 #define CONFIG_SYS_EXTRA_ENV_RELOC
  39 #define CONFIG_SYS_TEXT_BASE            0x11000000
  40 #define CONFIG_RESET_VECTOR_ADDRESS     0x1107fffc
  41 #endif
  42
  43 #ifdef CONFIG_NAND
  44 #define CONFIG_SPL
  45 #define CONFIG_SPL_INIT_MINIMAL
  46 #define CONFIG_SPL_SERIAL_SUPPORT
  47 #define CONFIG_SPL_NAND_SUPPORT
  48 #define CONFIG_SPL_NAND_MINIMAL
  49 #define CONFIG_SPL_FLUSH_IMAGE
  50 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  51
  52 #define CONFIG_SYS_TEXT_BASE            0x00201000
  53 #define CONFIG_SPL_TEXT_BASE            0xFFFFE000
  54 #define CONFIG_SPL_MAX_SIZE             8192
  55 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
  56 #define CONFIG_SPL_RELOC_STACK          0x00100000
  57 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((512 << 10) - 0x2000)
  58 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
  59 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  60 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
  61 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  62 #endif
  63
  64 #ifdef CONFIG_SPL_BUILD
  65 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  66 #else
  67 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  68 #endif
  69
  70
  71 /* High Level Configuration Options */
  72 #define CONFIG_BOOKE                    /* BOOKE */
  73 #define CONFIG_E500                     /* BOOKE e500 family */
  74 #define CONFIG_MPC85xx          /* MPC8540/60/55/41/48/P1020/P2020/P1010,etc*/
  75 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  76
  77 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
  78 #define CONFIG_TSEC_ENET
  79 #define CONFIG_ENV_OVERWRITE
  80
  81 #define CONFIG_DDR_CLK_FREQ     66666666 /* DDRCLK on 9131 RDB */
  82 #if defined(CONFIG_SYS_CLK_100)
  83 #define CONFIG_SYS_CLK_FREQ    100000000 /* SYSCLK for 9131 RDB */
  84 #else
  85 #define CONFIG_SYS_CLK_FREQ     66666666 /* SYSCLK for 9131 RDB */
  86 #endif
  87
  88 #define CONFIG_HWCONFIG
  89 /*
  90  * These can be toggled for performance analysis, otherwise use default.
  91  */
  92 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
  93 #define CONFIG_BTB                      /* enable branch predition */
  94
  95 #define CONFIG_SYS_MEMTEST_START        0x01000000      /* memtest works on */
  96 #define CONFIG_SYS_MEMTEST_END          0x01ffffff
  97
  98 /* DDR Setup */
  99 #define CONFIG_FSL_DDR3
 100 #undef CONFIG_SYS_DDR_RAW_TIMING
 101 #undef CONFIG_DDR_SPD
 102 #define CONFIG_SYS_SPD_BUS_NUM          0
 103 #define SPD_EEPROM_ADDRESS              0x52 /* I2C access */
 104
 105 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 106
 107 #ifndef __ASSEMBLY__
 108 extern unsigned long get_sdram_size(void);
 109 #endif
 110 #define CONFIG_SYS_SDRAM_SIZE           get_sdram_size() /* DDR size */
 111 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 112 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 113
 114 #define CONFIG_NUM_DDR_CONTROLLERS      1
 115 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 116 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 117
 118 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003f
 119 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014302
 120 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 121
 122 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 123 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 124 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 125 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 126
 127 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 128 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 129 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 130 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 131 #define CONFIG_SYS_DDR_CONTROL          0xC70C0000      /* Type = DDR3  */
 132 #define CONFIG_SYS_DDR_CONTROL_2        0x24401000
 133 #define CONFIG_SYS_DDR_TIMING_4         0x00000001
 134 #define CONFIG_SYS_DDR_TIMING_5         0x02401400
 135
 136 #define CONFIG_SYS_DDR_TIMING_3_800             0x00030000
 137 #define CONFIG_SYS_DDR_TIMING_0_800             0x00110104
 138 #define CONFIG_SYS_DDR_TIMING_1_800             0x6f6b8644
 139 #define CONFIG_SYS_DDR_TIMING_2_800             0x0fa888cf
 140 #define CONFIG_SYS_DDR_CLK_CTRL_800             0x03000000
 141 #define CONFIG_SYS_DDR_MODE_1_800               0x00441420
 142 #define CONFIG_SYS_DDR_MODE_2_800               0x8000c000
 143 #define CONFIG_SYS_DDR_INTERVAL_800             0x0c300100
 144 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800        0x8675f608
 145
 146 /*
 147  * Base addresses -- Note these are effective addresses where the
 148  * actual resources get mapped (not physical addresses)
 149  */
 150 /* relocated CCSRBAR */
 151 #define CONFIG_SYS_CCSRBAR      CONFIG_SYS_CCSRBAR_DEFAULT
 152 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR_DEFAULT
 153
 154 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR      /* PQII uses */
 155                                                         /* CONFIG_SYS_IMMR */
 156 /* DSP CCSRBAR */
 157 #define CONFIG_SYS_FSL_DSP_CCSRBAR      CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
 158 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
 159
 160 /*
 161  * Memory map
 162  *
 163  * 0x0000_0000  0x3FFF_FFFF     DDR                     1G cacheable
 164  * 0x8800_0000  0x8810_0000     IFC internal SRAM               1M
 165  * 0xB000_0000  0xB0FF_FFFF     DSP core M2 memory      16M
 166  * 0xC100_0000  0xC13F_FFFF     MAPLE-2F                4M
 167  * 0xC1F0_0000  0xC1F3_FFFF     PA L2 SRAM Region 0     256K
 168  * 0xC1F8_0000  0xC1F9_FFFF     PA L2 SRAM Region 1     128K
 169  * 0xFED0_0000  0xFED0_3FFF     SEC Secured RAM         16K
 170  * 0xFF60_0000  0xFF6F_FFFF     DSP CCSR                1M
 171  * 0xFF70_0000  0xFF7F_FFFF     PA CCSR                 1M
 172  * 0xFF80_0000  0xFFFF_FFFF     Boot Page & NAND flash buffer   8M
 173  *
 174  */
 175
 176 /*
 177  * IFC Definitions
 178  */
 179 #define CONFIG_SYS_NO_FLASH
 180
 181 /* NAND Flash on IFC */
 182 #define CONFIG_SYS_NAND_BASE            0xff800000
 183 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 184
 185 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 186                                 | CSPR_PORT_SIZE_8      /* Port Size = 8 bit*/ \
 187                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 188                                 | CSPR_V)
 189 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 190
 191 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 192                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 193                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 194                                 | CSOR_NAND_RAL_2       /* RAL = 2Byes */ \
 195                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 196                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 197                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 198
 199 /* NAND Flash Timing Params */
 200 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x08)  \
 201                                         | FTIM0_NAND_TWP(0x06)   \
 202                                         | FTIM0_NAND_TWCHT(0x03) \
 203                                         | FTIM0_NAND_TWH(0x04))
 204 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x18) \
 205                                         | FTIM1_NAND_TWBE(0x23) \
 206                                         | FTIM1_NAND_TRR(0x08)  \
 207                                         | FTIM1_NAND_TRP(0x05))
 208 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x08)  \
 209                                         | FTIM2_NAND_TREH(0x04) \
 210                                         | FTIM2_NAND_TWHRE(0x3f))
 211 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x22)
 212
 213 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 214 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 215 #define CONFIG_MTD_NAND_VERIFY_WRITE
 216 #define CONFIG_CMD_NAND
 217 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 218
 219 #define CONFIG_SYS_NAND_DDR_LAW         11
 220
 221 /* Set up IFC registers for boot location NAND */
 222 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 223 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 224 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 225 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 226 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 227 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 228 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 229
 230 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
 231
 232 #define CONFIG_SYS_INIT_RAM_LOCK
 233 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* stack in RAM */
 234 #define CONFIG_SYS_INIT_RAM_END         0x00004000/* End of used area in RAM */
 235
 236 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END \
 237                                                 - GENERATED_GBL_DATA_SIZE)
 238 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 239
 240 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon*/
 241 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
 242
 243 /* Serial Port */
 244 #define CONFIG_CONS_INDEX       1
 245 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 246 #define CONFIG_SYS_NS16550
 247 #define CONFIG_SYS_NS16550_SERIAL
 248 #define CONFIG_SYS_NS16550_REG_SIZE     1
 249 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 250 #ifdef CONFIG_SPL_BUILD
 251 #define CONFIG_NS16550_MIN_FUNCTIONS
 252 #endif
 253
 254 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 255
 256 #define CONFIG_SYS_BAUDRATE_TABLE       \
 257         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 258
 259 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 260
 261 /* Use the HUSH parser */
 262 #define CONFIG_SYS_HUSH_PARSER
 263 #ifdef  CONFIG_SYS_HUSH_PARSER
 264 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 265 #endif
 266
 267 /*
 268  * Pass open firmware flat tree
 269  */
 270 #define CONFIG_OF_LIBFDT
 271 #define CONFIG_OF_BOARD_SETUP
 272 #define CONFIG_OF_STDOUT_VIA_ALIAS
 273
 274 /* new uImage format support */
 275 #define CONFIG_FIT
 276 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
 277
 278 #define CONFIG_SYS_I2C
 279 #define CONFIG_SYS_I2C_FSL
 280 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 281 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 282 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 283
 284 /* I2C EEPROM */
 285 #define CONFIG_CMD_EEPROM
 286 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 287 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 288 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 289 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 290
 291 #define CONFIG_CMD_I2C
 292
 293
 294 #define CONFIG_FSL_ESPI
 295 /* eSPI - Enhanced SPI */
 296 #ifdef CONFIG_FSL_ESPI
 297 #define CONFIG_SPI_FLASH
 298 #define CONFIG_SPI_FLASH_SPANSION
 299 #define CONFIG_CMD_SF
 300 #define CONFIG_SF_DEFAULT_SPEED         10000000
 301 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 302 #endif
 303
 304 #if defined(CONFIG_TSEC_ENET)
 305
 306 #define CONFIG_MII                      /* MII PHY management */
 307 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 308 #define CONFIG_TSEC1    1
 309 #define CONFIG_TSEC1_NAME       "eTSEC1"
 310 #define CONFIG_TSEC2    1
 311 #define CONFIG_TSEC2_NAME       "eTSEC2"
 312
 313 #define TSEC1_PHY_ADDR          0
 314 #define TSEC2_PHY_ADDR          3
 315
 316 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 317 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 318
 319 #define TSEC1_PHYIDX            0
 320
 321 #define TSEC2_PHYIDX            0
 322
 323 #define CONFIG_ETHPRIME         "eTSEC1"
 324
 325 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 326
 327 #endif  /* CONFIG_TSEC_ENET */
 328
 329 /*
 330  * Environment
 331  */
 332 #if defined(CONFIG_RAMBOOT_SPIFLASH)
 333 #define CONFIG_ENV_IS_IN_SPI_FLASH
 334 #define CONFIG_ENV_SPI_BUS      0
 335 #define CONFIG_ENV_SPI_CS       0
 336 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 337 #define CONFIG_ENV_SPI_MODE     0
 338 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 339 #define CONFIG_ENV_SECT_SIZE    0x10000
 340 #define CONFIG_ENV_SIZE         0x2000
 341 #elif defined(CONFIG_NAND)
 342 #define CONFIG_ENV_IS_IN_NAND
 343 #define CONFIG_SYS_EXTRA_ENV_RELOC
 344 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 345 #define CONFIG_ENV_OFFSET       ((512 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 346 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
 347 #elif defined(CONFIG_SYS_RAMBOOT)
 348 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 349 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 350 #define CONFIG_ENV_SIZE         0x2000
 351 #endif
 352
 353 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 354 #define CONFIG_SYS_LOADS_BAUD_CHANGE            /* allow baudrate change */
 355
 356 /*
 357  * Command line configuration.
 358  */
 359 #include <config_cmd_default.h>
 360
 361 #define CONFIG_CMD_DHCP
 362 #define CONFIG_CMD_ERRATA
 363 #define CONFIG_CMD_ELF
 364 #define CONFIG_CMD_EXT2
 365 #define CONFIG_CMD_FAT
 366 #define CONFIG_CMD_IRQ
 367 #define CONFIG_CMD_MII
 368 #define CONFIG_DOS_PARTITION
 369 #define CONFIG_CMD_PING
 370 #define CONFIG_CMD_REGINFO
 371 #define CONFIG_CMD_SETEXPR
 372
 373 /*
 374  * Miscellaneous configurable options
 375  */
 376 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 377 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 378 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 379 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 380 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 381
 382 #if defined(CONFIG_CMD_KGDB)
 383 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 384 #else
 385 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 386 #endif
 387 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 388                                                 /* Print Buffer Size */
 389 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 390 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 391 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 392
 393 /*
 394  * For booting Linux, the board info and command line data
 395  * have to be in the first 64 MB of memory, since this is
 396  * the maximum mapped by the Linux kernel during initialization.
 397  */
 398 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 399 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 400
 401 #if defined(CONFIG_CMD_KGDB)
 402 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 403 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 404 #endif
 405
 406 #define CONFIG_USB_EHCI
 407
 408 #ifdef CONFIG_USB_EHCI
 409 #define CONFIG_CMD_USB
 410 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 411 #define CONFIG_USB_EHCI_FSL
 412 #define CONFIG_USB_STORAGE
 413 #define CONFIG_HAS_FSL_DR_USB
 414 #endif
 415
 416 /*
 417  * Environment Configuration
 418  */
 419
 420 #if defined(CONFIG_TSEC_ENET)
 421 #define CONFIG_HAS_ETH0
 422 #endif
 423
 424 #define CONFIG_HOSTNAME         BSC9131rdb
 425 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 426 #define CONFIG_BOOTFILE         "uImage"
 427 #define CONFIG_UBOOTPATH        "u-boot.bin" /* U-Boot image on TFTP server */
 428
 429 #define CONFIG_BAUDRATE         115200
 430
 431 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 432         "netdev=eth0\0"                                         \
 433         "uboot=" CONFIG_UBOOTPATH "\0"                          \
 434         "loadaddr=1000000\0"                    \
 435         "bootfile=uImage\0"     \
 436         "consoledev=ttyS0\0"                            \
 437         "ramdiskaddr=2000000\0"                 \
 438         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 439         "fdtaddr=c00000\0"                              \
 440         "fdtfile=bsc9131rdb.dtb\0"              \
 441         "bdev=sda1\0"   \
 442         "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"    \
 443         "bootm_size=0x37000000\0"       \
 444         "othbootargs=ramdisk_size=600000 " \
 445         "default_hugepagesz=256m hugepagesz=256m hugepages=1\0" \
 446         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 447         "console=$consoledev,$baudrate $othbootargs; "  \
 448         "usb start;"                    \
 449         "ext2load usb 0:4 $loadaddr $bootfile;"         \
 450         "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 451         "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 452         "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 453
 454 #define CONFIG_RAMBOOTCOMMAND           \
 455         "setenv bootargs root=/dev/ram rw "     \
 456         "console=$consoledev,$baudrate $othbootargs; "  \
 457         "tftp $ramdiskaddr $ramdiskfile;"       \
 458         "tftp $loadaddr $bootfile;"             \
 459         "tftp $fdtaddr $fdtfile;"               \
 460         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 461
 462 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 463
 464 #endif  /* __CONFIG_H */