include/configs/BSC9132QDS.h

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 /*
   8  * BSC9132 QDS board configuration file
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 #define CONFIG_DISPLAY_BOARDINFO
  15
  16 #ifdef CONFIG_BSC9132QDS
  17 #define CONFIG_BSC9132
  18 #endif
  19
  20 #define CONFIG_MISC_INIT_R
  21
  22 #ifdef CONFIG_SDCARD
  23 #define CONFIG_RAMBOOT_SDCARD
  24 #define CONFIG_SYS_RAMBOOT
  25 #define CONFIG_SYS_EXTRA_ENV_RELOC
  26 #define CONFIG_SYS_TEXT_BASE            0x11000000
  27 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  28 #endif
  29 #define CONFIG_SYS_FSL_ERRATUM_IFC_A002769      1
  30 #ifdef CONFIG_SPIFLASH
  31 #define CONFIG_RAMBOOT_SPIFLASH
  32 #define CONFIG_SYS_RAMBOOT
  33 #define CONFIG_SYS_EXTRA_ENV_RELOC
  34 #define CONFIG_SYS_TEXT_BASE            0x11000000
  35 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  36 #endif
  37 #ifdef CONFIG_NAND_SECBOOT
  38 #define CONFIG_RAMBOOT_NAND
  39 #define CONFIG_SYS_RAMBOOT
  40 #define CONFIG_SYS_EXTRA_ENV_RELOC
  41 #define CONFIG_SYS_TEXT_BASE            0x11000000
  42 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  43 #endif
  44
  45 #ifdef CONFIG_NAND
  46 #define CONFIG_SPL_INIT_MINIMAL
  47 #define CONFIG_SPL_NAND_BOOT
  48 #define CONFIG_SPL_FLUSH_IMAGE
  49 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
  50
  51 #define CONFIG_SYS_TEXT_BASE            0x00201000
  52 #define CONFIG_SPL_TEXT_BASE            0xFFFFE000
  53 #define CONFIG_SPL_MAX_SIZE             8192
  54 #define CONFIG_SPL_RELOC_TEXT_BASE      0x00100000
  55 #define CONFIG_SPL_RELOC_STACK          0x00100000
  56 #define CONFIG_SYS_NAND_U_BOOT_SIZE     ((768 << 10) - 0x2000)
  57 #define CONFIG_SYS_NAND_U_BOOT_DST      (0x00200000 - CONFIG_SPL_MAX_SIZE)
  58 #define CONFIG_SYS_NAND_U_BOOT_START    0x00200000
  59 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0
  60 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
  61 #endif
  62
  63 #ifndef CONFIG_SYS_TEXT_BASE
  64 #define CONFIG_SYS_TEXT_BASE            0x8ff40000
  65 #endif
  66
  67 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  68 #define CONFIG_RESET_VECTOR_ADDRESS     0x8ffffffc
  69 #endif
  70
  71 #ifdef CONFIG_SPL_BUILD
  72 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
  73 #else
  74 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  75 #endif
  76
  77 /* High Level Configuration Options */
  78 #define CONFIG_BOOKE                    /* BOOKE */
  79 #define CONFIG_E500                     /* BOOKE e500 family */
  80 #define CONFIG_FSL_IFC                  /* Enable IFC Support */
  81 #define CONFIG_FSL_CAAM                 /* Enable SEC/CAAM */
  82 #define CONFIG_SYS_HAS_SERDES           /* common SERDES init code */
  83
  84 #define CONFIG_PCI                      /* Enable PCI/PCIE */
  85 #if defined(CONFIG_PCI)
  86 #define CONFIG_PCIE1                    /* PCIE controller 1 (slot 1) */
  87 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  88 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
  89 #define CONFIG_FSL_PCIE_RESET           /* need PCIe reset errata */
  90 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  91
  92 #define CONFIG_CMD_PCI
  93
  94 /*
  95  * PCI Windows
  96  * Memory space is mapped 1-1, but I/O space must start from 0.
  97  */
  98 /* controller 1, Slot 1, tgtid 1, Base address a000 */
  99 #define CONFIG_SYS_PCIE1_NAME           "PCIe Slot"
 100 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x90000000
 101 #define CONFIG_SYS_PCIE1_MEM_BUS        0x90000000
 102 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x90000000
 103 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000      /* 256M */
 104 #define CONFIG_SYS_PCIE1_IO_VIRT        0xC0010000
 105 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 106 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 107 #define CONFIG_SYS_PCIE1_IO_PHYS        0xC0010000
 108
 109 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 110
 111 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 112 #define CONFIG_DOS_PARTITION
 113 #endif
 114
 115 #define CONFIG_FSL_LAW                  /* Use common FSL init code */
 116 #define CONFIG_ENV_OVERWRITE
 117 #define CONFIG_TSEC_ENET /* ethernet */
 118
 119 #if defined(CONFIG_SYS_CLK_100_DDR_100)
 120 #define CONFIG_SYS_CLK_FREQ     100000000
 121 #define CONFIG_DDR_CLK_FREQ     100000000
 122 #elif defined(CONFIG_SYS_CLK_100_DDR_133)
 123 #define CONFIG_SYS_CLK_FREQ     100000000
 124 #define CONFIG_DDR_CLK_FREQ     133000000
 125 #endif
 126
 127 #define CONFIG_MP
 128
 129 #define CONFIG_HWCONFIG
 130 /*
 131  * These can be toggled for performance analysis, otherwise use default.
 132  */
 133 #define CONFIG_L2_CACHE                 /* toggle L2 cache */
 134 #define CONFIG_BTB                      /* enable branch predition */
 135
 136 #define CONFIG_SYS_MEMTEST_START        0x01000000      /* memtest works on */
 137 #define CONFIG_SYS_MEMTEST_END          0x01ffffff
 138
 139 /* DDR Setup */
 140 #define CONFIG_SYS_FSL_DDR3
 141 #define CONFIG_SYS_SPD_BUS_NUM          0
 142 #define SPD_EEPROM_ADDRESS1             0x54 /* I2C access */
 143 #define SPD_EEPROM_ADDRESS2             0x56 /* I2C access */
 144 #define CONFIG_FSL_DDR_INTERACTIVE
 145
 146 #define CONFIG_MEM_INIT_VALUE           0xDeadBeef
 147
 148 #define CONFIG_SYS_SDRAM_SIZE           (1024)
 149 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 150 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
 151
 152 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
 153
 154 /* DDR3 Controller Settings */
 155 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
 156 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000003F
 157 #define CONFIG_SYS_DDR_CS0_CONFIG_1333  0x80004302
 158 #define CONFIG_SYS_DDR_CS0_CONFIG_800   0x80014302
 159 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
 160 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
 161 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
 162 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
 163 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
 164 #define CONFIG_SYS_DDR1_CS0_BNDS       0x0040007F
 165
 166 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
 167 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
 168 #define CONFIG_SYS_DDR_RCW_1            0x00000000
 169 #define CONFIG_SYS_DDR_RCW_2            0x00000000
 170 #define CONFIG_SYS_DDR_CONTROL_800              0x470C0000
 171 #define CONFIG_SYS_DDR_CONTROL_2_800    0x04401050
 172 #define CONFIG_SYS_DDR_TIMING_4_800             0x00220001
 173 #define CONFIG_SYS_DDR_TIMING_5_800             0x03402400
 174
 175 #define CONFIG_SYS_DDR_CONTROL_1333             0x470C0008
 176 #define CONFIG_SYS_DDR_CONTROL_2_1333   0x24401010
 177 #define CONFIG_SYS_DDR_TIMING_4_1333            0x00000001
 178 #define CONFIG_SYS_DDR_TIMING_5_1333            0x03401400
 179
 180 #define CONFIG_SYS_DDR_TIMING_3_800             0x00020000
 181 #define CONFIG_SYS_DDR_TIMING_0_800             0x00330004
 182 #define CONFIG_SYS_DDR_TIMING_1_800             0x6f6B4846
 183 #define CONFIG_SYS_DDR_TIMING_2_800             0x0FA8C8CF
 184 #define CONFIG_SYS_DDR_CLK_CTRL_800             0x03000000
 185 #define CONFIG_SYS_DDR_MODE_1_800               0x40461520
 186 #define CONFIG_SYS_DDR_MODE_2_800               0x8000c000
 187 #define CONFIG_SYS_DDR_INTERVAL_800             0x0C300000
 188 #define CONFIG_SYS_DDR_WRLVL_CONTROL_800        0x8655A608
 189
 190 #define CONFIG_SYS_DDR_TIMING_3_1333            0x01061000
 191 #define CONFIG_SYS_DDR_TIMING_0_1333            0x00440104
 192 #define CONFIG_SYS_DDR_TIMING_1_1333            0x98913A45
 193 #define CONFIG_SYS_DDR_TIMING_2_1333            0x0FB8B114
 194 #define CONFIG_SYS_DDR_CLK_CTRL_1333            0x02800000
 195 #define CONFIG_SYS_DDR_MODE_1_1333              0x00061A50
 196 #define CONFIG_SYS_DDR_MODE_2_1333              0x00100000
 197 #define CONFIG_SYS_DDR_INTERVAL_1333            0x144E0513
 198 #define CONFIG_SYS_DDR_WRLVL_CONTROL_1333       0x8655F607
 199
 200 /*FIXME: the following params are constant w.r.t diff freq
 201 combinations. this should be removed later
 202 */
 203 #if CONFIG_DDR_CLK_FREQ == 100000000
 204 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
 205 #define CONFIG_SYS_DDR_CONTROL          CONFIG_SYS_DDR_CONTROL_800
 206 #define CONFIG_SYS_DDR_CONTROL_2 CONFIG_SYS_DDR_CONTROL_2_800
 207 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
 208 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
 209 #elif CONFIG_DDR_CLK_FREQ == 133000000
 210 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_1333
 211 #define CONFIG_SYS_DDR_CONTROL          CONFIG_SYS_DDR_CONTROL_1333
 212 #define CONFIG_SYS_DDR_CONTROL_2        CONFIG_SYS_DDR_CONTROL_2_1333
 213 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_1333
 214 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_1333
 215 #else
 216 #define CONFIG_SYS_DDR_CS0_CONFIG CONFIG_SYS_DDR_CS0_CONFIG_800
 217 #define CONFIG_SYS_DDR_CONTROL          CONFIG_SYS_DDR_CONTROL_800
 218 #define CONFIG_SYS_DDR_CONTROL_2        CONFIG_SYS_DDR_CONTROL_2_800
 219 #define CONFIG_SYS_DDR_TIMING_4 CONFIG_SYS_DDR_TIMING_4_800
 220 #define CONFIG_SYS_DDR_TIMING_5 CONFIG_SYS_DDR_TIMING_5_800
 221 #endif
 222
 223 /* relocated CCSRBAR */
 224 #define CONFIG_SYS_CCSRBAR      CONFIG_SYS_CCSRBAR_DEFAULT
 225 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR_DEFAULT
 226
 227 #define CONFIG_SYS_IMMR         CONFIG_SYS_CCSRBAR
 228
 229 /* DSP CCSRBAR */
 230 #define CONFIG_SYS_FSL_DSP_CCSRBAR      CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
 231 #define CONFIG_SYS_FSL_DSP_CCSRBAR_PHYS CONFIG_SYS_FSL_DSP_CCSRBAR_DEFAULT
 232
 233 /*
 234  * IFC Definitions
 235  */
 236 /* NOR Flash on IFC */
 237
 238 #ifdef CONFIG_SPL_BUILD
 239 #define CONFIG_SYS_NO_FLASH
 240 #endif
 241 #define CONFIG_SYS_FLASH_BASE           0x88000000
 242 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* Max number of sector: 32M */
 243
 244 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 245
 246 #define CONFIG_SYS_NOR_CSPR     0x88000101
 247 #define CONFIG_SYS_NOR_AMASK    IFC_AMASK(128*1024*1024)
 248 #define CONFIG_SYS_NOR_CSOR     CSOR_NOR_ADM_SHIFT(5)
 249 /* NOR Flash Timing Params */
 250
 251 #define CONFIG_SYS_NOR_FTIM0    (FTIM0_NOR_TACSE(0x01) \
 252                                 | FTIM0_NOR_TEADC(0x03) \
 253                                 | FTIM0_NOR_TAVDS(0x00) \
 254                                 | FTIM0_NOR_TEAHC(0x0f))
 255 #define CONFIG_SYS_NOR_FTIM1    (FTIM1_NOR_TACO(0x1d) \
 256                                 | FTIM1_NOR_TRAD_NOR(0x09) \
 257                                 | FTIM1_NOR_TSEQRAD_NOR(0x09))
 258 #define CONFIG_SYS_NOR_FTIM2    (FTIM2_NOR_TCS(0x1) \
 259                                 | FTIM2_NOR_TCH(0x4) \
 260                                 | FTIM2_NOR_TWPH(0x7) \
 261                                 | FTIM2_NOR_TWP(0x1e))
 262 #define CONFIG_SYS_NOR_FTIM3    0x0
 263
 264 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 265 #define CONFIG_SYS_FLASH_QUIET_TEST
 266 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 267 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 268
 269 #undef CONFIG_SYS_FLASH_CHECKSUM
 270 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 271 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 272
 273 /* CFI for NOR Flash */
 274 #define CONFIG_FLASH_CFI_DRIVER
 275 #define CONFIG_SYS_FLASH_CFI
 276 #define CONFIG_SYS_FLASH_EMPTY_INFO
 277 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 278
 279 /* NAND Flash on IFC */
 280 #define CONFIG_SYS_NAND_BASE            0xff800000
 281 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 282
 283 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 284                                 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
 285                                 | CSPR_MSEL_NAND        /* MSEL = NAND */ \
 286                                 | CSPR_V)
 287 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 288
 289 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 290                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 291                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 292                                 | CSOR_NAND_RAL_2       /* RAL = 2Byes */ \
 293                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 294                                 | CSOR_NAND_SPRZ_64/* Spare size = 64 */ \
 295                                 | CSOR_NAND_PB(64))     /*Pages Per Block = 64*/
 296
 297 /* NAND Flash Timing Params */
 298 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x03) \
 299                                         | FTIM0_NAND_TWP(0x05) \
 300                                         | FTIM0_NAND_TWCHT(0x02) \
 301                                         | FTIM0_NAND_TWH(0x04))
 302 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x1c) \
 303                                         | FTIM1_NAND_TWBE(0x1e) \
 304                                         | FTIM1_NAND_TRR(0x07) \
 305                                         | FTIM1_NAND_TRP(0x05))
 306 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0x08) \
 307                                         | FTIM2_NAND_TREH(0x04) \
 308                                         | FTIM2_NAND_TWHRE(0x11))
 309 #define CONFIG_SYS_NAND_FTIM3           FTIM3_NAND_TWW(0x04)
 310
 311 #define CONFIG_SYS_NAND_DDR_LAW         11
 312
 313 /* NAND */
 314 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 315 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 316 #define CONFIG_CMD_NAND
 317
 318 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 319
 320 #ifndef CONFIG_SPL_BUILD
 321 #define CONFIG_FSL_QIXIS
 322 #endif
 323 #ifdef CONFIG_FSL_QIXIS
 324 #define CONFIG_SYS_FPGA_BASE    0xffb00000
 325 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 326 #define QIXIS_BASE      CONFIG_SYS_FPGA_BASE
 327 #define QIXIS_LBMAP_SWITCH      9
 328 #define QIXIS_LBMAP_MASK        0x07
 329 #define QIXIS_LBMAP_SHIFT       0
 330 #define QIXIS_LBMAP_DFLTBANK            0x00
 331 #define QIXIS_LBMAP_ALTBANK             0x04
 332 #define QIXIS_RST_CTL_RESET             0x83
 333 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 334 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 335 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 336
 337 #define CONFIG_SYS_FPGA_BASE_PHYS       CONFIG_SYS_FPGA_BASE
 338
 339 #define CONFIG_SYS_CSPR2                (CSPR_PHYS_ADDR(CONFIG_SYS_FPGA_BASE) \
 340                                         | CSPR_PORT_SIZE_8 \
 341                                         | CSPR_MSEL_GPCM \
 342                                         | CSPR_V)
 343 #define CONFIG_SYS_AMASK2               IFC_AMASK(64*1024)
 344 #define CONFIG_SYS_CSOR2                0x0
 345 /* CPLD Timing parameters for IFC CS3 */
 346 #define CONFIG_SYS_CS2_FTIM0            (FTIM0_GPCM_TACSE(0x0e) | \
 347                                         FTIM0_GPCM_TEADC(0x0e) | \
 348                                         FTIM0_GPCM_TEAHC(0x0e))
 349 #define CONFIG_SYS_CS2_FTIM1            (FTIM1_GPCM_TACO(0x0e) | \
 350                                         FTIM1_GPCM_TRAD(0x1f))
 351 #define CONFIG_SYS_CS2_FTIM2            (FTIM2_GPCM_TCS(0x0e) | \
 352                                         FTIM2_GPCM_TCH(0x8) | \
 353                                         FTIM2_GPCM_TWP(0x1f))
 354 #define CONFIG_SYS_CS2_FTIM3            0x0
 355 #endif
 356
 357 /* Set up IFC registers for boot location NOR/NAND */
 358 #if defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
 359 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NAND_CSPR
 360 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NAND_AMASK
 361 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NAND_CSOR
 362 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NAND_FTIM0
 363 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NAND_FTIM1
 364 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NAND_FTIM2
 365 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NAND_FTIM3
 366 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR_CSPR
 367 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 368 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 369 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 370 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 371 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 372 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 373 #else
 374 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR_CSPR
 375 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 376 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 377 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 378 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 379 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 380 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 381 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NAND_CSPR
 382 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NAND_AMASK
 383 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NAND_CSOR
 384 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NAND_FTIM0
 385 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NAND_FTIM1
 386 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NAND_FTIM2
 387 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NAND_FTIM3
 388 #endif
 389
 390 #define CONFIG_BOARD_EARLY_INIT_F       /* Call board_pre_init */
 391 #define CONFIG_BOARD_EARLY_INIT_R
 392
 393 #define CONFIG_SYS_INIT_RAM_LOCK
 394 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* stack in RAM */
 395 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000 /* End of used area in RAM */
 396
 397 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE \
 398                                                 - GENERATED_GBL_DATA_SIZE)
 399 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 400
 401 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 402 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)   /* Reserved for malloc*/
 403
 404 /* Serial Port */
 405 #define CONFIG_CONS_INDEX       1
 406 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 407 #define CONFIG_SYS_NS16550_SERIAL
 408 #define CONFIG_SYS_NS16550_REG_SIZE     1
 409 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 410 #ifdef CONFIG_SPL_BUILD
 411 #define CONFIG_NS16550_MIN_FUNCTIONS
 412 #endif
 413
 414 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* determine from environment */
 415
 416 #define CONFIG_SYS_BAUDRATE_TABLE       \
 417         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 418
 419 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500)
 420 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600)
 421 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x4700)
 422 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x4800)
 423
 424 #define CONFIG_SYS_I2C
 425 #define CONFIG_SYS_I2C_FSL
 426 #define CONFIG_SYS_FSL_I2C_SPEED        400800 /* I2C speed and slave address*/
 427 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 428 #define CONFIG_SYS_FSL_I2C2_SPEED       400800 /* I2C speed and slave address*/
 429 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 430 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 431 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 432
 433 /* I2C EEPROM */
 434 #define CONFIG_ID_EEPROM
 435 #ifdef CONFIG_ID_EEPROM
 436 #define CONFIG_SYS_I2C_EEPROM_NXID
 437 #endif
 438 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x57
 439 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 440 #define CONFIG_SYS_EEPROM_BUS_NUM       0
 441
 442 /* enable read and write access to EEPROM */
 443 #define CONFIG_CMD_EEPROM
 444 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 445 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 446 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 447
 448 /* I2C FPGA */
 449 #define CONFIG_I2C_FPGA
 450 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 451
 452 #define CONFIG_RTC_DS3231
 453 #define CONFIG_SYS_I2C_RTC_ADDR         0x68
 454
 455 /*
 456  * SPI interface will not be available in case of NAND boot SPI CS0 will be
 457  * used for SLIC
 458  */
 459 /* eSPI - Enhanced SPI */
 460 #ifdef CONFIG_FSL_ESPI
 461 #define CONFIG_SF_DEFAULT_SPEED         10000000
 462 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_0
 463 #endif
 464
 465 #if defined(CONFIG_TSEC_ENET)
 466
 467 #define CONFIG_MII                      /* MII PHY management */
 468 #define CONFIG_MII_DEFAULT_TSEC 1       /* Allow unregistered phys */
 469 #define CONFIG_TSEC1    1
 470 #define CONFIG_TSEC1_NAME       "eTSEC1"
 471 #define CONFIG_TSEC2    1
 472 #define CONFIG_TSEC2_NAME       "eTSEC2"
 473
 474 #define TSEC1_PHY_ADDR          0
 475 #define TSEC2_PHY_ADDR          1
 476
 477 #define TSEC1_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 478 #define TSEC2_FLAGS             (TSEC_GIGABIT | TSEC_REDUCED)
 479
 480 #define TSEC1_PHYIDX            0
 481 #define TSEC2_PHYIDX            0
 482
 483 #define CONFIG_ETHPRIME         "eTSEC1"
 484
 485 #define CONFIG_PHY_GIGE         /* Include GbE speed/duplex detection */
 486
 487 /* TBI PHY configuration for SGMII mode */
 488 #define CONFIG_TSEC_TBICR_SETTINGS ( \
 489                 TBICR_PHY_RESET \
 490                 | TBICR_ANEG_ENABLE \
 491                 | TBICR_FULL_DUPLEX \
 492                 | TBICR_SPEED1_SET \
 493                 )
 494
 495 #endif  /* CONFIG_TSEC_ENET */
 496
 497 #define CONFIG_MMC
 498 #ifdef CONFIG_MMC
 499 #define CONFIG_DOS_PARTITION
 500 #define CONFIG_FSL_ESDHC
 501 #define CONFIG_GENERIC_MMC
 502 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 503 #endif
 504
 505 #define CONFIG_USB_EHCI  /* USB */
 506 #ifdef CONFIG_USB_EHCI
 507 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 508 #define CONFIG_USB_EHCI_FSL
 509 #define CONFIG_HAS_FSL_DR_USB
 510 #endif
 511
 512 /*
 513  * Environment
 514  */
 515 #if defined(CONFIG_RAMBOOT_SDCARD)
 516 #define CONFIG_ENV_IS_IN_MMC
 517 #define CONFIG_FSL_FIXED_MMC_LOCATION
 518 #define CONFIG_SYS_MMC_ENV_DEV          0
 519 #define CONFIG_ENV_SIZE                 0x2000
 520 #elif defined(CONFIG_RAMBOOT_SPIFLASH)
 521 #define CONFIG_ENV_IS_IN_SPI_FLASH
 522 #define CONFIG_ENV_SPI_BUS      0
 523 #define CONFIG_ENV_SPI_CS       0
 524 #define CONFIG_ENV_SPI_MAX_HZ   10000000
 525 #define CONFIG_ENV_SPI_MODE     0
 526 #define CONFIG_ENV_OFFSET       0x100000        /* 1MB */
 527 #define CONFIG_ENV_SECT_SIZE    0x10000
 528 #define CONFIG_ENV_SIZE         0x2000
 529 #elif defined(CONFIG_NAND) || defined(CONFIG_NAND_SECBOOT)
 530 #define CONFIG_ENV_IS_IN_NAND
 531 #define CONFIG_ENV_SIZE         CONFIG_SYS_NAND_BLOCK_SIZE
 532 #define CONFIG_ENV_OFFSET       ((768 * 1024) + CONFIG_SYS_NAND_BLOCK_SIZE)
 533 #define CONFIG_ENV_RANGE        (3 * CONFIG_ENV_SIZE)
 534 #elif defined(CONFIG_SYS_RAMBOOT)
 535 #define CONFIG_ENV_IS_NOWHERE           /* Store ENV in memory only */
 536 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_MONITOR_BASE - 0x1000)
 537 #define CONFIG_ENV_SIZE                 0x2000
 538 #else
 539 #define CONFIG_ENV_IS_IN_FLASH
 540 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 541 #define CONFIG_ENV_SIZE         0x2000
 542 #define CONFIG_ENV_SECT_SIZE    0x20000
 543 #endif
 544
 545 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 546 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 547
 548 /*
 549  * Command line configuration.
 550  */
 551 #define CONFIG_CMD_DATE
 552 #define CONFIG_CMD_ERRATA
 553 #define CONFIG_CMD_IRQ
 554 #define CONFIG_CMD_REGINFO
 555
 556 #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
 557 #define CONFIG_DOS_PARTITION
 558 #endif
 559
 560 /* Hash command with SHA acceleration supported in hardware */
 561 #ifdef CONFIG_FSL_CAAM
 562 #define CONFIG_CMD_HASH
 563 #define CONFIG_SHA_HW_ACCEL
 564 #endif
 565
 566 /*
 567  * Miscellaneous configurable options
 568  */
 569 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 570 #define CONFIG_CMDLINE_EDITING                  /* Command-line editing */
 571 #define CONFIG_AUTO_COMPLETE                    /* add autocompletion support */
 572 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 573
 574 #if defined(CONFIG_CMD_KGDB)
 575 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size */
 576 #else
 577 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size */
 578 #endif
 579 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 580                                                 /* Print Buffer Size */
 581 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 582 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
 583
 584 /*
 585  * For booting Linux, the board info and command line data
 586  * have to be in the first 64 MB of memory, since this is
 587  * the maximum mapped by the Linux kernel during initialization.
 588  */
 589 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20) /* Initial Memory map for Linux */
 590 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 591
 592 #if defined(CONFIG_CMD_KGDB)
 593 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 594 #endif
 595
 596 /*
 597  * Dynamic MTD Partition support with mtdparts
 598  */
 599 #ifndef CONFIG_SYS_NO_FLASH
 600 #define CONFIG_MTD_DEVICE
 601 #define CONFIG_MTD_PARTITIONS
 602 #define CONFIG_CMD_MTDPARTS
 603 #define CONFIG_FLASH_CFI_MTD
 604 #define MTDIDS_DEFAULT "nor0=88000000.nor,nand0=ff800000.flash,"
 605 #define MTDPARTS_DEFAULT "mtdparts=88000000.nor:256k(dtb),7m(kernel)," \
 606                         "55m(fs),1m(uboot);ff800000.flash:1m(uboot)," \
 607                         "8m(kernel),512k(dtb),-(fs)"
 608 #endif
 609 /*
 610  * Override partitions in device tree using info
 611  * in "mtdparts" environment variable
 612  */
 613 #ifdef CONFIG_CMD_MTDPARTS
 614 #define CONFIG_FDT_FIXUP_PARTITIONS
 615 #endif
 616
 617 /*
 618  * Environment Configuration
 619  */
 620
 621 #if defined(CONFIG_TSEC_ENET)
 622 #define CONFIG_HAS_ETH0
 623 #define CONFIG_HAS_ETH1
 624 #endif
 625
 626 #define CONFIG_HOSTNAME         BSC9132qds
 627 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 628 #define CONFIG_BOOTFILE         "uImage"
 629 #define CONFIG_UBOOTPATH        "u-boot.bin"
 630
 631 #define CONFIG_BAUDRATE         115200
 632
 633 #ifdef CONFIG_SDCARD
 634 #define CONFIG_DEF_HWCONFIG     "hwconfig=usb1:dr_mode=host,phy_type=ulpi\0"
 635 #else
 636 #define CONFIG_DEF_HWCONFIG     "hwconfig=sim;usb1:dr_mode=host,phy_type=ulpi\0"
 637 #endif
 638
 639 #define CONFIG_EXTRA_ENV_SETTINGS                               \
 640         "netdev=eth0\0"                                         \
 641         "uboot=" CONFIG_UBOOTPATH "\0"                          \
 642         "loadaddr=1000000\0"                    \
 643         "bootfile=uImage\0"     \
 644         "consoledev=ttyS0\0"                            \
 645         "ramdiskaddr=2000000\0"                 \
 646         "ramdiskfile=rootfs.ext2.gz.uboot\0"            \
 647         "fdtaddr=1e00000\0"                             \
 648         "fdtfile=bsc9132qds.dtb\0"              \
 649         "bdev=sda1\0"   \
 650         CONFIG_DEF_HWCONFIG\
 651         "othbootargs=mem=880M ramdisk_size=600000 " \
 652                 "default_hugepagesz=256m hugepagesz=256m hugepages=1 " \
 653                 "isolcpus=0\0" \
 654         "usbext2boot=setenv bootargs root=/dev/ram rw " \
 655                 "console=$consoledev,$baudrate $othbootargs; "  \
 656                 "usb start;"                    \
 657                 "ext2load usb 0:4 $loadaddr $bootfile;"         \
 658                 "ext2load usb 0:4 $fdtaddr $fdtfile;"   \
 659                 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;"   \
 660                 "bootm $loadaddr $ramdiskaddr $fdtaddr\0"       \
 661         "debug_halt_off=mw ff7e0e30 0xf0000000;"
 662
 663 #define CONFIG_NFSBOOTCOMMAND   \
 664         "setenv bootargs root=/dev/nfs rw "     \
 665         "nfsroot=$serverip:$rootpath "  \
 666         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 667         "console=$consoledev,$baudrate $othbootargs;" \
 668         "tftp $loadaddr $bootfile;"     \
 669         "tftp $fdtaddr $fdtfile;"       \
 670         "bootm $loadaddr - $fdtaddr"
 671
 672 #define CONFIG_HDBOOT   \
 673         "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
 674         "console=$consoledev,$baudrate $othbootargs;" \
 675         "usb start;"    \
 676         "ext2load usb 0:1 $loadaddr /boot/$bootfile;"   \
 677         "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
 678         "bootm $loadaddr - $fdtaddr"
 679
 680 #define CONFIG_RAMBOOTCOMMAND           \
 681         "setenv bootargs root=/dev/ram rw "     \
 682         "console=$consoledev,$baudrate $othbootargs; "  \
 683         "tftp $ramdiskaddr $ramdiskfile;"       \
 684         "tftp $loadaddr $bootfile;"             \
 685         "tftp $fdtaddr $fdtfile;"               \
 686         "bootm $loadaddr $ramdiskaddr $fdtaddr"
 687
 688 #define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
 689
 690 #include <asm/fsl_secure_boot.h>
 691
 692 #endif  /* __CONFIG_H */