include/configs/CCM.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * configuration options, board specific, for Siemens Card Controller Module
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 #undef  CCM_80MHz                       /* define for 80 MHz CPU only */
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #define CONFIG_MPC860           1   /* This is a MPC860 CPU ... */
  39 #define CONFIG_CCM              1   /* on a Card Controller Module  */
  40
  41 #define CONFIG_8xx_CONS_SMC1    1   /* Console is on SMC1       */
  42 #undef  CONFIG_8xx_CONS_SMC2
  43 #undef  CONFIG_8xx_CONS_NONE
  44
  45 /*  ENVIRONMENT */
  46
  47 #define CONFIG_BAUDRATE         19200         /* console baudrate in bps    */
  48 #define CONFIG_BOOTDELAY        2             /* autoboot after 2 seconds   */
  49 #define CONFIG_CLOCKS_IN_MHZ    1             /* clocks passsed to Linux in MHz */
  50
  51 #define CONFIG_IPADDR           192.168.0.42
  52 #define CONFIG_NETMASK          255.255.255.0
  53 #define CONFIG_GATEWAYIP        0.0.0.0
  54 #define CONFIG_SERVERIP         192.168.0.254
  55
  56 #define CONFIG_HOSTNAME         CCM
  57
  58 #define CONFIG_LOADADDR         40180000
  59
  60 #undef  CONFIG_BOOTARGS
  61
  62 #define CONFIG_BOOTCOMMAND      "setenv bootargs " \
  63                                 "mem=$(mem) " \
  64                                 "root=/dev/ram rw ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off " \
  65                                 "wt_8xx=timeout:3600; " \
  66                                 "bootm"
  67
  68 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  69 #undef  CFG_LOADS_BAUD_CHANGE   /* don't allow baudrate change  */
  70
  71 #define CONFIG_WATCHDOG         1       /* watchdog enabled             */
  72
  73 #undef  CONFIG_STATUS_LED               /* Status LED disabled          */
  74
  75 #define CONFIG_PRAM             512     /* reserve 512kB "protected RAM"*/
  76
  77 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  78
  79 #define CONFIG_SPI                      /* enable SPI driver            */
  80 #define CONFIG_SPI_X                    /* 16 bit EEPROM addressing     */
  81
  82 /* ----------------------------------------------------------------
  83  * Offset to initial SPI buffers in DPRAM (used if the environment
  84  * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
  85  * use at an early stage. It is used between the two initialization
  86  * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
  87  * far enough from the start of the data area (as well as from the
  88  * stack pointer).
  89  * ---------------------------------------------------------------- */
  90 #define CFG_SPI_INIT_OFFSET             0xB00
  91
  92 #define CFG_EEPROM_PAGE_WRITE_BITS      5       /* 32-byte page size    */
  93
  94
  95 #define CONFIG_MAC_PARTITION            /* nod used yet                 */
  96 #define CONFIG_DOS_PARTITION
  97
  98 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  99
 100 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
 101                                 CFG_CMD_DHCP    | \
 102                                 CFG_CMD_DATE    | \
 103                                 CFG_CMD_EEPROM  | \
 104                                 CFG_CMD_BSP     )
 105
 106 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 107 #include <cmd_confdefs.h>
 108
 109 /*----------------------------------------------------------------------*/
 110
 111 /*
 112  * Miscellaneous configurable options
 113  */
 114 #define CFG_LONGHELP                    /* undef to save memory         */
 115 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 116 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 117 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 118 #else
 119 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 120 #endif
 121 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 122 #define CFG_MAXARGS     16              /* max number of command args   */
 123 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 124
 125 #define CFG_MEMTEST_START       0x00100000      /* memtest works on     */
 126 #define CFG_MEMTEST_END         0x00F00000      /* 1 ... 15MB in DRAM   */
 127
 128 #define CFG_LOAD_ADDR           0x00100000      /* default load address */
 129
 130 /* Ethernet hardware configuration done using port pins */
 131 #define CFG_PA_ETH_RESET        0x0200          /* PA  6        */
 132 #define CFG_PA_ETH_MDDIS        0x4000          /* PA  1        */
 133 #define CFG_PB_ETH_POWERDOWN    0x00000800      /* PB 20        */
 134 #define CFG_PB_ETH_CFG1         0x00000400      /* PB 21        */
 135 #define CFG_PB_ETH_CFG2         0x00000200      /* PB 22        */
 136 #define CFG_PB_ETH_CFG3         0x00000100      /* PB 23        */
 137
 138 /* Ethernet settings:
 139  * MDIO not disabled, autonegotiation, 10/100Mbps, half/full duplex
 140  */
 141 #define CFG_ETH_MDDIS_VALUE     0
 142 #define CFG_ETH_CFG1_VALUE      1
 143 #define CFG_ETH_CFG2_VALUE      1
 144 #define CFG_ETH_CFG3_VALUE      1
 145
 146 /* PUMA configuration */
 147 #define CFG_PC_PUMA_PROG        0x0200          /* PC  6        */
 148 #define CFG_PC_PUMA_DONE        0x0008          /* PC 12        */
 149 #define CFG_PC_PUMA_INIT        0x0004          /* PC 13        */
 150
 151 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 152
 153 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 154
 155 /*
 156  * Low Level Configuration Settings
 157  * (address mappings, register initial values, etc.)
 158  * You should know what you are doing if you make changes here.
 159  */
 160 /*-----------------------------------------------------------------------
 161  * Internal Memory Mapped Register
 162  */
 163 #define CFG_IMMR                0xF0000000
 164
 165 /*-----------------------------------------------------------------------
 166  * Definitions for initial stack pointer and data area (in DPRAM)
 167  */
 168 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 169 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 170 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 171 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 172 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 173
 174 /*-----------------------------------------------------------------------
 175  * Address accessed to reset the board - must not be mapped/assigned
 176  */
 177 #define CFG_RESET_ADDRESS       0xFEFFFFFF
 178
 179 /*-----------------------------------------------------------------------
 180  * Start addresses for the final memory configuration
 181  * (Set up by the startup code)
 182  * Please note that CFG_SDRAM_BASE _must_ start at 0
 183  */
 184 #define CFG_SDRAM_BASE          0x00000000
 185 #define CFG_FLASH_BASE          0x40000000
 186 #if defined(DEBUG)
 187 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 188 #else
 189 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor   */
 190 #endif
 191 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 192 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 193
 194 /*
 195  * For booting Linux, the board info and command line data
 196  * have to be in the first 8 MB of memory, since this is
 197  * the maximum mapped by the Linux kernel during initialization.
 198  */
 199 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 200
 201 /*-----------------------------------------------------------------------
 202  * FLASH organization
 203  */
 204 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 205 #define CFG_MAX_FLASH_SECT      67      /* max number of sectors on one chip    */
 206
 207 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 208 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 209
 210 #if 1
 211 /* Start port with environment in flash; switch to SPI EEPROM later */
 212 #define CFG_ENV_IS_IN_FLASH     1
 213 #define CFG_ENV_OFFSET          0x8000  /*   Offset   of Environment Sector     */
 214 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 215
 216 /* Address and size of Redundant Environment Sector     */
 217 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SIZE)
 218 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 219 #else
 220 /* Final version: environment in EEPROM */
 221 #define CFG_ENV_IS_IN_EEPROM    1
 222 #define CFG_ENV_OFFSET          2048
 223 #define CFG_ENV_SIZE            2048
 224 #endif
 225
 226 /*-----------------------------------------------------------------------
 227  * Hardware Information Block
 228  */
 229 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 230 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 231 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 232
 233 /*-----------------------------------------------------------------------
 234  * Cache Configuration
 235  */
 236 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 237 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 238
 239 /*-----------------------------------------------------------------------
 240  * SYPCR - System Protection Control                            11-9
 241  * SYPCR can only be written once after reset!
 242  *-----------------------------------------------------------------------
 243  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 244  */
 245 #if defined(CONFIG_WATCHDOG)
 246 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 247                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 248 #else
 249 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 250                                                   SYPCR_SWP)
 251 #endif
 252
 253 /*-----------------------------------------------------------------------
 254  * SIUMCR - SIU Module Configuration                            11-6
 255  *-----------------------------------------------------------------------
 256  * we must activate GPL5 in the SIUMCR for CAN
 257  */
 258 #define CFG_SIUMCR      (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 259
 260 /*-----------------------------------------------------------------------
 261  * TBSCR - Time Base Status and Control                         11-26
 262  *-----------------------------------------------------------------------
 263  * Clear Reference Interrupt Status, Timebase freezing enabled
 264  */
 265 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 266
 267 /*-----------------------------------------------------------------------
 268  * RTCSC - Real-Time Clock Status and Control Register          11-27
 269  *-----------------------------------------------------------------------
 270  */
 271 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 272
 273 /*-----------------------------------------------------------------------
 274  * PISCR - Periodic Interrupt Status and Control                11-31
 275  *-----------------------------------------------------------------------
 276  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 277  */
 278 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 279
 280 /*-----------------------------------------------------------------------
 281  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 282  *-----------------------------------------------------------------------
 283  * Reset PLL lock status sticky bit, timer expired status bit and timer
 284  * interrupt status bit
 285  *
 286  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 287  */
 288 #ifdef  CCM_80MHz       /* for 80 MHz, we use a 16 MHz clock * 5 */
 289 #define CFG_PLPRCR                                                      \
 290                 ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
 291 #else                   /* up to 50 MHz we use a 1:1 clock */
 292 #define CFG_PLPRCR      (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 293 #endif  /* CCM_80MHz */
 294
 295 /*-----------------------------------------------------------------------
 296  * SCCR - System Clock and reset Control Register               15-27
 297  *-----------------------------------------------------------------------
 298  * Set clock output, timebase and RTC source and divider,
 299  * power management and some other internal clocks
 300  */
 301 #define SCCR_MASK       SCCR_EBDF11
 302 #ifdef  CCM_80MHz       /* for 80 MHz, we use a 16 MHz clock * 5 */
 303 #define CFG_SCCR        (/* SCCR_TBS  | */ \
 304                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 305                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 306                          SCCR_DFALCD00)
 307 #else                   /* up to 50 MHz we use a 1:1 clock */
 308 #define CFG_SCCR        (SCCR_TBS     | \
 309                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 310                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 311                          SCCR_DFALCD00)
 312 #endif  /* CCM_80MHz */
 313
 314 /*-----------------------------------------------------------------------
 315  *
 316  * Interrupt Levels
 317  *-----------------------------------------------------------------------
 318  */
 319 #define CFG_CPM_INTERRUPT       13      /* SIU_LEVEL6   */
 320
 321 /*-----------------------------------------------------------------------
 322  *
 323  *-----------------------------------------------------------------------
 324  *
 325  */
 326 #define CFG_DER 0
 327
 328 /*
 329  * Init Memory Controller:
 330  *
 331  * BR0/1 and OR0/1 (FLASH)
 332  */
 333
 334 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 335 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 336
 337 /* used to re-map FLASH both when starting from SRAM or FLASH:
 338  * restrict access enough to keep SRAM working (if any)
 339  * but not too much to meddle with FLASH accesses
 340  */
 341 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 342 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 343
 344 /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1        */
 345 #define CFG_OR_TIMING_FLASH     (OR_CSNT_SAM  | OR_ACS_DIV2 | OR_BI | \
 346                                  OR_SCY_5_CLK | OR_EHTR)
 347
 348 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 349 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 350 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 351
 352 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 353 #define CFG_OR1_PRELIM  CFG_OR0_PRELIM
 354 #define CFG_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 355
 356 /*
 357  * BR2 and OR2 (SDRAM)
 358  *
 359  */
 360 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 361 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 362 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 363
 364 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 365 #define CFG_OR_TIMING_SDRAM     0x00000A00
 366
 367 #define CFG_OR2_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
 368 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 369
 370 /*
 371  * BR3 and OR3 (CAN Controller)
 372  */
 373 #define CFG_CAN_BASE            0xC0000000      /* CAN mapped at 0xC0000000     */
 374 #define CFG_CAN_OR_AM           0xFFFF8000      /* 32 kB address mask           */
 375 #define CFG_OR3_CAN             (CFG_CAN_OR_AM | OR_G5LA | OR_BI)
 376 #define CFG_BR3_CAN             ((CFG_CAN_BASE & BR_BA_MSK) | \
 377                                         BR_PS_8 | BR_MS_UPMB | BR_V )
 378
 379 /*
 380  * BR4/OR4: PUMA Config
 381  *
 382  * Memory controller will be used in 2 modes:
 383  *
 384  * - "read" mode:
 385  *      BR4: 0x10100801         OR4: 0xffff8520
 386  * - "load" mode (chip select on UPM B):
 387  *      BR4: 0x101004c1         OR4: 0xffff8600
 388  *
 389  * Default initialization is in "read" mode
 390  */
 391 #define PUMA_CONF_BASE          0x10100000      /* PUMA Config */
 392 #define PUMA_CONF_OR_AM         0xFFFF8000      /* 32 kB */
 393 #define PUMA_CONF_LOAD_TIMING   (OR_ACS_DIV2     | OR_SCY_2_CLK)
 394 #define PUMA_CONF_READ_TIMING   (OR_G5LA | OR_BI | OR_SCY_2_CLK)
 395
 396 #define PUMA_CONF_BR_LOAD       ((PUMA_CONF_BASE & BR_BA_MSK) | \
 397                                         BR_PS_8  | BR_MS_UPMB | BR_V)
 398 #define PUMA_CONF_OR_LOAD       (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
 399
 400 #define PUMA_CONF_BR_READ       ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 401 #define PUMA_CONF_OR_READ       (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
 402
 403 #define CFG_BR4_PRELIM          PUMA_CONF_BR_READ
 404 #define CFG_OR4_PRELIM          PUMA_CONF_OR_READ
 405
 406 /*
 407  * BR5/OR5: PUMA: SMA Bus 8 Bit
 408  *      BR5: 0x10200401         OR5: 0xffe0010a
 409  */
 410 #define PUMA_SMA8_BASE          0x10200000      /* PUMA SMA Bus 8 Bit */
 411 #define PUMA_SMA8_OR_AM         0xFFE00000      /* 2 MB */
 412 #define PUMA_SMA8_TIMING        (OR_BI | OR_SCY_0_CLK | OR_EHTR)
 413
 414 #define CFG_BR5_PRELIM          ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 415 #define CFG_OR5_PRELIM          (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
 416
 417 /*
 418  * BR6/OR6: PUMA: SMA Bus 16 Bit
 419  *      BR6: 0x10600801         OR6: 0xffe0010a
 420  */
 421 #define PUMA_SMA16_BASE         0x10600000      /* PUMA SMA Bus 16 Bit */
 422 #define PUMA_SMA16_OR_AM        0xFFE00000      /* 2 MB */
 423 #define PUMA_SMA16_TIMING       (OR_BI | OR_SCY_0_CLK | OR_EHTR)
 424
 425 #define CFG_BR6_PRELIM          ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 426 #define CFG_OR6_PRELIM          (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
 427
 428 /*
 429  * BR7/OR7: PUMA: external Flash
 430  *      BR7: 0x10a00801         OR7: 0xfe00010a
 431  */
 432 #define PUMA_FLASH_BASE         0x10A00000      /* PUMA external Flash */
 433 #define PUMA_FLASH_OR_AM        0xFE000000      /* 32 MB */
 434 #define PUMA_FLASH_TIMING       (OR_BI | OR_SCY_0_CLK | OR_EHTR)
 435
 436 #define CFG_BR7_PRELIM          ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 437 #define CFG_OR7_PRELIM          (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
 438
 439
 440 /*
 441  * Memory Periodic Timer Prescaler
 442  */
 443
 444 /* periodic timer for refresh */
 445 #define CFG_MAMR_PTA    97              /* start with divider for 100 MHz       */
 446
 447 /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit     */
 448 #define CFG_MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
 449 #define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
 450
 451 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 452 #define CFG_MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
 453 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 454
 455 /*
 456  * MAMR settings for SDRAM
 457  */
 458
 459 /* 8 column SDRAM */
 460 #define CFG_MAMR_8COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 461                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 462                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 463 /* 9 column SDRAM */
 464 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 465                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 466                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 467
 468
 469 /*
 470  * Internal Definitions
 471  *
 472  * Boot Flags
 473  */
 474 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 475 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 476
 477 #endif  /* __CONFIG_H */