include/configs/CPCI2DP.h

   1 /*
   2  * (C) Copyright 2005
   3  * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  21
  22 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  23
  24 #define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  25
  26 #undef  CONFIG_BOOTARGS
  27 #undef  CONFIG_BOOTCOMMAND
  28
  29 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  30
  31 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  32 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  33
  34 #define CONFIG_MII              1       /* MII PHY management           */
  35 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  36
  37 /*
  38  * BOOTP options
  39  */
  40 #define CONFIG_BOOTP_BOOTFILESIZE
  41 #define CONFIG_BOOTP_BOOTPATH
  42 #define CONFIG_BOOTP_GATEWAY
  43 #define CONFIG_BOOTP_HOSTNAME
  44
  45 /*
  46  * Command line configuration.
  47  */
  48 #define CONFIG_CMD_PCI
  49 #define CONFIG_CMD_IRQ
  50
  51 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  52
  53 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  54
  55 /*
  56  * Miscellaneous configurable options
  57  */
  58 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  59
  60 #if defined(CONFIG_CMD_KGDB)
  61 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  62 #else
  63 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  64 #endif
  65 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  66 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  67 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  68
  69 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
  70
  71 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
  72
  73 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
  74 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
  75
  76 #define CONFIG_CONS_INDEX       2       /* Use UART1                    */
  77 #define CONFIG_SYS_NS16550_SERIAL
  78 #define CONFIG_SYS_NS16550_REG_SIZE     1
  79 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  80
  81 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
  82 #define CONFIG_SYS_BASE_BAUD        691200
  83
  84 /* The following table includes the supported baudrates */
  85 #define CONFIG_SYS_BAUDRATE_TABLE       \
  86         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
  87          57600, 115200, 230400, 460800, 921600 }
  88
  89 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
  90 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
  91
  92 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
  93
  94 /*-----------------------------------------------------------------------
  95  * PCI stuff
  96  *-----------------------------------------------------------------------
  97  */
  98 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
  99 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 100 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 101
 102 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 103 #define CONFIG_PCI_HOST PCI_HOST_AUTO   /* select pci host function     */
 104                                         /* resource configuration       */
 105
 106 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 107
 108 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 109
 110 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 111
 112 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 113 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x040b  /* PCI Device ID: CPCI-2DP      */
 114 #define CONFIG_SYS_PCI_CLASSCODE       0x0280   /* PCI Class Code: Network/Other*/
 115
 116 #define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
 117 #define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
 118 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 119 #define CONFIG_SYS_PCI_PTM2LA   0xef000000      /* point to internal regs + PB0/1 */
 120 #define CONFIG_SYS_PCI_PTM2MS  0xff000001      /* 16MB, enable                  */
 121 #define CONFIG_SYS_PCI_PTM2PCI 0x00000000      /* Host: use this pci address   */
 122
 123 /*-----------------------------------------------------------------------
 124  * Start addresses for the final memory configuration
 125  * (Set up by the startup code)
 126  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 127  */
 128 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 129 #define CONFIG_SYS_FLASH_BASE           0xFFFC0000
 130 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 131 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 132 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 133
 134 /*
 135  * For booting Linux, the board info and command line data
 136  * have to be in the first 8 MB of memory, since this is
 137  * the maximum mapped by the Linux kernel during initialization.
 138  */
 139 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 140 /*-----------------------------------------------------------------------
 141  * FLASH organization
 142  */
 143 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 144 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 145
 146 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 147 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 148
 149 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 150 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 151 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 152
 153 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 154 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 155 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 156
 157 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 158
 159 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 160 #define CONFIG_ENV_OFFSET               0x000   /* environment starts at the beginning of the EEPROM */
 161 #define CONFIG_ENV_SIZE         0x400   /* 1024 bytes may be used for env vars */
 162
 163 /*-----------------------------------------------------------------------
 164  * I2C EEPROM (CAT24WC16) for environment
 165  */
 166 #define CONFIG_SYS_I2C
 167 #define CONFIG_SYS_I2C_PPC4XX
 168 #define CONFIG_SYS_I2C_PPC4XX_CH0
 169 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 170 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 171
 172 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 173 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 174 /* mask of address bits that overflow into the "EEPROM chip address"    */
 175 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 176 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 177                                         /* 16 byte page write mode using*/
 178                                         /* last 4 bits of the address   */
 179 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 180
 181 #define CONFIG_SYS_EEPROM_WREN         1
 182
 183 /*
 184  * Init Memory Controller:
 185  *
 186  * BR0/1 and OR0/1 (FLASH)
 187  */
 188 #define FLASH_BASE0_PRELIM      0xFFE00000      /* FLASH bank #0        */
 189 #define FLASH_BASE1_PRELIM      0               /* FLASH bank #1        */
 190
 191 /*-----------------------------------------------------------------------
 192  * External Bus Controller (EBC) Setup
 193  */
 194
 195 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 196 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 197 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 198
 199 /* Memory Bank 2 (PB0) initialization                                   */
 200 #define CONFIG_SYS_EBC_PB2AP            0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
 201 #define CONFIG_SYS_EBC_PB2CR            0xEF018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 202
 203 /* Memory Bank 3 (PB1) initialization                           */
 204 #define CONFIG_SYS_EBC_PB3AP            0x03004580  /* TWT=6,WBN=1,TH=2,RE=1,SOR=1 */
 205 #define CONFIG_SYS_EBC_PB3CR            0xEF118000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
 206
 207 /*-----------------------------------------------------------------------
 208  * Definitions for initial stack pointer and data area (in data cache)
 209  */
 210 #define CONFIG_SYS_INIT_DCACHE_CS       7       /* use cs # 7 for data cache memory    */
 211
 212 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000  /* use data cache                  */
 213 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in RAM            */
 214 #define CONFIG_SYS_GBL_DATA_OFFSET     (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 215 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 216
 217 /*-----------------------------------------------------------------------
 218  * GPIO definitions
 219  */
 220 #define CONFIG_SYS_EEPROM_WP            (0x80000000 >> 13)   /* GPIO13 */
 221 #define CONFIG_SYS_SELF_RST             (0x80000000 >> 14)   /* GPIO14 */
 222 #define CONFIG_SYS_PB_LED               (0x80000000 >> 16)   /* GPIO16 */
 223 #define CONFIG_SYS_INTA_FAKE            (0x80000000 >> 23)   /* GPIO23 */
 224
 225 #endif  /* __CONFIG_H */