include/configs/CPCI4052.h

   1 /*
   2  * (C) Copyright 2001-2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  21 #define CONFIG_CPCI405          1       /* ...on a CPCI405 board        */
  22 #define CONFIG_CPCI405_VER2     1       /* ...version 2                 */
  23 #undef  CONFIG_CPCI405_6U               /* enable this for 6U boards    */
  24
  25 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  26 #define CONFIG_DISPLAY_BOARDINFO
  27
  28 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  29 #define CONFIG_MISC_INIT_R       1      /* call misc_init_r()           */
  30
  31 #define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  32
  33 #define CONFIG_BAUDRATE         9600
  34 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  35
  36 #undef  CONFIG_BOOTARGS
  37 #undef  CONFIG_BOOTCOMMAND
  38
  39 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  40
  41 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  42 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  43
  44 #define CONFIG_PPC4xx_EMAC
  45 #define CONFIG_MII              1       /* MII PHY management           */
  46 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  47 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  48 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  49
  50 #undef  CONFIG_HAS_ETH1
  51
  52 #define CONFIG_RTC_M48T35A      1               /* ST Electronics M48 timekeeper */
  53
  54 /*
  55  * BOOTP options
  56  */
  57 #define CONFIG_BOOTP_SUBNETMASK
  58 #define CONFIG_BOOTP_GATEWAY
  59 #define CONFIG_BOOTP_HOSTNAME
  60 #define CONFIG_BOOTP_BOOTPATH
  61 #define CONFIG_BOOTP_DNS
  62 #define CONFIG_BOOTP_DNS2
  63 #define CONFIG_BOOTP_SEND_HOSTNAME
  64
  65 /*
  66  * Command line configuration.
  67  */
  68 #define CONFIG_CMD_PCI
  69 #define CONFIG_CMD_IRQ
  70 #define CONFIG_CMD_IDE
  71 #define CONFIG_CMD_DATE
  72 #define CONFIG_CMD_BSP
  73 #define CONFIG_CMD_EEPROM
  74
  75 #define CONFIG_MAC_PARTITION
  76 #define CONFIG_DOS_PARTITION
  77
  78 #define CONFIG_SUPPORT_VFAT
  79
  80 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  81
  82 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  83
  84 /*
  85  * Miscellaneous configurable options
  86  */
  87 #undef CONFIG_SYS_LONGHELP                      /* undef to save memory         */
  88
  89 #if defined(CONFIG_CMD_KGDB)
  90 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  91 #else
  92 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  93 #endif
  94 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  95 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  96 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  97
  98 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
  99
 100 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 101
 102 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 103
 104 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 105 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 106
 107 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 108 #define CONFIG_SYS_NS16550_SERIAL
 109 #define CONFIG_SYS_NS16550_REG_SIZE     1
 110 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 111
 112 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 113 #define CONFIG_SYS_BASE_BAUD        691200
 114
 115 /* The following table includes the supported baudrates */
 116 #define CONFIG_SYS_BAUDRATE_TABLE       \
 117         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 118          57600, 115200, 230400, 460800, 921600 }
 119
 120 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 121 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 122
 123 #define CONFIG_CMDLINE_EDITING          /* add command line history     */
 124
 125 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 126
 127 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 128
 129 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 130
 131 /*-----------------------------------------------------------------------
 132  * PCI stuff
 133  *-----------------------------------------------------------------------
 134  */
 135 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 136 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 137 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 138
 139 #define CONFIG_PCI                      /* include pci support          */
 140 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 141 #define CONFIG_PCI_HOST PCI_HOST_AUTO   /* select pci host function     */
 142 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 143                                         /* resource configuration       */
 144
 145 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 146
 147 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 148
 149 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 150
 151 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 152 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 153 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
 154 #define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 155 #define CONFIG_SYS_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
 156 #define CONFIG_SYS_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
 157 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 158 #define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
 159 #define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 160 #define CONFIG_SYS_PCI_PTM2PCI (bd->bi_memsize) /* host use this pci address */
 161
 162 #define CONFIG_PCI_4xx_PTM_OVERWRITE    1 /* overwrite PTMx settings by env */
 163
 164 /*-----------------------------------------------------------------------
 165  * IDE/ATA stuff
 166  *-----------------------------------------------------------------------
 167  */
 168 #undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
 169 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 170 #define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 171
 172 #define CONFIG_SYS_IDE_MAXBUS           1               /* max. 1 IDE busses    */
 173 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 174
 175 #define CONFIG_SYS_ATA_BASE_ADDR        0xF0100000
 176 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 177
 178 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* Offset for data I/O                  */
 179 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* Offset for normal register accesses  */
 180 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0000  /* Offset for alternate registers       */
 181
 182 /*-----------------------------------------------------------------------
 183  * Start addresses for the final memory configuration
 184  * (Set up by the startup code)
 185  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 186  */
 187 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 188 #define CONFIG_SYS_FLASH_BASE           0xFFFC0000
 189 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 190 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 191 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 192
 193 #define CONFIG_PRAM             0       /* use pram variable to overwrite */
 194
 195 /*
 196  * For booting Linux, the board info and command line data
 197  * have to be in the first 8 MB of memory, since this is
 198  * the maximum mapped by the Linux kernel during initialization.
 199  */
 200 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 201
 202 /*-----------------------------------------------------------------------
 203  * FLASH organization
 204  */
 205 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 206 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 207
 208 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 209 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 210
 211 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 212 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 213 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 214 /*
 215  * The following defines are added for buggy IOP480 byte interface.
 216  * All other boards should use the standard values (CPCI405 etc.)
 217  */
 218 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 219 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 220 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 221
 222 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 223
 224 #if 0 /* Use NVRAM for environment variables */
 225 /*-----------------------------------------------------------------------
 226  * NVRAM organization
 227  */
 228 #define CONFIG_ENV_IS_IN_NVRAM  1       /* use NVRAM for environment vars       */
 229 #define CONFIG_ENV_SIZE         0x0ff8          /* Size of Environment vars     */
 230 #define CONFIG_ENV_ADDR         \
 231         (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-(CONFIG_ENV_SIZE+8))  /* Env  */
 232
 233 #else /* Use EEPROM for environment variables */
 234
 235 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 236 #define CONFIG_ENV_OFFSET               0x000   /* environment starts at the beginning of the EEPROM */
 237 #define CONFIG_ENV_SIZE         0x800   /* 2048 bytes may be used for env vars*/
 238                                    /* total size of a CAT24WC16 is 2048 bytes */
 239 #endif
 240
 241 #define CONFIG_SYS_NVRAM_BASE_ADDR      0xf0200000              /* NVRAM base address   */
 242 #define CONFIG_SYS_NVRAM_SIZE           (32*1024)               /* NVRAM size           */
 243 #define CONFIG_SYS_VXWORKS_MAC_PTR     (CONFIG_SYS_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
 244
 245 /*-----------------------------------------------------------------------
 246  * I2C EEPROM (CAT24WC16) for environment
 247  */
 248 #define CONFIG_SYS_I2C
 249 #define CONFIG_SYS_I2C_PPC4XX
 250 #define CONFIG_SYS_I2C_PPC4XX_CH0
 251 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 252 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 253
 254 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 255 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 256 /* mask of address bits that overflow into the "EEPROM chip address"    */
 257 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 258 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 259                                         /* 16 byte page write mode using*/
 260                                         /* last 4 bits of the address   */
 261 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 262
 263 /*
 264  * Init Memory Controller:
 265  *
 266  * BR0/1 and OR0/1 (FLASH)
 267  */
 268
 269 #define FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank #0        */
 270 #define FLASH_BASE1_PRELIM      0xFFC00000      /* FLASH bank #1        */
 271
 272 /*-----------------------------------------------------------------------
 273  * External Bus Controller (EBC) Setup
 274  */
 275
 276 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 277 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 278 #define CONFIG_SYS_EBC_PB0CR            0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 279
 280 /* Memory Bank 1 (Flash Bank 1) initialization                                  */
 281 #define CONFIG_SYS_EBC_PB1AP            0x92015480
 282 #define CONFIG_SYS_EBC_PB1CR            0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 283
 284 /* Memory Bank 2 (CAN0, 1) initialization                                       */
 285 #define CONFIG_SYS_EBC_PB2AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 286 #define CONFIG_SYS_EBC_PB2CR            0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 287 #define CONFIG_SYS_LED_ADDR             0xF0000380
 288
 289 /* Memory Bank 3 (CompactFlash IDE) initialization                              */
 290 #define CONFIG_SYS_EBC_PB3AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 291 #define CONFIG_SYS_EBC_PB3CR            0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 292
 293 /* Memory Bank 4 (NVRAM/RTC) initialization                                     */
 294 /*#define CONFIG_SYS_EBC_PB4AP            0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1     */
 295 #define CONFIG_SYS_EBC_PB4AP            0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1     */
 296 #define CONFIG_SYS_EBC_PB4CR            0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
 297
 298 /* Memory Bank 5 (optional Quart) initialization                                */
 299 #define CONFIG_SYS_EBC_PB5AP            0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
 300 #define CONFIG_SYS_EBC_PB5CR            0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
 301
 302 /* Memory Bank 6 (FPGA internal) initialization                                 */
 303 #define CONFIG_SYS_EBC_PB6AP            0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 304 #define CONFIG_SYS_EBC_PB6CR            0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 305 #define CONFIG_SYS_FPGA_BASE_ADDR       0xF0400000
 306
 307 /*-----------------------------------------------------------------------
 308  * FPGA stuff
 309  */
 310 /* FPGA internal regs */
 311 #define CONFIG_SYS_FPGA_MODE            0x00
 312 #define CONFIG_SYS_FPGA_STATUS          0x02
 313 #define CONFIG_SYS_FPGA_TS              0x04
 314 #define CONFIG_SYS_FPGA_TS_LOW          0x06
 315 #define CONFIG_SYS_FPGA_TS_CAP0 0x10
 316 #define CONFIG_SYS_FPGA_TS_CAP0_LOW     0x12
 317 #define CONFIG_SYS_FPGA_TS_CAP1 0x14
 318 #define CONFIG_SYS_FPGA_TS_CAP1_LOW     0x16
 319 #define CONFIG_SYS_FPGA_TS_CAP2 0x18
 320 #define CONFIG_SYS_FPGA_TS_CAP2_LOW     0x1a
 321 #define CONFIG_SYS_FPGA_TS_CAP3 0x1c
 322 #define CONFIG_SYS_FPGA_TS_CAP3_LOW     0x1e
 323
 324 /* FPGA Mode Reg */
 325 #define CONFIG_SYS_FPGA_MODE_CF_RESET       0x0001
 326 #define CONFIG_SYS_FPGA_MODE_DUART_RESET   0x0002
 327 #define CONFIG_SYS_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
 328 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_ENABLE 0x0100
 329 #define CONFIG_SYS_FPGA_MODE_TS_IRQ_CLEAR  0x1000
 330 #define CONFIG_SYS_FPGA_MODE_TS_CLEAR       0x2000
 331
 332 /* FPGA Status Reg */
 333 #define CONFIG_SYS_FPGA_STATUS_DIP0     0x0001
 334 #define CONFIG_SYS_FPGA_STATUS_DIP1     0x0002
 335 #define CONFIG_SYS_FPGA_STATUS_DIP2     0x0004
 336 #define CONFIG_SYS_FPGA_STATUS_FLASH    0x0008
 337 #define CONFIG_SYS_FPGA_STATUS_TS_IRQ   0x1000
 338
 339 #define CONFIG_SYS_FPGA_SPARTAN2        1           /* using Xilinx Spartan 2 now    */
 340 #define CONFIG_SYS_FPGA_MAX_SIZE        32*1024     /* 32kByte is enough for XC2S15  */
 341
 342 /* FPGA program pin configuration */
 343 #define CONFIG_SYS_FPGA_PRG             0x04000000  /* FPGA program pin (ppc output) */
 344 #define CONFIG_SYS_FPGA_CLK             0x02000000  /* FPGA clk pin (ppc output)     */
 345 #define CONFIG_SYS_FPGA_DATA            0x01000000  /* FPGA data pin (ppc output)    */
 346 #define CONFIG_SYS_FPGA_INIT            0x00010000  /* FPGA init pin (ppc input)     */
 347 #define CONFIG_SYS_FPGA_DONE            0x00008000  /* FPGA done pin (ppc input)     */
 348
 349 /*-----------------------------------------------------------------------
 350  * Definitions for initial stack pointer and data area (in data cache)
 351  */
 352 #define CONFIG_SYS_INIT_DCACHE_CS       7       /* use cs # 7 for data cache memory    */
 353
 354 #define CONFIG_SYS_INIT_RAM_ADDR        0x40000000  /* use data cache                  */
 355 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in RAM            */
 356 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 357 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 358
 359 #endif  /* __CONFIG_H */