include/configs/CPCI405AB.h

   1 /*
   2  * (C) Copyright 2001-2003
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  37 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38 #define CONFIG_CPCI405          1       /* ...on a CPCI405 board        */
  39 #define CONFIG_CPCI405_VER2     1       /* ...version 2                 */
  40 #define CONFIG_CPCI405AB        1       /* ...and special AB version    */
  41
  42 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  43
  44 #define CONFIG_SYS_CLK_FREQ     33330000 /* external frequency to pll   */
  45
  46 #define CONFIG_BAUDRATE         9600
  47 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  48
  49 #undef  CONFIG_BOOTARGS
  50 #undef  CONFIG_BOOTCOMMAND
  51
  52 #define CONFIG_PREBOOT                  /* enable preboot variable      */
  53
  54 #undef  CONFIG_LOADS_ECHO               /* echo on for serial download  */
  55 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
  56
  57 #define CONFIG_MII              1       /* MII PHY management           */
  58 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  59 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  60 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  61
  62 #define CONFIG_NET_MULTI        1
  63 #undef  CONFIG_HAS_ETH1
  64
  65 #define CONFIG_RTC_M48T35A      1               /* ST Electronics M48 timekeeper */
  66
  67 /*
  68  * BOOTP options
  69  */
  70 #define CONFIG_BOOTP_SUBNETMASK
  71 #define CONFIG_BOOTP_GATEWAY
  72 #define CONFIG_BOOTP_HOSTNAME
  73 #define CONFIG_BOOTP_BOOTPATH
  74 #define CONFIG_BOOTP_DNS
  75 #define CONFIG_BOOTP_DNS2
  76 #define CONFIG_BOOTP_SEND_HOSTNAME
  77
  78
  79 /*
  80  * Command line configuration.
  81  */
  82 #include <config_cmd_default.h>
  83
  84 #define CONFIG_CMD_DHCP
  85 #define CONFIG_CMD_PCI
  86 #define CONFIG_CMD_IRQ
  87 #define CONFIG_CMD_IDE
  88 #define CONFIG_CMD_FAT
  89 #define CONFIG_CMD_ELF
  90 #define CONFIG_CMD_DATE
  91 #define CONFIG_CMD_I2C
  92 #define CONFIG_CMD_MII
  93 #define CONFIG_CMD_PING
  94 #define CONFIG_CMD_EEPROM
  95
  96
  97 #define CONFIG_MAC_PARTITION
  98 #define CONFIG_DOS_PARTITION
  99
 100 #define CONFIG_SUPPORT_VFAT
 101
 102 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 103
 104 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
 105
 106 /*
 107  * Miscellaneous configurable options
 108  */
 109 #define CFG_LONGHELP                    /* undef to save memory         */
 110 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 111
 112 #undef  CFG_HUSH_PARSER                 /* use "hush" command parser    */
 113 #ifdef  CFG_HUSH_PARSER
 114 #define CFG_PROMPT_HUSH_PS2     "> "
 115 #endif
 116
 117 #if defined(CONFIG_CMD_KGDB)
 118 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 119 #else
 120 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 121 #endif
 122 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 123 #define CFG_MAXARGS     16              /* max number of command args   */
 124 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 125
 126 #define CFG_DEVICE_NULLDEV      1       /* include nulldev device       */
 127
 128 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
 129
 130 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 131 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 132
 133 #undef  CFG_EXT_SERIAL_CLOCK           /* no external serial clock used */
 134 #define CFG_IGNORE_405_UART_ERRATA_59   /* ignore ppc405gp errata #59   */
 135 #define CFG_BASE_BAUD       691200
 136
 137 /* The following table includes the supported baudrates */
 138 #define CFG_BAUDRATE_TABLE      \
 139         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 140          57600, 115200, 230400, 460800, 921600 }
 141
 142 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 143 #define CFG_EXTBDINFO   1               /* To use extended board_into (bd_t) */
 144
 145 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 146
 147 #define CONFIG_CMDLINE_EDITING          /* add command line history     */
 148
 149 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 150
 151 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 152
 153 #define CFG_RX_ETH_BUFFER       16      /* use 16 rx buffer on 405 emac */
 154
 155 /*-----------------------------------------------------------------------
 156  * PCI stuff
 157  *-----------------------------------------------------------------------
 158  */
 159 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 160 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 161 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 162
 163 #define CONFIG_PCI                      /* include pci support          */
 164 #define CONFIG_PCI_HOST PCI_HOST_AUTO   /* select pci host function     */
 165 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 166                                         /* resource configuration       */
 167
 168 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 169
 170 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 171
 172 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 173
 174 #define CFG_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 175 #define CFG_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 176 #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A    */
 177 #define CFG_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 178 #define CFG_PCI_PTM1LA  (bd->bi_memstart) /* point to sdram               */
 179 #define CFG_PCI_PTM1MS  (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */
 180 #define CFG_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 181 #define CFG_PCI_PTM2LA  0xffc00000      /* point to flash               */
 182 #define CFG_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 183 #define CFG_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 184
 185 /*-----------------------------------------------------------------------
 186  * IDE/ATA stuff
 187  *-----------------------------------------------------------------------
 188  */
 189 #undef  CONFIG_IDE_8xx_DIRECT               /* no pcmcia interface required */
 190 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 191 #define CONFIG_IDE_RESET        1       /* reset for ide supported      */
 192
 193 #define CFG_IDE_MAXBUS          1               /* max. 1 IDE busses    */
 194 #define CFG_IDE_MAXDEVICE       (CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 195
 196 #define CFG_ATA_BASE_ADDR       0xF0100000
 197 #define CFG_ATA_IDE0_OFFSET     0x0000
 198
 199 #define CFG_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O                  */
 200 #define CFG_ATA_REG_OFFSET      0x0000  /* Offset for normal register accesses  */
 201 #define CFG_ATA_ALT_OFFSET      0x0000  /* Offset for alternate registers       */
 202
 203 /*-----------------------------------------------------------------------
 204  * Start addresses for the final memory configuration
 205  * (Set up by the startup code)
 206  * Please note that CFG_SDRAM_BASE _must_ start at 0
 207  */
 208 #define CFG_SDRAM_BASE          0x00000000
 209 #define CFG_FLASH_BASE          0xFFFC0000
 210 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 211 #define CFG_MONITOR_LEN         (256 * 1024)    /* Reserve 256 kB for Monitor   */
 212 #define CFG_MALLOC_LEN          (256 * 1024)    /* Reserve 256 kB for malloc()  */
 213
 214 /*
 215  * For booting Linux, the board info and command line data
 216  * have to be in the first 8 MB of memory, since this is
 217  * the maximum mapped by the Linux kernel during initialization.
 218  */
 219 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 220
 221 #define CONFIG_OF_LIBFDT
 222 #define CONFIG_OF_BOARD_SETUP
 223
 224 /*-----------------------------------------------------------------------
 225  * FLASH organization
 226  */
 227 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 228 #define CFG_MAX_FLASH_SECT      256     /* max number of sectors on one chip    */
 229
 230 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 231 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 232
 233 #define CFG_FLASH_WORD_SIZE     unsigned short  /* flash word size (width)      */
 234 #define CFG_FLASH_ADDR0         0x5555  /* 1st address for flash config cycles  */
 235 #define CFG_FLASH_ADDR1         0x2AAA  /* 2nd address for flash config cycles  */
 236 /*
 237  * The following defines are added for buggy IOP480 byte interface.
 238  * All other boards should use the standard values (CPCI405 etc.)
 239  */
 240 #define CFG_FLASH_READ0         0x0000  /* 0 is standard                        */
 241 #define CFG_FLASH_READ1         0x0001  /* 1 is standard                        */
 242 #define CFG_FLASH_READ2         0x0002  /* 2 is standard                        */
 243
 244 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 245
 246 /*-----------------------------------------------------------------------
 247  * I2C EEPROM (CAT24WC32) for environment
 248  */
 249 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 250 #define CFG_I2C_SPEED           100000  /* I2C speed and slave address */
 251 #define CFG_I2C_SLAVE           0x7F
 252
 253 #define CFG_I2C_EEPROM_ADDR     0x50    /* EEPROM CAT28WC32             */
 254 #define CFG_I2C_EEPROM_ADDR_LEN 2       /* Bytes of address             */
 255 /* mask of address bits that overflow into the "EEPROM chip address"    */
 256 #define CFG_I2C_EEPROM_ADDR_OVERFLOW    0x01
 257 #define CFG_I2C_MULTI_EEPROMS   1       /* more than one eeprom used!   */
 258 #define CFG_EEPROM_PAGE_WRITE_BITS 5    /* The Catalyst CAT24WC32 has   */
 259                                         /* 32 byte page write mode using*/
 260                                         /* last 5 bits of the address   */
 261 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 262 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 263
 264 /* Use EEPROM for environment variables */
 265
 266 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 267 #define CONFIG_ENV_OFFSET               0x000   /* environment starts at the beginning of the EEPROM */
 268 #define CONFIG_ENV_SIZE         0x800   /* 2048 bytes may be used for env vars*/
 269                                    /* total size of a CAT24WC32 is 4096 bytes */
 270
 271 #define CFG_NVRAM_BASE_ADDR     0xf0200000              /* NVRAM base address   */
 272 #define CFG_NVRAM_SIZE          (32*1024)               /* NVRAM size           */
 273 #define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
 274
 275 /*
 276  * Init Memory Controller:
 277  *
 278  * BR0/1 and OR0/1 (FLASH)
 279  */
 280
 281 #define FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank #0        */
 282 #define FLASH_BASE1_PRELIM      0xFFC00000      /* FLASH bank #1        */
 283
 284 /*-----------------------------------------------------------------------
 285  * External Bus Controller (EBC) Setup
 286  */
 287
 288 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 289 #define CFG_EBC_PB0AP           0x92015480
 290 #define CFG_EBC_PB0CR           0xFFC5A000  /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 291
 292 /* Memory Bank 1 (Flash Bank 1) initialization                                  */
 293 #define CFG_EBC_PB1AP           0x92015480
 294 #define CFG_EBC_PB1CR           0xFF85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 295
 296 /* Memory Bank 2 (CAN0, 1) initialization                                       */
 297 #define CFG_EBC_PB2AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 298 #define CFG_EBC_PB2CR           0xF0018000  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 299 #define CFG_LED_ADDR            0xF0000380
 300
 301 /* Memory Bank 3 (CompactFlash IDE) initialization                              */
 302 #define CFG_EBC_PB3AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 303 #define CFG_EBC_PB3CR           0xF011A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 304
 305 /* Memory Bank 4 (NVRAM/RTC) initialization                                     */
 306 /*#define CFG_EBC_PB4AP           0x01805280  / * TWT=3,WBN=1,WBF=1,TH=1,SOR=1     */
 307 #define CFG_EBC_PB4AP           0x01805680  /* TWT=3,WBN=1,WBF=1,TH=3,SOR=1     */
 308 #define CFG_EBC_PB4CR           0xF0218000  /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit  */
 309
 310 /* Memory Bank 5 (optional Quart) initialization                                */
 311 #define CFG_EBC_PB5AP           0x04005B80  /* TWT=8,WBN=1,WBF=1,TH=5,RE=1,SOR=1*/
 312 #define CFG_EBC_PB5CR           0xF0318000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
 313
 314 /* Memory Bank 6 (FPGA internal) initialization                                 */
 315 #define CFG_EBC_PB6AP           0x010053C0  /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 316 #define CFG_EBC_PB6CR           0xF041A000  /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 317 #define CFG_FPGA_BASE_ADDR      0xF0400000
 318
 319 /*-----------------------------------------------------------------------
 320  * FPGA stuff
 321  */
 322 /* FPGA internal regs */
 323 #define CFG_FPGA_MODE           0x00
 324 #define CFG_FPGA_STATUS         0x02
 325 #define CFG_FPGA_TS             0x04
 326 #define CFG_FPGA_TS_LOW         0x06
 327 #define CFG_FPGA_TS_CAP0        0x10
 328 #define CFG_FPGA_TS_CAP0_LOW    0x12
 329 #define CFG_FPGA_TS_CAP1        0x14
 330 #define CFG_FPGA_TS_CAP1_LOW    0x16
 331 #define CFG_FPGA_TS_CAP2        0x18
 332 #define CFG_FPGA_TS_CAP2_LOW    0x1a
 333 #define CFG_FPGA_TS_CAP3        0x1c
 334 #define CFG_FPGA_TS_CAP3_LOW    0x1e
 335
 336 /* FPGA Mode Reg */
 337 #define CFG_FPGA_MODE_CF_RESET      0x0001
 338 #define CFG_FPGA_MODE_DUART_RESET   0x0002
 339 #define CFG_FPGA_MODE_ENABLE_OUTPUT 0x0004     /* only set on CPCI-405 Ver 3 */
 340 #define CFG_FPGA_MODE_1WIRE_DIR     0x0100     /* dir=1 -> output */
 341 #define CFG_FPGA_MODE_SIM_OK_DIR    0x0200
 342 #define CFG_FPGA_MODE_TESTRIG_FAIL_DIR 0x0400
 343 #define CFG_FPGA_MODE_1WIRE         0x1000
 344 #define CFG_FPGA_MODE_SIM_OK        0x2000     /* wired-or net from all devices */
 345 #define CFG_FPGA_MODE_TESTRIG_FAIL  0x4000
 346
 347 /* FPGA Status Reg */
 348 #define CFG_FPGA_STATUS_DIP0    0x0001
 349 #define CFG_FPGA_STATUS_DIP1    0x0002
 350 #define CFG_FPGA_STATUS_DIP2    0x0004
 351 #define CFG_FPGA_STATUS_FLASH   0x0008
 352 #define CFG_FPGA_STATUS_1WIRE   0x1000
 353 #define CFG_FPGA_STATUS_SIM_OK  0x2000
 354
 355 #define CFG_FPGA_SPARTAN2       1           /* using Xilinx Spartan 2 now    */
 356 #define CFG_FPGA_MAX_SIZE       128*1024    /* 128kByte is enough for XC2S30 */
 357
 358 /* FPGA program pin configuration */
 359 #define CFG_FPGA_PRG            0x04000000  /* FPGA program pin (ppc output) */
 360 #define CFG_FPGA_CLK            0x02000000  /* FPGA clk pin (ppc output)     */
 361 #define CFG_FPGA_DATA           0x01000000  /* FPGA data pin (ppc output)    */
 362 #define CFG_FPGA_INIT           0x00010000  /* FPGA init pin (ppc input)     */
 363 #define CFG_FPGA_DONE           0x00008000  /* FPGA done pin (ppc input)     */
 364
 365 /*-----------------------------------------------------------------------
 366  * Definitions for initial stack pointer and data area (in data cache)
 367  */
 368 #define CFG_INIT_DCACHE_CS      7       /* use cs # 7 for data cache memory    */
 369
 370 #define CFG_INIT_RAM_ADDR       0x40000000  /* use data cache                  */
 371 #define CFG_INIT_RAM_END        0x2000  /* End of used area in RAM             */
 372 #define CFG_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 373 #define CFG_GBL_DATA_OFFSET    (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 374 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 375
 376
 377 /*
 378  * Internal Definitions
 379  *
 380  * Boot Flags
 381  */
 382 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 383 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 384
 385 #endif  /* __CONFIG_H */