include/configs/DU405.h

   1 /*
   2  * (C) Copyright 2001
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  20 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  21 #define CONFIG_DU405            1       /* ...on a DU405 board          */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0xFFFD0000
  24
  25 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  26 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  27
  28 #define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
  29
  30 #define CONFIG_BAUDRATE         9600
  31 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  32
  33 #undef  CONFIG_BOOTARGS
  34 #define CONFIG_BOOTCOMMAND      "bootm fff00000"
  35
  36 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  37 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  38
  39 #define CONFIG_PPC4xx_EMAC
  40 #define CONFIG_MII              1       /* MII PHY management           */
  41 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  42 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  43 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  44 #undef  CONFIG_HAS_ETH1
  45
  46 /*
  47  * BOOTP options
  48  */
  49 #define CONFIG_BOOTP_BOOTFILESIZE
  50 #define CONFIG_BOOTP_BOOTPATH
  51 #define CONFIG_BOOTP_GATEWAY
  52 #define CONFIG_BOOTP_HOSTNAME
  53
  54
  55 /*
  56  * Command line configuration.
  57  */
  58 #include <config_cmd_default.h>
  59
  60 #undef CONFIG_CMD_NFS
  61 #undef CONFIG_CMD_EDITENV
  62 #undef CONFIG_CMD_IMLS
  63 #undef CONFIG_CMD_CONSOLE
  64 #undef CONFIG_CMD_LOADB
  65 #undef CONFIG_CMD_LOADS
  66 #define CONFIG_CMD_IDE
  67 #define CONFIG_CMD_ELF
  68 #define CONFIG_CMD_MII
  69 #define CONFIG_CMD_DATE
  70 #define CONFIG_CMD_EEPROM
  71 #define CONFIG_CMD_I2C
  72
  73 #define CONFIG_MAC_PARTITION
  74 #define CONFIG_DOS_PARTITION
  75
  76 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
  77
  78 #define CONFIG_RTC_MC146818             /* BQ3285 is MC146818 compatible*/
  79 #define CONFIG_SYS_RTC_REG_BASE_ADDR     0xF0000080 /* RTC Base Address         */
  80
  81 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  82
  83 /*
  84  * Miscellaneous configurable options
  85  */
  86 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  87 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
  88 #if defined(CONFIG_CMD_KGDB)
  89 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
  90 #else
  91 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
  92 #endif
  93 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  94 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
  95 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  96
  97 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
  98
  99 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 100 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 101
 102 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 103 #define CONFIG_SYS_NS16550
 104 #define CONFIG_SYS_NS16550_SERIAL
 105 #define CONFIG_SYS_NS16550_REG_SIZE     1
 106 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 107
 108 #define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200  /* use external serial clock  */
 109
 110 /* The following table includes the supported baudrates */
 111 #define CONFIG_SYS_BAUDRATE_TABLE       \
 112         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 113          57600, 115200, 230400, 460800, 921600 }
 114
 115 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 116 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 117
 118 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 119
 120 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 121
 122 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 123
 124 /*-----------------------------------------------------------------------
 125  * IDE/ATA stuff
 126  *-----------------------------------------------------------------------
 127  */
 128 #undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
 129 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 130 #undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
 131
 132 #define CONFIG_SYS_IDE_MAXBUS           1               /* max. 1 IDE busses    */
 133 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 134
 135 #define CONFIG_SYS_ATA_BASE_ADDR        0xF0100000
 136 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 137
 138 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* Offset for data I/O                  */
 139 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* Offset for normal register accesses  */
 140 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0000  /* Offset for alternate registers       */
 141
 142 /*-----------------------------------------------------------------------
 143  * Start addresses for the final memory configuration
 144  * (Set up by the startup code)
 145  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 146  */
 147 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 148 #define CONFIG_SYS_FLASH_BASE           0xFFFD0000
 149 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 150 #define CONFIG_SYS_MONITOR_LEN          (192 * 1024)    /* Reserve 192 kB for Monitor   */
 151 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 152
 153 /*
 154  * For booting Linux, the board info and command line data
 155  * have to be in the first 8 MB of memory, since this is
 156  * the maximum mapped by the Linux kernel during initialization.
 157  */
 158 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 159 /*-----------------------------------------------------------------------
 160  * FLASH organization
 161  */
 162 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 163 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 164
 165 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 166 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 167
 168 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 169 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 170 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 171 /*
 172  * The following defines are added for buggy IOP480 byte interface.
 173  * All other boards should use the standard values (CPCI405 etc.)
 174  */
 175 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 176 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 177 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 178
 179 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 180
 181 /*-----------------------------------------------------------------------
 182  * I2C EEPROM (CAT24WC08) for environment
 183  */
 184 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 185 #define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 186 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 187 #define CONFIG_SYS_I2C_SLAVE            0x7F
 188
 189 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 190 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 191 /* mask of address bits that overflow into the "EEPROM chip address"    */
 192 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 193 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 194                                         /* 16 byte page write mode using*/
 195                                         /* last 4 bits of the address   */
 196 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 197
 198 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 199 #define CONFIG_ENV_OFFSET               0x000   /* environment starts at the beginning of the EEPROM */
 200 #define CONFIG_ENV_SIZE         0x400   /* 1024 bytes may be used for env vars */
 201                                    /* total size of a CAT24WC08 is 1024 bytes */
 202
 203 /*
 204  * Init Memory Controller:
 205  *
 206  * BR0/1 and OR0/1 (FLASH)
 207  */
 208
 209 #define FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank #0        */
 210 #define FLASH_BASE1_PRELIM      0xFFC00000      /* FLASH bank #1        */
 211
 212 /*-----------------------------------------------------------------------
 213  * External Bus Controller (EBC) Setup
 214  */
 215
 216 #define FLASH0_BA       0xFFC00000          /* FLASH 0 Base Address             */
 217 #define FLASH1_BA       0xFF800000          /* FLASH 1 Base Address             */
 218 #define CAN_BA          0xF0000000          /* CAN Base Address                 */
 219 #define DUART_BA        0xF0300000          /* DUART Base Address               */
 220 #define CF_BA           0xF0100000          /* CompactFlash Base Address        */
 221 #define SRAM_BA         0xF0200000          /* SRAM Base Address                */
 222 #define DURAG_IO_BA     0xF0400000          /* DURAG Bus IO Base Address        */
 223 #define DURAG_MEM_BA    0xF0500000          /* DURAG Bus Mem Base Address       */
 224
 225 #define FPGA_MODE_REG   (DUART_BA+0x80)     /* FPGA Mode Register               */
 226
 227 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 228 #define CONFIG_SYS_EBC_PB0AP    0x92015480
 229 #define CONFIG_SYS_EBC_PB0CR    FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 230
 231 /* Memory Bank 1 (Flash Bank 1) initialization                                  */
 232 #define CONFIG_SYS_EBC_PB1AP    0x92015480
 233 #define CONFIG_SYS_EBC_PB1CR    FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 234
 235 /* Memory Bank 2 (CAN0) initialization                                          */
 236 #define CONFIG_SYS_EBC_PB2AP    0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 237 #define CONFIG_SYS_EBC_PB2CR    CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 238
 239 /* Memory Bank 3 (DUART) initialization                                         */
 240 #define CONFIG_SYS_EBC_PB3AP    0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 241 #define CONFIG_SYS_EBC_PB3CR    DUART_BA | 0x18000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
 242
 243 /* Memory Bank 4 (CompactFlash IDE) initialization                              */
 244 #define CONFIG_SYS_EBC_PB4AP    0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 245 #define CONFIG_SYS_EBC_PB4CR    CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 246
 247 /* Memory Bank 5 (SRAM) initialization                                          */
 248 #define CONFIG_SYS_EBC_PB5AP    0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 249 #define CONFIG_SYS_EBC_PB5CR    SRAM_BA | 0x1A000   /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
 250
 251 /* Memory Bank 6 (DURAG Bus IO Space) initialization                            */
 252 #define CONFIG_SYS_EBC_PB6AP    0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 253 #define CONFIG_SYS_EBC_PB6CR    DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/
 254
 255 /* Memory Bank 7 (DURAG Bus Mem Space) initialization                           */
 256 #define CONFIG_SYS_EBC_PB7AP    0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 257 #define CONFIG_SYS_EBC_PB7CR    DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
 258
 259
 260 /*-----------------------------------------------------------------------
 261  * Definitions for initial stack pointer and data area (in DPRAM)
 262  */
 263
 264 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 265 #define CONFIG_SYS_TEMP_STACK_OCM         1
 266
 267 /* On Chip Memory location */
 268 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 269 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 270
 271 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 272 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 273 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 274 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 275
 276 #endif  /* __CONFIG_H */