include/configs/DU405.h

   1 /*
   2  * (C) Copyright 2001
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35 #define CONFIG_405GP            1       /* This is a PPC405 CPU         */
  36 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  37 #define CONFIG_DU405            1       /* ...on a DU405 board          */
  38
  39 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  40 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  41
  42 #define CONFIG_SYS_CLK_FREQ     25000000 /* external frequency to pll   */
  43
  44 #define CONFIG_BAUDRATE         9600
  45 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
  46
  47 #undef  CONFIG_BOOTARGS
  48 #define CONFIG_BOOTCOMMAND      "bootm fff00000"
  49
  50 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  51 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  52
  53 #define CONFIG_PPC4xx_EMAC
  54 #define CONFIG_MII              1       /* MII PHY management           */
  55 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  56 #define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
  57 #define CONFIG_RESET_PHY_R      1       /* use reset_phy() to disable phy sleep mode */
  58 #define CONFIG_NET_MULTI        1
  59 #undef  CONFIG_HAS_ETH1
  60
  61 /*
  62  * BOOTP options
  63  */
  64 #define CONFIG_BOOTP_BOOTFILESIZE
  65 #define CONFIG_BOOTP_BOOTPATH
  66 #define CONFIG_BOOTP_GATEWAY
  67 #define CONFIG_BOOTP_HOSTNAME
  68
  69
  70 /*
  71  * Command line configuration.
  72  */
  73 #include <config_cmd_default.h>
  74
  75 #undef CONFIG_CMD_NFS
  76 #define CONFIG_CMD_IDE
  77 #define CONFIG_CMD_ELF
  78 #define CONFIG_CMD_MII
  79 #define CONFIG_CMD_DATE
  80 #define CONFIG_CMD_EEPROM
  81 #define CONFIG_CMD_I2C
  82
  83 #define CONFIG_MAC_PARTITION
  84 #define CONFIG_DOS_PARTITION
  85
  86 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
  87
  88 #define CONFIG_RTC_MC146818             /* BQ3285 is MC146818 compatible*/
  89 #define CONFIG_SYS_RTC_REG_BASE_ADDR     0xF0000080 /* RTC Base Address         */
  90
  91 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
  92
  93 /*
  94  * Miscellaneous configurable options
  95  */
  96 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
  97 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
  98 #if defined(CONFIG_CMD_KGDB)
  99 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 100 #else
 101 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 102 #endif
 103 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 104 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 105 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 106
 107 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 108
 109 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 110 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 111
 112 #define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200  /* use external serial clock  */
 113
 114 /* The following table includes the supported baudrates */
 115 #define CONFIG_SYS_BAUDRATE_TABLE       \
 116         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 117          57600, 115200, 230400, 460800, 921600 }
 118
 119 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 120 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 121
 122 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 123
 124 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 125
 126 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 127
 128 /*-----------------------------------------------------------------------
 129  * PCI stuff
 130  *-----------------------------------------------------------------------
 131  */
 132 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 133 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 134 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 135
 136 #define CONFIG_PCI                      /* include pci support          */
 137 #define CONFIG_PCI_HOST PCI_HOST_AUTO   /* select pci host function     */
 138 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 139                                         /* resource configuration       */
 140
 141 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 142
 143 #define CONFIG_PCI_BOOTDELAY    0       /* enable pci bootdelay variable*/
 144
 145 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE   /* PCI Vendor ID: esd gmbh      */
 146 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404   /* PCI Device ID: CPCI-ISER4    */
 147 #define CONFIG_SYS_PCI_PTM1LA   0x00000000      /* point to sdram               */
 148 #define CONFIG_SYS_PCI_PTM1MS   0xff000001      /* 16MB, enable hard-wired to 1 */
 149 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000       /* Host: use this pci address   */
 150 #define CONFIG_SYS_PCI_PTM2LA   0xffe00000      /* point to flash               */
 151 #define CONFIG_SYS_PCI_PTM2MS   0xffe00001      /* 2MB, enable                  */
 152 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000       /* Host: use this pci address   */
 153
 154 /*-----------------------------------------------------------------------
 155  * IDE/ATA stuff
 156  *-----------------------------------------------------------------------
 157  */
 158 #undef  CONFIG_IDE_8xx_DIRECT           /* no pcmcia interface required */
 159 #undef  CONFIG_IDE_LED                  /* no led for ide supported     */
 160 #undef  CONFIG_IDE_RESET                /* no reset for ide supported   */
 161
 162 #define CONFIG_SYS_IDE_MAXBUS           1               /* max. 1 IDE busses    */
 163 #define CONFIG_SYS_IDE_MAXDEVICE        (CONFIG_SYS_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */
 164
 165 #define CONFIG_SYS_ATA_BASE_ADDR        0xF0100000
 166 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 167
 168 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0000  /* Offset for data I/O                  */
 169 #define CONFIG_SYS_ATA_REG_OFFSET       0x0000  /* Offset for normal register accesses  */
 170 #define CONFIG_SYS_ATA_ALT_OFFSET       0x0000  /* Offset for alternate registers       */
 171
 172 /*-----------------------------------------------------------------------
 173  * Start addresses for the final memory configuration
 174  * (Set up by the startup code)
 175  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 176  */
 177 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 178 #define CONFIG_SYS_FLASH_BASE           0xFFFD0000
 179 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 180 #define CONFIG_SYS_MONITOR_LEN          (192 * 1024)    /* Reserve 192 kB for Monitor   */
 181 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024)    /* Reserve 128 kB for malloc()  */
 182
 183 /*
 184  * For booting Linux, the board info and command line data
 185  * have to be in the first 8 MB of memory, since this is
 186  * the maximum mapped by the Linux kernel during initialization.
 187  */
 188 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 189 /*-----------------------------------------------------------------------
 190  * FLASH organization
 191  */
 192 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 193 #define CONFIG_SYS_MAX_FLASH_SECT       256     /* max number of sectors on one chip    */
 194
 195 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 196 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 197
 198 #define CONFIG_SYS_FLASH_WORD_SIZE      unsigned short  /* flash word size (width)      */
 199 #define CONFIG_SYS_FLASH_ADDR0          0x5555  /* 1st address for flash config cycles  */
 200 #define CONFIG_SYS_FLASH_ADDR1          0x2AAA  /* 2nd address for flash config cycles  */
 201 /*
 202  * The following defines are added for buggy IOP480 byte interface.
 203  * All other boards should use the standard values (CPCI405 etc.)
 204  */
 205 #define CONFIG_SYS_FLASH_READ0          0x0000  /* 0 is standard                        */
 206 #define CONFIG_SYS_FLASH_READ1          0x0001  /* 1 is standard                        */
 207 #define CONFIG_SYS_FLASH_READ2          0x0002  /* 2 is standard                        */
 208
 209 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 210
 211 /*-----------------------------------------------------------------------
 212  * I2C EEPROM (CAT24WC08) for environment
 213  */
 214 #define CONFIG_HARD_I2C                 /* I2c with hardware support */
 215 #define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 216 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address */
 217 #define CONFIG_SYS_I2C_SLAVE            0x7F
 218
 219 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT28WC08             */
 220 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 221 /* mask of address bits that overflow into the "EEPROM chip address"    */
 222 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 223 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 224                                         /* 16 byte page write mode using*/
 225                                         /* last 4 bits of the address   */
 226 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 227
 228 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 229 #define CONFIG_ENV_OFFSET               0x000   /* environment starts at the beginning of the EEPROM */
 230 #define CONFIG_ENV_SIZE         0x400   /* 1024 bytes may be used for env vars */
 231                                    /* total size of a CAT24WC08 is 1024 bytes */
 232
 233 /*
 234  * Init Memory Controller:
 235  *
 236  * BR0/1 and OR0/1 (FLASH)
 237  */
 238
 239 #define FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank #0        */
 240 #define FLASH_BASE1_PRELIM      0xFFC00000      /* FLASH bank #1        */
 241
 242 /*-----------------------------------------------------------------------
 243  * External Bus Controller (EBC) Setup
 244  */
 245
 246 #define FLASH0_BA       0xFFC00000          /* FLASH 0 Base Address             */
 247 #define FLASH1_BA       0xFF800000          /* FLASH 1 Base Address             */
 248 #define CAN_BA          0xF0000000          /* CAN Base Address                 */
 249 #define DUART_BA        0xF0300000          /* DUART Base Address               */
 250 #define CF_BA           0xF0100000          /* CompactFlash Base Address        */
 251 #define SRAM_BA         0xF0200000          /* SRAM Base Address                */
 252 #define DURAG_IO_BA     0xF0400000          /* DURAG Bus IO Base Address        */
 253 #define DURAG_MEM_BA    0xF0500000          /* DURAG Bus Mem Base Address       */
 254
 255 #define FPGA_MODE_REG   (DUART_BA+0x80)     /* FPGA Mode Register               */
 256
 257 /* Memory Bank 0 (Flash Bank 0) initialization                                  */
 258 #define CONFIG_SYS_EBC_PB0AP    0x92015480
 259 #define CONFIG_SYS_EBC_PB0CR    FLASH0_BA | 0x5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
 260
 261 /* Memory Bank 1 (Flash Bank 1) initialization                                  */
 262 #define CONFIG_SYS_EBC_PB1AP    0x92015480
 263 #define CONFIG_SYS_EBC_PB1CR    FLASH1_BA | 0x5A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
 264
 265 /* Memory Bank 2 (CAN0) initialization                                          */
 266 #define CONFIG_SYS_EBC_PB2AP    0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 267 #define CONFIG_SYS_EBC_PB2CR    CAN_BA | 0x18000    /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 268
 269 /* Memory Bank 3 (DUART) initialization                                         */
 270 #define CONFIG_SYS_EBC_PB3AP    0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 271 #define CONFIG_SYS_EBC_PB3CR    DUART_BA | 0x18000  /* BAS=0xF03,BS=1MB,BU=R/W,BW=8bit  */
 272
 273 /* Memory Bank 4 (CompactFlash IDE) initialization                              */
 274 #define CONFIG_SYS_EBC_PB4AP    0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 275 #define CONFIG_SYS_EBC_PB4CR    CF_BA | 0x1A000     /* BAS=0xF01,BS=1MB,BU=R/W,BW=16bit */
 276
 277 /* Memory Bank 5 (SRAM) initialization                                          */
 278 #define CONFIG_SYS_EBC_PB5AP    0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 279 #define CONFIG_SYS_EBC_PB5CR    SRAM_BA | 0x1A000   /* BAS=0xF02,BS=1MB,BU=R/W,BW=16bit */
 280
 281 /* Memory Bank 6 (DURAG Bus IO Space) initialization                            */
 282 #define CONFIG_SYS_EBC_PB6AP    0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 283 #define CONFIG_SYS_EBC_PB6CR    DURAG_IO_BA | 0x18000 /* BAS=0xF04,BS=1MB,BU=R/W,BW=8bit*/
 284
 285 /* Memory Bank 7 (DURAG Bus Mem Space) initialization                           */
 286 #define CONFIG_SYS_EBC_PB7AP    0x010053C0   /* BWT=2,WBN=1,WBF=1,TH=1,RE=1,SOR=1,BEM=1 */
 287 #define CONFIG_SYS_EBC_PB7CR    DURAG_MEM_BA | 0x18000 /* BAS=0xF05,BS=1MB,BU=R/W,BW=8bit */
 288
 289
 290 /*-----------------------------------------------------------------------
 291  * Definitions for initial stack pointer and data area (in DPRAM)
 292  */
 293
 294 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 295 #define CONFIG_SYS_TEMP_STACK_OCM         1
 296
 297 /* On Chip Memory location */
 298 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 299 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 300
 301 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 302 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM     */
 303 #define CONFIG_SYS_GBL_DATA_SIZE      128  /* size in bytes reserved for initial data */
 304 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 305 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 306
 307
 308 /*
 309  * Internal Definitions
 310  *
 311  * Boot Flags
 312  */
 313 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 314 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 315
 316 #endif  /* __CONFIG_H */