include/configs/DU440.h

   1 /*
   2  * (C) Copyright 2008
   3  * Matthias Fuchs, esd gmbh, matthias.fuchs@esd-electronics.com
   4  *
   5  * based on the Sequoia board configuration by
   6  * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 /*
  12  **********************************************************************
  13  * DU440.h - configuration for esd's DU440 board (Power PC440EPx)
  14  **********************************************************************
  15  */
  16 #ifndef __CONFIG_H
  17 #define __CONFIG_H
  18
  19 /*
  20  * High Level Configuration Options
  21  */
  22 #define CONFIG_DU440            1               /* Board is esd DU440   */
  23 #define CONFIG_440EPX           1               /* Specific PPC440EPx   */
  24 #define CONFIG_4xx              1               /* ... PPC4xx family    */
  25 #define CONFIG_SYS_CLK_FREQ     33333400        /* external freq to pll */
  26
  27 #ifndef CONFIG_SYS_TEXT_BASE
  28 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  29 #endif
  30
  31 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  32 #define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
  33 #define CONFIG_LAST_STAGE_INIT  1               /* last_stage_init      */
  34
  35 /*
  36  * Base addresses -- Note these are effective addresses where the
  37  * actual resources get mapped (not physical addresses)
  38  */
  39 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024)    /* Reserve 384 kB for Monitor */
  40 #define CONFIG_SYS_MALLOC_LEN           (8 << 20)       /* Reserve 8 MB for malloc()  */
  41
  42 #define CONFIG_SYS_BOOT_BASE_ADDR       0xf0000000
  43 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* _must_ be 0          */
  44 #define CONFIG_SYS_FLASH_BASE           0xfc000000      /* start of FLASH       */
  45 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  46 #define CONFIG_SYS_NAND0_ADDR           0xd0000000      /* NAND Flash           */
  47 #define CONFIG_SYS_NAND1_ADDR           0xd0100000      /* NAND Flash           */
  48 #define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  49 #define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  50 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  51 #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE  + 0x10000000
  52 #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000
  53 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000
  54 #define CONFIG_SYS_PCI_IOBASE           0xe8000000
  55 #define CONFIG_SYS_PCI_SUBSYS_VENDORID  PCI_VENDOR_ID_ESDGMBH
  56 #define CONFIG_SYS_PCI_SUBSYS_ID        0x0444          /* device ID for DU440 */
  57
  58 #define CONFIG_SYS_USB2D0_BASE          0xe0000100
  59 #define CONFIG_SYS_USB_DEVICE           0xe0000000
  60 #define CONFIG_SYS_USB_HOST             0xe0000400
  61
  62 /*
  63  * Initial RAM & stack pointer
  64  */
  65 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
  66 #define CONFIG_SYS_INIT_RAM_OCM 1               /* OCM as init ram      */
  67 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
  68
  69 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  70 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  71 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
  72
  73 /*
  74  * Serial Port
  75  */
  76 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  77 #define CONFIG_SYS_NS16550
  78 #define CONFIG_SYS_NS16550_SERIAL
  79 #define CONFIG_SYS_NS16550_REG_SIZE     1
  80 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  81 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
  82 #define CONFIG_BAUDRATE         115200
  83
  84 #define CONFIG_SYS_BAUDRATE_TABLE                                               \
  85         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  86
  87 /*
  88  * Video Port
  89  */
  90 #define CONFIG_VIDEO
  91 #define CONFIG_VIDEO_SMI_LYNXEM
  92 #define CONFIG_CFB_CONSOLE
  93 #define CONFIG_VIDEO_LOGO
  94 #define CONFIG_VGA_AS_SINGLE_DEVICE
  95 #define CONFIG_SPLASH_SCREEN
  96 #define CONFIG_SPLASH_SCREEN_ALIGN
  97 #define CONFIG_VIDEO_BMP_GZIP              /* gzip compressed bmp images */
  98 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (4 << 20)  /* for decompressed img */
  99 #define CONFIG_SYS_DEFAULT_VIDEO_MODE 0x31a       /* 1280x1024,16bpp */
 100 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 101 #define CONFIG_SYS_ISA_IO CONFIG_SYS_PCI_IOBASE
 102
 103 /*
 104  * Environment
 105  */
 106 #define CONFIG_ENV_IS_IN_EEPROM    1    /* use FLASH for environment vars */
 107
 108 /*
 109  * FLASH related
 110  */
 111 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible */
 112 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver       */
 113
 114 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 115
 116 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks         */
 117 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip  */
 118
 119 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)    */
 120 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)    */
 121
 122 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)   */
 123 /* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */
 124 #define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection      */
 125
 126 #define CONFIG_SYS_FLASH_EMPTY_INFO
 127 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash      */
 128
 129 #ifdef CONFIG_ENV_IS_IN_FLASH
 130 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector        */
 131 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 132 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector   */
 133
 134 /* Address and size of Redundant Environment Sector     */
 135 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 136 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 137 #endif
 138
 139 #ifdef CONFIG_ENV_IS_IN_EEPROM
 140 #define CONFIG_ENV_OFFSET               0       /* environment starts at */
 141                                         /* the beginning of the EEPROM */
 142 #define CONFIG_ENV_SIZE         0x1000 /* 4096 bytes may be used for env vars */
 143 #endif
 144
 145 /*
 146  * DDR SDRAM
 147  */
 148 #define CONFIG_SYS_MBYTES_SDRAM        (1024)   /* 512 MiB      TODO: remove    */
 149 #define CONFIG_DDR_DATA_EYE             /* use DDR2 optimization        */
 150 #define CONFIG_SYS_MEM_TOP_HIDE        (4 << 10) /* don't use last 4kbytes     */
 151                                         /* 440EPx errata CHIP 11        */
 152 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup     */
 153 #define CONFIG_DDR_ECC                  /* Use ECC when available       */
 154 #define SPD_EEPROM_ADDRESS      {0x50}
 155 #define CONFIG_PROG_SDRAM_TLB
 156
 157 /*
 158  * I2C
 159  */
 160 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 161 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 162 #define CONFIG_PPC4XX_I2C               /* use PPC4xx driver            */
 163 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address  */
 164 #define CONFIG_SYS_I2C_SLAVE            0x7F
 165 #define CONFIG_I2C_MULTI_BUS    1
 166
 167 #define CONFIG_SYS_SPD_BUS_NUM         0
 168 #define IIC1_MCP3021_ADDR       0x4d
 169 #define IIC1_USB2507_ADDR       0x2c
 170 #ifdef CONFIG_I2C_MULTI_BUS
 171 #define CONFIG_SYS_I2C_NOPROBES        {{1, IIC1_USB2507_ADDR}}
 172 #endif
 173 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 174 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x54
 175 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 176 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5
 177 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 178 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x01
 179
 180 #define CONFIG_SYS_EEPROM_WREN         1
 181 #define CONFIG_SYS_I2C_BOOT_EEPROM_ADDR 0x52
 182
 183 /*
 184  * standard dtt sensor configuration - bottom bit will determine local or
 185  * remote sensor of the TMP401
 186  */
 187 #define CONFIG_DTT_SENSORS              { 0, 1 }
 188
 189 /*
 190  * The PMC440 uses a TI TMP401 temperature sensor. This part
 191  * is basically compatible to the ADM1021 that is supported
 192  * by U-Boot.
 193  *
 194  * - i2c addr 0x4c
 195  * - conversion rate 0x02 = 0.25 conversions/second
 196  * - ALERT ouput disabled
 197  * - local temp sensor enabled, min set to 0 deg, max set to 70 deg
 198  * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg
 199  */
 200 #define CONFIG_DTT_ADM1021
 201 #define CONFIG_SYS_DTT_ADM1021          { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} }
 202
 203 /*
 204  * RTC stuff
 205  */
 206 #define CONFIG_RTC_DS1338
 207 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 208
 209 #undef  CONFIG_BOOTARGS
 210
 211 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 212         "netdev=eth0\0"                                                 \
 213         "ethrotate=no\0"                                                \
 214         "hostname=du440\0"                                              \
 215         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 216                 "nfsroot=${serverip}:${rootpath}\0"                     \
 217         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 218         "addip=setenv bootargs ${bootargs} "                            \
 219                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 220                 ":${hostname}:${netdev}:off panic=1\0"                  \
 221         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 222         "flash_self=run ramargs addip addtty optargs;"                  \
 223                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 224         "net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;"  \
 225                 "bootm\0"                                               \
 226         "rootpath=/tftpboot/du440/target_root_du440\0"                  \
 227         "img=/tftpboot/du440/uImage\0"                                  \
 228         "kernel_addr=FFC00000\0"                                        \
 229         "ramdisk_addr=FFE00000\0"                                       \
 230         "initrd_high=30000000\0"                                        \
 231         "load=tftp 100000 /tftpboot/du440/u-boot.bin\0"                 \
 232         "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"   \
 233                 "cp.b 100000 FFFA0000 60000\0"                          \
 234         ""
 235
 236 #define CONFIG_PREBOOT                  /* enable preboot variable      */
 237
 238 #define CONFIG_BOOTDELAY        3       /* autoboot after 5 seconds     */
 239
 240 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 241 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 242
 243 #ifndef __ASSEMBLY__
 244 int du440_phy_addr(int devnum);
 245 #endif
 246
 247 #define CONFIG_PPC4xx_EMAC
 248 #define CONFIG_IBM_EMAC4_V4     1
 249 #define CONFIG_MII              1       /* MII PHY management           */
 250 #define CONFIG_PHY_ADDR         du440_phy_addr(0) /* PHY address        */
 251
 252 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 253 #undef CONFIG_PHY_GIGE                  /* no GbE detection             */
 254
 255 #define CONFIG_HAS_ETH0
 256 #define CONFIG_SYS_RX_ETH_BUFFER        128
 257
 258 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 259 #define CONFIG_PHY1_ADDR        du440_phy_addr(1)
 260
 261 /*
 262  * USB
 263  */
 264 #define CONFIG_USB_OHCI_NEW
 265 #define CONFIG_USB_STORAGE
 266 #define CONFIG_SYS_OHCI_BE_CONTROLLER
 267
 268 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
 269 #define CONFIG_SYS_USB_OHCI_REGS_BASE   CONFIG_SYS_USB_HOST
 270 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "du440"
 271 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 272
 273 /* Comment this out to enable USB 1.1 device */
 274 #define USB_2_0_DEVICE
 275
 276 /* Partitions */
 277 #define CONFIG_MAC_PARTITION
 278 #define CONFIG_DOS_PARTITION
 279 #define CONFIG_ISO_PARTITION
 280
 281 #include <config_cmd_default.h>
 282
 283 #define CONFIG_CMD_ASKENV
 284 #define CONFIG_CMD_BMP
 285 #define CONFIG_CMD_BSP
 286 #define CONFIG_CMD_DATE
 287 #define CONFIG_CMD_DHCP
 288 #define CONFIG_CMD_DIAG
 289 #define CONFIG_CMD_DTT
 290 #define CONFIG_CMD_EEPROM
 291 #define CONFIG_CMD_ELF
 292 #define CONFIG_CMD_FAT
 293 #define CONFIG_CMD_I2C
 294 #define CONFIG_CMD_IRQ
 295 #define CONFIG_CMD_MII
 296 #define CONFIG_CMD_NAND
 297 #define CONFIG_CMD_NET
 298 #define CONFIG_CMD_NFS
 299 #define CONFIG_CMD_PCI
 300 #define CONFIG_CMD_PING
 301 #define CONFIG_CMD_REGINFO
 302 #define CONFIG_CMD_SDRAM
 303 #define CONFIG_CMD_SOURCE
 304 #define CONFIG_CMD_USB
 305
 306 #define CONFIG_SUPPORT_VFAT
 307
 308 /*
 309  * Miscellaneous configurable options
 310  */
 311 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 312 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 313 #if defined(CONFIG_CMD_KGDB)
 314 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 315 #else
 316 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 317 #endif
 318 /* Print Buffer Size */
 319 #define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 320 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 321 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size  */
 322
 323 #define CONFIG_SYS_MEMTEST_START        0x00400000 /* memtest works on          */
 324 #define CONFIG_SYS_MEMTEST_END          0x3f000000 /* 4 ... < 1GB DRAM  */
 325
 326 #define CONFIG_SYS_LOAD_ADDR            0x100000  /* default load address       */
 327 #define CONFIG_SYS_EXTBDINFO            1       /* To use extended board_into (bd_t) */
 328
 329 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 330
 331 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 332 #define CONFIG_LOOPW            1       /* enable loopw command         */
 333 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 334 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 335 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 336
 337 #define CONFIG_AUTOBOOT_KEYED   1
 338 #define CONFIG_AUTOBOOT_PROMPT  \
 339         "Press SPACE to abort autoboot in %d seconds\n", bootdelay
 340 #define CONFIG_AUTOBOOT_DELAY_STR "d"
 341 #define CONFIG_AUTOBOOT_STOP_STR " "
 342
 343 /*
 344  * PCI stuff
 345  */
 346 #define CONFIG_PCI                      /* include pci support          */
 347 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 348 #define CONFIG_PCI_PNP                  /* do (not) pci plug-and-play   */
 349 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 350 #define CONFIG_SYS_PCI_TARGBASE       0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
 351
 352 /* Board-specific PCI */
 353 #define CONFIG_SYS_PCI_TARGET_INIT
 354 #define CONFIG_SYS_PCI_MASTER_INIT
 355
 356 /*
 357  * For booting Linux, the board info and command line data
 358  * have to be in the first 8 MB of memory, since this is
 359  * the maximum mapped by the Linux kernel during initialization.
 360  */
 361 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)     /* Initial Memory map for Linux */
 362
 363 /*
 364  * External Bus Controller (EBC) Setup
 365  */
 366 #define CONFIG_SYS_FLASH                CONFIG_SYS_FLASH_BASE
 367
 368 #define CONFIG_SYS_CPLD_BASE            0xC0000000
 369 #define CONFIG_SYS_CPLD_RANGE           0x00000010
 370 #define CONFIG_SYS_DUMEM_BASE           0xC0100000
 371 #define CONFIG_SYS_DUMEM_RANGE          0x00100000
 372 #define CONFIG_SYS_DUIO_BASE            0xC0200000
 373 #define CONFIG_SYS_DUIO_RANGE           0x00010000
 374
 375 #define CONFIG_SYS_NAND0_CS             2               /* NAND chip connected to CSx */
 376 #define CONFIG_SYS_NAND1_CS             3               /* NAND chip connected to CSx */
 377 /* Memory Bank 0 (NOR-FLASH) initialization */
 378 #define CONFIG_SYS_EBC_PB0AP            0x04017200
 379 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH_BASE | 0xda000)
 380
 381 /* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */
 382 #define CONFIG_SYS_EBC_PB1AP            0x018003c0
 383 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_CPLD_BASE | 0x18000)
 384
 385 /* Memory Bank 2 (NAND-FLASH) initialization */
 386 #define CONFIG_SYS_EBC_PB2AP            0x018003c0
 387 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_NAND0_ADDR | 0x1c000)
 388
 389 /* Memory Bank 3 (NAND-FLASH) initialization */
 390 #define CONFIG_SYS_EBC_PB3AP            0x018003c0
 391 #define CONFIG_SYS_EBC_PB3CR            (CONFIG_SYS_NAND1_ADDR | 0x1c000)
 392
 393 /* Memory Bank 4 (DUMEM, 1MB) initialization */
 394 #define CONFIG_SYS_EBC_PB4AP            0x018053c0
 395 #define CONFIG_SYS_EBC_PB4CR            (CONFIG_SYS_DUMEM_BASE | 0x18000)
 396
 397 /* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */
 398 #define CONFIG_SYS_EBC_PB5AP            0x018053c0
 399 #define CONFIG_SYS_EBC_PB5CR            (CONFIG_SYS_DUIO_BASE | 0x18000)
 400
 401 /*
 402  * NAND FLASH
 403  */
 404 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 405 #define CONFIG_SYS_NAND_SELECT_DEVICE  1        /* nand driver supports mutipl. chips */
 406 #define CONFIG_SYS_NAND_BASE_LIST       {CONFIG_SYS_NAND0_ADDR + CONFIG_SYS_NAND0_CS, \
 407                                  CONFIG_SYS_NAND1_ADDR + CONFIG_SYS_NAND1_CS}
 408
 409 #if defined(CONFIG_CMD_KGDB)
 410 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 411 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 412 #endif
 413
 414 #define CONFIG_SOURCE           1
 415
 416 #define CONFIG_OF_LIBFDT
 417 #define CONFIG_OF_BOARD_SETUP
 418
 419 #endif  /* __CONFIG_H */