include/configs/ELPPC.h

   1 /*
   2  * (C) Copyright 2002 ELTEC Elektronik AG
   3  * Frank Gottschling <fgottschling@eltec.de>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 #include <asm/processor.h>
  32
  33 #undef  DEBUG
  34 #define GTREGREAD(x) 0xffffffff         /* needed for debug */
  35
  36 /*
  37  * High Level Configuration Options
  38  * (easy to change)
  39  */
  40
  41 /* these hardware addresses are pretty bogus, please change them to
  42    suit your needs */
  43
  44 /* first ethernet */
  45 #define CONFIG_ETHADDR          00:00:5b:ee:de:ad
  46
  47 #define CONFIG_IPADDR           192.168.0.105
  48 #define CONFIG_SERVERIP         192.168.0.100
  49
  50 #define CONFIG_ELPPC            1       /* this is an BAB740/BAB750 board */
  51
  52 #define CONFIG_BAUDRATE         9600    /* console baudrate */
  53
  54 #undef  CONFIG_WATCHDOG
  55
  56 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
  57
  58 #define CONFIG_ZERO_BOOTDELAY_CHECK
  59
  60 #undef  CONFIG_BOOTARGS
  61 #define CONFIG_BOOTCOMMAND                                  \
  62     "bootp 1000000; "                                       \
  63     "setenv bootargs root=ramfs console=ttyS00,9600 "       \
  64     "ip=$(ipaddr):$(serverip):$(rootpath):$(gatewayip):"    \
  65     "$(netmask):$(hostname):eth0:none; "                    \
  66     "bootm"
  67
  68 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
  69 #define CFG_LOADS_BAUD_CHANGE           /* allow baudrate changes */
  70
  71 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  72
  73 #define CONFIG_COMMANDS         (CONFIG_CMD_DFL | CFG_CMD_PCI | CFG_CMD_JFFS2)
  74
  75 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  76 #include <cmd_confdefs.h>
  77
  78 /*
  79  * Miscellaneous configurable options
  80  */
  81 #define CFG_LONGHELP                    /* undef to save memory */
  82 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt */
  83
  84 /*
  85  * choose between COM1 and COM2 as serial console
  86  */
  87 #define CONFIG_CONS_INDEX       1
  88
  89 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  90 #define CFG_CBSIZE              1024        /* Console I/O Buffer Size */
  91 #else
  92 #define CFG_CBSIZE              256         /* Console I/O Buffer Size */
  93 #endif
  94 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
  95 #define CFG_MAXARGS             16          /* max number of command args    */
  96 #define CFG_BARGSIZE            CFG_CBSIZE  /* Boot Argument Buffer Size    */
  97
  98 #define CFG_MEMTEST_START       0x00000000  /* memtest works on    */
  99 #define CFG_MEMTEST_END         0x04000000  /* 0 ... 64 MB in DRAM    */
 100
 101 #define CFG_LOAD_ADDR           0x1000000   /* default load address    */
 102
 103 #define CFG_HZ                  1000        /* dec. freq: 1 ms ticks */
 104
 105 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 106
 107 /*
 108  * Low Level Configuration Settings
 109  * (address mappings, register initial values, etc.)
 110  * You should know what you are doing if you make changes here.
 111  */
 112 #define CFG_BOARD_ASM_INIT
 113 #define CONFIG_MISC_INIT_R
 114
 115 /*
 116  * Address mapping scheme for the MPC107 mem controller is mapping B (CHRP)
 117  */
 118 #undef  CFG_ADDRESS_MAP_A
 119
 120 #define CFG_PCI_MEMORY_BUS      0x00000000
 121 #define CFG_PCI_MEMORY_PHYS     0x00000000
 122 #define CFG_PCI_MEMORY_SIZE     0x40000000
 123
 124 #define CFG_PCI_MEM_BUS         0x80000000
 125 #define CFG_PCI_MEM_PHYS        0x80000000
 126 #define CFG_PCI_MEM_SIZE        0x7d000000
 127
 128 #define CFG_ISA_MEM_BUS         0x00000000
 129 #define CFG_ISA_MEM_PHYS        0xfd000000
 130 #define CFG_ISA_MEM_SIZE        0x01000000
 131
 132 #define CFG_PCI_IO_BUS          0x00800000
 133 #define CFG_PCI_IO_PHYS         0xfe800000
 134 #define CFG_PCI_IO_SIZE         0x00400000
 135
 136 #define CFG_ISA_IO_BUS          0x00000000
 137 #define CFG_ISA_IO_PHYS         0xfe000000
 138 #define CFG_ISA_IO_SIZE         0x00800000
 139
 140 /* driver defines FDC,IDE,... */
 141 #define CFG_ISA_IO_BASE_ADDRESS CFG_ISA_IO_PHYS
 142 #define CFG_ISA_IO              CFG_ISA_IO_PHYS
 143 #define CFG_60X_PCI_IO_OFFSET   CFG_ISA_IO_PHYS
 144
 145 /*
 146  * Start addresses for the final memory configuration
 147  * (Set up by the startup code)
 148  * Please note that CFG_SDRAM_BASE _must_ start at 0
 149  */
 150 #define CFG_SDRAM_BASE          0x00000000
 151
 152 #define CFG_USR_LED_BASE        0x78000000
 153 #define CFG_NVRAM_BASE          0xff000000
 154 #define CFG_UART_BASE           0xff400000
 155 #define CFG_FLASH_BASE          0xfff00000
 156
 157 #define MPC107_EUMB_ADDR        0xfce00000
 158 #define MPC107_EUMB_PI          0xfce41090
 159 #define MPC107_EUMB_GCR         0xfce41020
 160 #define MPC107_EUMB_IACKR       0xfce600a0
 161 #define MPC107_I2C_ADDR         0xfce03000
 162
 163 /*
 164  * Definitions for initial stack pointer and data area
 165  */
 166 #define CFG_INIT_RAM_ADDR       0x00fd0000  /* above the memtest region */
 167 #define CFG_INIT_RAM_END        0x4000
 168 #define CFG_GBL_DATA_SIZE       64          /* size in bytes reserved for init data */
 169 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 170 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 171
 172 /*
 173  * Flash mapping/organization on the MPC10x.
 174  */
 175 #define FLASH_BASE0_PRELIM      0xff800000
 176 #define FLASH_BASE1_PRELIM      0xffc00000
 177
 178 #define CFG_MAX_FLASH_BANKS     2           /* max number of memory banks    */
 179 #define CFG_MAX_FLASH_SECT      67          /* max number of sectors on one chip */
 180
 181 #define CFG_FLASH_ERASE_TOUT    120000      /* Timeout for Flash Erase (in ms) */
 182 #define CFG_FLASH_WRITE_TOUT    500         /* Timeout for Flash Write (in ms) */
 183
 184 #define CFG_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
 185 #define CFG_JFFS2_NUM_BANKS     2           /* ! second bank contains U-Boot */
 186
 187 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 188 #define CFG_MONITOR_LEN         0x40000     /* Reserve 256 kB for Monitor */
 189 #define CFG_MALLOC_LEN          0x20000     /* Reserve 128 kB for malloc() */
 190 #undef  CFG_MEMTEST
 191
 192 /*
 193  * Environment settings
 194  */
 195 #define CONFIG_ENV_OVERWRITE
 196 #define CFG_ENV_IS_IN_NVRAM     1           /* use NVRAM for environment vars */
 197 #define CFG_NVRAM_SIZE          0x800       /* NVRAM size (2kB) */
 198 #define CFG_ENV_SIZE            0x400       /* Size of Environment vars (1kB) */
 199 #define CFG_ENV_ADDR            0x0
 200 #define CFG_ENV_MAP_ADRS        0xff000000
 201 #define CFG_NV_SROM_COPY_ADDR   (CFG_ENV_ADDR + CFG_ENV_SIZE)
 202 #define CFG_NVRAM_ACCESS_ROUTINE            /* only byte accsess alowed */
 203 #define CFG_SROM_SIZE           0x100       /* shadow of revision info is in nvram */
 204
 205 /*
 206  * Serial devices
 207  */
 208 #define CFG_NS16550
 209 #define CFG_NS16550_SERIAL
 210 #define CFG_NS16550_REG_SIZE    1
 211 #define CFG_NS16550_CLK         24000000
 212 #define CFG_NS16550_COM1        (CFG_UART_BASE + 0)
 213 #define CFG_NS16550_COM2        (CFG_UART_BASE + 8)
 214
 215 /*
 216  * PCI stuff
 217  */
 218 #define CONFIG_PCI                                /* include pci support */
 219 #define CONFIG_PCI_PNP                            /* pci plug-and-play */
 220 #define CONFIG_PCI_HOST         PCI_HOST_AUTO
 221 #undef  CONFIG_PCI_SCAN_SHOW
 222
 223 /*
 224  * Optional Video console (graphic: SMI LynxEM)
 225  */
 226 #define CONFIG_VIDEO
 227 #define CONFIG_CFB_CONSOLE
 228 #define VIDEO_KBD_INIT_FCT    (simple_strtol (getenv("console"), NULL, 10))
 229 #define VIDEO_TSTC_FCT        serial_tstc
 230 #define VIDEO_GETC_FCT        serial_getc
 231
 232 #define CONFIG_VIDEO_SMI_LYNXEM
 233 #define CONFIG_VIDEO_LOGO
 234 #define CONFIG_CONSOLE_EXTRA_INFO
 235
 236 /*
 237  * Initial BATs
 238  */
 239 #if 1
 240
 241 #define CFG_IBAT0L 0
 242 #define CFG_IBAT0U 0
 243 #define CFG_DBAT0L CFG_IBAT1L
 244 #define CFG_DBAT0U CFG_IBAT1U
 245
 246 #define CFG_IBAT1L 0
 247 #define CFG_IBAT1U 0
 248 #define CFG_DBAT1L CFG_IBAT1L
 249 #define CFG_DBAT1U CFG_IBAT1U
 250
 251 #define CFG_IBAT2L 0
 252 #define CFG_IBAT2U 0
 253 #define CFG_DBAT2L CFG_IBAT2L
 254 #define CFG_DBAT2U CFG_IBAT2U
 255
 256 #define CFG_IBAT3L 0
 257 #define CFG_IBAT3U 0
 258 #define CFG_DBAT3L CFG_IBAT3L
 259 #define CFG_DBAT3U CFG_IBAT3U
 260
 261 #else
 262
 263 /* SDRAM */
 264 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_RW)
 265 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 266 #define CFG_DBAT0L CFG_IBAT1L
 267 #define CFG_DBAT0U CFG_IBAT1U
 268
 269 /* address range for flashes */
 270 #define CFG_IBAT1L (CFG_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
 271 #define CFG_IBAT1U (CFG_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
 272 #define CFG_DBAT1L CFG_IBAT1L
 273 #define CFG_DBAT1U CFG_IBAT1U
 274
 275 /* ISA IO space */
 276 #define CFG_IBAT2L (CFG_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
 277 #define CFG_IBAT2U (CFG_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
 278 #define CFG_DBAT2L CFG_IBAT2L
 279 #define CFG_DBAT2U CFG_IBAT2U
 280
 281 /* ISA memory space */
 282 #define CFG_IBAT3L (CFG_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
 283 #define CFG_IBAT3U (CFG_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
 284 #define CFG_DBAT3L CFG_IBAT3L
 285 #define CFG_DBAT3U CFG_IBAT3U
 286
 287 #endif
 288
 289 /*
 290  * Speed settings are board specific
 291  */
 292 #define CFG_BUS_HZ              100000000
 293 #define CFG_CPU_CLK             400000000
 294 #define CFG_BUS_CLK             CFG_BUS_HZ
 295
 296 /*
 297  * For booting Linux, the board info and command line data
 298  * have to be in the first 8 MB of memory, since this is
 299  * the maximum mapped by the Linux kernel during initialization.
 300  */
 301 #define CFG_BOOTMAPSZ           (8 << 20)           /* Initial Memory map for Linux */
 302
 303 /*
 304  * Cache Configuration
 305  */
 306 #define CFG_CACHELINE_SIZE        32    /* For all MPC74xx CPUs */
 307 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 308 #define CFG_CACHELINE_SHIFT        5    /* log base 2 of the above value */
 309 #endif
 310
 311 /*
 312  * L2CR setup -- make sure this is right for your board!
 313  * look in include/mpc74xx.h for the defines used here
 314  */
 315
 316 #define CFG_L2
 317
 318 #if 1
 319 #define L2_INIT     0       /* cpu 750 CXe*/
 320 #else
 321 #define L2_INIT     (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 322                      L2CR_L2OH_5   | L2CR_L2CTL | L2CR_L2WT)
 323 #endif
 324 #define L2_ENABLE   (L2_INIT | L2CR_L2E)
 325
 326 /*
 327  * Internal Definitions
 328  *
 329  * Boot Flags
 330  */
 331 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 332 #define BOOTFLAG_WARM           0x02    /* Software reboot */
 333
 334 #define CONFIG_NET_MULTI        /* Multi ethernet cards support */
 335 #define CONFIG_EEPRO100
 336 #define CONFIG_EEPRO100_SROM_WRITE
 337
 338 #endif    /* __CONFIG_H */