include/configs/EP88x.h

   1 /*
   2  * Copyright (C) 2005 Arabella Software Ltd.
   3  * Yuli Barcohen <yuli@arabellasw.com>
   4  *
   5  * Support for Embedded Planet EP88x boards.
   6  * Tested on EP88xC with MPC885 CPU, 64MB SDRAM and 16MB flash.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10 #ifndef __CONFIG_H
  11 #define __CONFIG_H
  12
  13 #define CONFIG_MPC885
  14
  15 #define CONFIG_EP88X                            /* Embedded Planet EP88x board  */
  16
  17 #define CONFIG_SYS_TEXT_BASE    0xFC000000
  18
  19 #define CONFIG_BOARD_EARLY_INIT_F               /* Call board_early_init_f      */
  20
  21 /* Allow serial number (serial#) and MAC address (ethaddr) to be overwritten */
  22 #define CONFIG_ENV_OVERWRITE
  23
  24 #define CONFIG_8xx_CONS_SMC1    1               /* Console is on SMC1           */
  25 #define CONFIG_BAUDRATE         38400
  26
  27 #define CONFIG_ETHER_ON_FEC1                    /* Enable Ethernet on FEC1      */
  28 #define CONFIG_ETHER_ON_FEC2                    /* Enable Ethernet on FEC2      */
  29 #if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2)
  30 #define CONFIG_SYS_DISCOVER_PHY
  31 #define CONFIG_MII_INIT         1
  32 #define FEC_ENET
  33 #endif /* CONFIG_FEC_ENET */
  34
  35 #define CONFIG_8xx_OSCLK                10000000 /* 10 MHz oscillator on EXTCLK */
  36 #define CONFIG_8xx_CPUCLK_DEFAULT       100000000
  37 #define CONFIG_SYS_8xx_CPUCLK_MIN               40000000
  38 #define CONFIG_SYS_8xx_CPUCLK_MAX               133000000
  39
  40 /*
  41  * BOOTP options
  42  */
  43 #define CONFIG_BOOTP_BOOTFILESIZE
  44 #define CONFIG_BOOTP_BOOTPATH
  45 #define CONFIG_BOOTP_GATEWAY
  46 #define CONFIG_BOOTP_HOSTNAME
  47
  48
  49 /*
  50  * Command line configuration.
  51  */
  52 #include <config_cmd_default.h>
  53
  54 #define CONFIG_CMD_DHCP
  55 #define CONFIG_CMD_IMMAP
  56 #define CONFIG_CMD_MII
  57 #define CONFIG_CMD_PING
  58
  59
  60 #define CONFIG_BOOTDELAY        5               /* Autoboot after 5 seconds     */
  61 #define CONFIG_BOOTCOMMAND      "bootm fe060000"        /* Autoboot command     */
  62 #define CONFIG_BOOTARGS         "root=/dev/mtdblock1 rw mtdparts=phys:2M(ROM)ro,-(root)"
  63
  64 #define CONFIG_BZIP2            /* Include support for bzip2 compressed images  */
  65 #undef  CONFIG_WATCHDOG         /* Disable platform specific watchdog           */
  66
  67 /*-----------------------------------------------------------------------
  68  * Miscellaneous configurable options
  69  */
  70 #define CONFIG_SYS_PROMPT               "=> "           /* Monitor Command Prompt       */
  71 #define CONFIG_SYS_HUSH_PARSER
  72 #define CONFIG_SYS_LONGHELP                             /* #undef to save memory        */
  73 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
  74 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)  /* Print Buffer Size */
  75 #define CONFIG_SYS_MAXARGS              16              /* Max number of command args   */
  76 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
  77
  78 #define CONFIG_SYS_LOAD_ADDR            0x400000        /* Default load address         */
  79
  80 #define CONFIG_SYS_HZ                   1000            /* Decrementer freq: 1 ms ticks */
  81
  82 /*-----------------------------------------------------------------------
  83  * RAM configuration (note that CONFIG_SYS_SDRAM_BASE must be zero)
  84  */
  85 #define CONFIG_SYS_SDRAM_BASE           0x00000000
  86 #define CONFIG_SYS_SDRAM_MAX_SIZE       0x08000000      /* Up to 128 Mbyte              */
  87
  88 #define CONFIG_SYS_MAMR         0x00805000
  89
  90 /*
  91  * 4096 Up to 4096 SDRAM rows
  92  * 1000 factor s -> ms
  93  * 32   PTP (pre-divider from MPTPR)
  94  * 4    Number of refresh cycles per period
  95  * 64   Refresh cycle in ms per number of rows
  96  */
  97 #define CONFIG_SYS_PTA_PER_CLK          ((4096 * 32 * 1000) / (4 * 64))
  98
  99 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on             */
 100 #define CONFIG_SYS_MEMTEST_END          0x00500000      /* 1 ... 5 MB in SDRAM          */
 101
 102 #define CONFIG_SYS_RESET_ADDRESS        0x09900000
 103
 104 /*-----------------------------------------------------------------------
 105  * For booting Linux, the board info and command line data
 106  * have to be in the first 8 MB of memory, since this is
 107  * the maximum mapped by the Linux kernel during initialization.
 108  */
 109 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 110
 111 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 112 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 KB for Monitor   */
 113 #ifdef CONFIG_BZIP2
 114 #define CONFIG_SYS_MALLOC_LEN           (4096 << 10)    /* Reserve ~4 MB for malloc()   */
 115 #else
 116 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 KB for malloc()  */
 117 #endif /* CONFIG_BZIP2 */
 118
 119 /*-----------------------------------------------------------------------
 120  * Flash organisation
 121  */
 122 #define CONFIG_SYS_FLASH_BASE           0xFC000000
 123 #define CONFIG_SYS_FLASH_CFI                            /* The flash is CFI compatible  */
 124 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
 125 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* Max number of flash banks    */
 126 #define CONFIG_SYS_MAX_FLASH_SECT       512             /* Max num of sects on one chip */
 127
 128 /* Environment is in flash */
 129 #define CONFIG_ENV_IS_IN_FLASH
 130 #define CONFIG_ENV_SECT_SIZE    0x20000         /* We use one complete sector   */
 131 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 132
 133 #define CONFIG_SYS_OR0_PRELIM           0xFC000160
 134 #define CONFIG_SYS_BR0_PRELIM           (CONFIG_SYS_FLASH_BASE | BR_PS_32 | BR_MS_GPCM | BR_V)
 135
 136 #define CONFIG_SYS_DIRECT_FLASH_TFTP
 137
 138 /*-----------------------------------------------------------------------
 139  * BCSR
 140  */
 141 #define CONFIG_SYS_OR3_PRELIM           0xFF0005B0
 142 #define CONFIG_SYS_BR3_PRELIM           (0xFA000000 |BR_PS_16 | BR_MS_GPCM | BR_V)
 143
 144 #define CONFIG_SYS_BCSR         0xFA400000
 145
 146 /*-----------------------------------------------------------------------
 147  * Internal Memory Map Register
 148  */
 149 #define CONFIG_SYS_IMMR         0xF0000000
 150
 151 /*-----------------------------------------------------------------------
 152  * Definitions for initial stack pointer and data area (in DPRAM)
 153  */
 154 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 155 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00          /* Size of used area in DPRAM   */
 156 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 157 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 158
 159 /*-----------------------------------------------------------------------
 160  * Configuration registers
 161  */
 162 #ifdef CONFIG_WATCHDOG
 163 #define CONFIG_SYS_SYPCR                (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
 164                                  SYPCR_SWF  | SYPCR_SWE | SYPCR_SWRI | \
 165                                  SYPCR_SWP)
 166 #else
 167 #define CONFIG_SYS_SYPCR                (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME  | \
 168                                  SYPCR_SWF  | SYPCR_SWP)
 169 #endif /* CONFIG_WATCHDOG */
 170
 171 #define CONFIG_SYS_SIUMCR               (SIUMCR_MLRC01 | SIUMCR_DBGC11)
 172
 173 /* TBSCR - Time Base Status and Control Register */
 174 #define CONFIG_SYS_TBSCR                (TBSCR_TBF | TBSCR_TBE)
 175
 176 /* PISCR - Periodic Interrupt Status and Control */
 177 #define CONFIG_SYS_PISCR                PISCR_PS
 178
 179 /* SCCR - System Clock and reset Control Register */
 180 #define SCCR_MASK               SCCR_EBDF11
 181 #define CONFIG_SYS_SCCR         SCCR_RTSEL
 182
 183 #define CONFIG_SYS_DER                  0
 184
 185 /*-----------------------------------------------------------------------
 186  * Cache Configuration
 187  */
 188 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx chips                 */
 189
 190 #endif /* __CONFIG_H */