include/configs/EVB64260.h

   1 /*
   2  * (C) Copyright 2001
   3  * Josh Huber <huber@mclx.com>, Mission Critical Linux, Inc.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 #ifndef __ASSEMBLY__
  32 #include <galileo/core.h>
  33 #endif
  34
  35 #include "../board/evb64260/local.h"
  36
  37 /*
  38  * High Level Configuration Options
  39  * (easy to change)
  40  */
  41
  42 #define CONFIG_EVB64260         1       /* this is an EVB64260 board    */
  43 #define CFG_GT_6426x        GT_64260 /* with a 64260 system controller */
  44
  45 #define CONFIG_BAUDRATE         38400   /* console baudrate = 38400     */
  46
  47 #undef  CONFIG_ECC                      /* enable ECC support */
  48 /* #define CONFIG_EVB64260_750CX  1 */      /* Support the EVB-64260-750CX Board */
  49
  50 /* which initialization functions to call for this board */
  51 #define CONFIG_MISC_INIT_R      1
  52 #define CONFIG_BOARD_EARLY_INIT_F 1
  53
  54 #ifndef CONFIG_EVB64260_750CX
  55 #define CFG_BOARD_NAME          "EVB64260"
  56 #else
  57 #define CFG_BOARD_NAME         "EVB64260-750CX"
  58 #endif
  59
  60 #define CFG_HUSH_PARSER
  61 #define CFG_PROMPT_HUSH_PS2     "> "
  62
  63 /*
  64  * The following defines let you select what serial you want to use
  65  * for your console driver.
  66  *
  67  * what to do:
  68  * to use the DUART, undef CONFIG_MPSC.  If you have hacked a serial
  69  * cable onto the second DUART channel, change the CFG_DUART port from 1
  70  * to 0 below.
  71  *
  72  * to use the MPSC, #define CONFIG_MPSC.  If you have wired up another
  73  * mpsc channel, change CONFIG_MPSC_PORT to the desired value.
  74  */
  75 #define CONFIG_MPSC
  76 #define CONFIG_MPSC_PORT        0
  77
  78 #define CONFIG_NET_MULTI        /* attempt all available adapters */
  79
  80 /* define this if you want to enable GT MAC filtering */
  81 #define CONFIG_GT_USE_MAC_HASH_TABLE
  82
  83 #undef CONFIG_ETHER_PORT_MII    /* use RMII */
  84
  85 #if 1
  86 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  87 #else
  88 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  89 #endif
  90 #define CONFIG_ZERO_BOOTDELAY_CHECK
  91
  92 #undef  CONFIG_BOOTARGS
  93 #define CONFIG_BOOTCOMMAND                                                   \
  94         "bootp && "                                                  \
  95         "setenv bootargs root=/dev/nfs rw nfsroot=$serverip:$rootpath " \
  96         "ip=$ipaddr:$serverip:$gatewayip:" \
  97         "$netmask:$hostname:eth0:none; && " \
  98         "bootm"
  99
 100 #define CONFIG_LOADS_ECHO       0       /* echo off for serial download */
 101 #define CFG_LOADS_BAUD_CHANGE           /* allow baudrate changes       */
 102
 103 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 104 #undef  CONFIG_ALTIVEC                  /* undef to disable             */
 105
 106 /*
 107  * BOOTP options
 108  */
 109 #define CONFIG_BOOTP_SUBNETMASK
 110 #define CONFIG_BOOTP_GATEWAY
 111 #define CONFIG_BOOTP_HOSTNAME
 112 #define CONFIG_BOOTP_BOOTPATH
 113 #define CONFIG_BOOTP_BOOTFILESIZE
 114
 115
 116 /*
 117  * Command line configuration.
 118  */
 119 #include <config_cmd_default.h>
 120
 121 #define CONFIG_CMD_ASKENV
 122
 123
 124 /*
 125  * Miscellaneous configurable options
 126  */
 127 #define CFG_LONGHELP                    /* undef to save memory         */
 128 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 129 #if defined(CONFIG_CMD_KGDB)
 130 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 131 #else
 132 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 133 #endif
 134 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 135 #define CFG_MAXARGS     16              /* max number of command args   */
 136 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 137
 138 #define CFG_MEMTEST_START       0x00400000      /* memtest works on     */
 139 #define CFG_MEMTEST_END         0x00C00000      /* 4 ... 12 MB in DRAM  */
 140
 141 #define CFG_LOAD_ADDR           0x00300000      /* default load address */
 142
 143 #define CFG_HZ                  1000            /* decr freq: 1ms ticks */
 144 #define CFG_BUS_HZ              100000000       /* 100 MHz              */
 145 #define CFG_BUS_CLK             CFG_BUS_HZ
 146
 147 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 148
 149 #ifdef CONFIG_EVB64260_750CX
 150 #define CONFIG_750CX
 151 #define CFG_BROKEN_CL2
 152 #endif
 153
 154 /*
 155  * Low Level Configuration Settings
 156  * (address mappings, register initial values, etc.)
 157  * You should know what you are doing if you make changes here.
 158  */
 159
 160 /*-----------------------------------------------------------------------
 161  * Definitions for initial stack pointer and data area
 162  */
 163 #define CFG_INIT_RAM_ADDR       0x40000000
 164 #define CFG_INIT_RAM_END        0x1000
 165 #define CFG_GBL_DATA_SIZE       128  /* size in bytes reserved for init data */
 166 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 167 #define CFG_INIT_RAM_LOCK
 168
 169
 170 /*-----------------------------------------------------------------------
 171  * Start addresses for the final memory configuration
 172  * (Set up by the startup code)
 173  * Please note that CFG_SDRAM_BASE _must_ start at 0
 174  */
 175 #define CFG_SDRAM_BASE          0x00000000
 176 #define CFG_FLASH_BASE          0xfff00000
 177 #define CFG_RESET_ADDRESS       0xfff00100
 178 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor */
 179 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 180 #define CFG_MALLOC_LEN          (256 << 10)     /* Reserve 256 kB for malloc */
 181
 182 /* areas to map different things with the GT in physical space */
 183 #define CFG_DRAM_BANKS          4
 184 #define CFG_DFL_GT_REGS         0x14000000      /* boot time GT_REGS */
 185
 186 /* What to put in the bats. */
 187 #define CFG_MISC_REGION_BASE    0xf0000000
 188
 189 /* Peripheral Device section */
 190 #define CFG_GT_REGS             0xf8000000
 191 #define CFG_DEV_BASE            0xfc000000
 192
 193 #define CFG_DEV0_SPACE          CFG_DEV_BASE
 194 #define CFG_DEV1_SPACE          (CFG_DEV0_SPACE + CFG_DEV0_SIZE)
 195 #define CFG_DEV2_SPACE          (CFG_DEV1_SPACE + CFG_DEV1_SIZE)
 196 #define CFG_DEV3_SPACE          (CFG_DEV2_SPACE + CFG_DEV2_SIZE)
 197
 198 #define CFG_DEV0_SIZE            _8M /* evb64260 sram  @ 0xfc00.0000 */
 199 #define CFG_DEV1_SIZE            _8M /* evb64260 rtc   @ 0xfc80.0000 */
 200 #define CFG_DEV2_SIZE           _16M /* evb64260 duart @ 0xfd00.0000 */
 201 #define CFG_DEV3_SIZE           _16M /* evb64260 flash @ 0xfe00.0000 */
 202
 203 #define CFG_DEV0_PAR            0x20205093
 204 #define CFG_DEV1_PAR            0xcfcfffff
 205 #define CFG_DEV2_PAR            0xc0059bd4
 206 #define CFG_8BIT_BOOT_PAR       0xc00b5e7c
 207 #define CFG_32BIT_BOOT_PAR      0xc4a8241c
 208         /*   c    4    a      8     2     4    1      c         */
 209         /* 33 22|2222|22 22|111 1|11 11|1 1  |    |             */
 210         /* 10 98|7654|32 10|987 6|54 32|1 098|7 654|3 210       */
 211         /* 11|00|0100|10 10|100|0 00|10 0|100 0|001 1|100       */
 212         /*  3| 0|.... ..| 2| 4 |  0 |  4 |  8  |  3  | 4        */
 213
 214 #if 0 /* Wrong?? NTL */
 215 #define CFG_MPP_CONTROL_0       0x53541717      /* InitAct EOT[4] DBurst TCEn[1] */
 216                                                 /* DMAAck[1:0] GNT0[1:0] */
 217 #else
 218 #define CFG_MPP_CONTROL_0       0x53547777      /* InitAct EOT[4] DBurst TCEn[1] */
 219                                                 /* REQ0[1:0] GNT0[1:0] */
 220 #endif
 221 #define CFG_MPP_CONTROL_1       0x44009911      /* TCEn[4] TCTcnt[4] GPP[13:12] */
 222                                                 /* DMAReq[4] DMAAck[4] WDNMI WDE */
 223 #if 0 /* Wrong?? NTL */
 224 #define CFG_MPP_CONTROL_2       0x40091818      /* TCTcnt[0] GPP[22:21] BClkIn */
 225                                                 /* DMAAck[1:0] GNT1[1:0] */
 226 #else
 227 #define CFG_MPP_CONTROL_2       0x40098888      /* TCTcnt[0] */
 228                                                 /* GPP[22] (RS232IntB or PCI1Int) */
 229                                                 /* GPP[21] (RS323IntA) */
 230                                                 /* BClkIn */
 231                                                 /* REQ1[1:0] GNT1[1:0] */
 232 #endif
 233
 234 #if 0 /* Wrong?? NTL */
 235 # define CFG_MPP_CONTROL_3      0x00090066      /* GPP[31:29] BClkOut0 */
 236                                                 /* GPP[27:26] Int[1:0] */
 237 #else
 238 # define CFG_MPP_CONTROL_3      0x22090066      /* MREQ MGNT */
 239                                                 /* GPP[29]    (PCI1Int) */
 240                                                 /* BClkOut0 */
 241                                                 /* GPP[27]    (PCI0Int) */
 242                                                 /* GPP[26]    (RtcInt or PCI1Int) */
 243                                                 /* CPUInt[25:24] */
 244 #endif
 245
 246 # define CFG_SERIAL_PORT_MUX    0x00000102      /* 0=hiZ  1=MPSC0 2=ETH 0 and 2 RMII */
 247
 248 #if 0 /* Wrong?? - NTL */
 249 # define CFG_GPP_LEVEL_CONTROL  0x000002c6
 250 #else
 251 # define CFG_GPP_LEVEL_CONTROL  0x2c600000      /* 0010 1100 0110 0000 */
 252                                                 /* gpp[29] */
 253                                                 /* gpp[27:26] */
 254                                                 /* gpp[22:21] */
 255
 256 # define CFG_SDRAM_CONFIG       0xd8e18200      /* 0x448 */
 257                                 /* idmas use buffer 1,1
 258                                    comm use buffer 0
 259                                    pci use buffer 1,1
 260                                    cpu use buffer 0
 261                                    normal load (see also ifdef HVL)
 262                                    standard SDRAM (see also ifdef REG)
 263                                    non staggered refresh */
 264                                 /* 31:26  25 23  20 19 18 16 */
 265                                 /* 110110 00 111 0  0  00 1 */
 266                                 /* refresh_count=0x200
 267                                    phisical interleaving disable
 268                                    virtual interleaving enable */
 269                                 /* 15 14 13:0 */
 270                                 /* 1  0  0x200 */
 271 #endif
 272
 273 #define CFG_DUART_IO            CFG_DEV2_SPACE
 274 #define CFG_DUART_CHAN          1               /* channel to use for console */
 275 #define CFG_INIT_CHAN1
 276 #define CFG_INIT_CHAN2
 277
 278 #define SRAM_BASE               CFG_DEV0_SPACE
 279 #define SRAM_SIZE               0x00100000              /* 1 MB of sram */
 280
 281
 282 /*-----------------------------------------------------------------------
 283  * PCI stuff
 284  *-----------------------------------------------------------------------
 285  */
 286
 287 #define PCI_HOST_ADAPTER 0              /* configure ar pci adapter     */
 288 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 289 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 290
 291 #define CONFIG_PCI                      /* include pci support          */
 292 #define CONFIG_PCI_HOST PCI_HOST_FORCE  /* select pci host function     */
 293 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 294
 295 /* PCI MEMORY MAP section */
 296 #define CFG_PCI0_MEM_BASE       0x80000000
 297 #define CFG_PCI0_MEM_SIZE       _128M
 298 #define CFG_PCI1_MEM_BASE       0x88000000
 299 #define CFG_PCI1_MEM_SIZE       _128M
 300
 301 #define CFG_PCI0_0_MEM_SPACE    (CFG_PCI0_MEM_BASE)
 302 #define CFG_PCI1_0_MEM_SPACE    (CFG_PCI1_MEM_BASE)
 303
 304
 305 /* PCI I/O MAP section */
 306 #define CFG_PCI0_IO_BASE        0xfa000000
 307 #define CFG_PCI0_IO_SIZE        _16M
 308 #define CFG_PCI1_IO_BASE        0xfb000000
 309 #define CFG_PCI1_IO_SIZE        _16M
 310
 311 #define CFG_PCI0_IO_SPACE       (CFG_PCI0_IO_BASE)
 312 #define CFG_PCI0_IO_SPACE_PCI   0x00000000
 313 #define CFG_PCI1_IO_SPACE       (CFG_PCI1_IO_BASE)
 314 #define CFG_PCI1_IO_SPACE_PCI   0x00000000
 315
 316 /*
 317  * NS16550 Configuration
 318  */
 319 #define CFG_NS16550
 320
 321 #define CFG_NS16550_REG_SIZE    -4
 322
 323 #define CFG_NS16550_CLK         3686400
 324
 325 #define CFG_NS16550_COM1        (CFG_DUART_IO + 0)
 326 #define CFG_NS16550_COM2        (CFG_DUART_IO + 0x20)
 327
 328 /*----------------------------------------------------------------------
 329  * Initial BAT mappings
 330  */
 331
 332 /* NOTES:
 333  * 1) GUARDED and WRITE_THRU not allowed in IBATS
 334  * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
 335  */
 336
 337 /* SDRAM */
 338 #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
 339 #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 340 #define CFG_DBAT0L (CFG_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 341 #define CFG_DBAT0U CFG_IBAT0U
 342
 343 /* init ram */
 344 #define CFG_IBAT1L  (CFG_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
 345 #define CFG_IBAT1U  (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 346 #define CFG_DBAT1L  CFG_IBAT1L
 347 #define CFG_DBAT1U  CFG_IBAT1U
 348
 349 /* PCI0, PCI1 in one BAT */
 350 #define CFG_IBAT2L BATL_NO_ACCESS
 351 #define CFG_IBAT2U CFG_DBAT2U
 352 #define CFG_DBAT2L (CFG_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 353 #define CFG_DBAT2U (CFG_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 354
 355 /* GT regs, bootrom, all the devices, PCI I/O */
 356 #define CFG_IBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
 357 #define CFG_IBAT3U (CFG_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
 358 #define CFG_DBAT3L (CFG_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
 359 #define CFG_DBAT3U CFG_IBAT3U
 360
 361 /* I2C speed and slave address (for compatability) defaults */
 362 #define CFG_I2C_SPEED   400000
 363 #define CFG_I2C_SLAVE   0x7F
 364
 365 /* I2C addresses for the two DIMM SPD chips */
 366 #ifndef CONFIG_EVB64260_750CX
 367 #define DIMM0_I2C_ADDR  0x56
 368 #define DIMM1_I2C_ADDR  0x54
 369 #else /* CONFIG_EVB64260_750CX - only has 1 DIMM */
 370 #define DIMM0_I2C_ADDR  0x54
 371 #define DIMM1_I2C_ADDR  0x54
 372 #endif
 373
 374 /*
 375  * For booting Linux, the board info and command line data
 376  * have to be in the first 8 MB of memory, since this is
 377  * the maximum mapped by the Linux kernel during initialization.
 378  */
 379 #define CFG_BOOTMAPSZ           (8<<20) /* Initial Memory map for Linux */
 380
 381 /*-----------------------------------------------------------------------
 382  * FLASH organization
 383  */
 384 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks   */
 385 #define CFG_MAX_FLASH_SECT      67      /* max number of sectors on one chip */
 386
 387 #define CFG_EXTRA_FLASH_DEVICE  DEVICE3 /* extra flash at device 3 */
 388 #define CFG_EXTRA_FLASH_WIDTH   4       /* 32 bit */
 389
 390 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms) */
 391 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms) */
 392 #define CFG_FLASH_CFI           1
 393
 394 #define CFG_ENV_IS_IN_FLASH     1
 395 #define CFG_ENV_SIZE            0x1000  /* Total Size of Environment Sector */
 396 #define CFG_ENV_SECT_SIZE       0x10000
 397 #define CFG_ENV_ADDR    (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE)
 398
 399 /*-----------------------------------------------------------------------
 400  * Cache Configuration
 401  */
 402 #define CFG_CACHELINE_SIZE      32      /* For all MPC74xx CPUs          */
 403 #if defined(CONFIG_CMD_KGDB)
 404 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 405 #endif
 406
 407 /*-----------------------------------------------------------------------
 408  * L2CR setup -- make sure this is right for your board!
 409  * look in include/74xx_7xx.h for the defines used here
 410  */
 411
 412 #define CFG_L2
 413
 414 #ifdef CONFIG_750CX
 415 #define L2_INIT         0
 416 #else
 417 #define L2_INIT         (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
 418                          L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
 419 #endif
 420
 421 #define L2_ENABLE       (L2_INIT | L2CR_L2E)
 422
 423 /*
 424  * Internal Definitions
 425  *
 426  * Boot Flags
 427  */
 428 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH */
 429 #define BOOTFLAG_WARM   0x02            /* Software reboot                  */
 430
 431 #define CFG_BOARD_ASM_INIT      1
 432
 433
 434 #endif  /* __CONFIG_H */