include/configs/FPS850L.h

   1 /*
   2  * (C) Copyright 2000
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC850           1       /* This is a MPC850 CPU         */
  37 #define CONFIG_FPS850L          1       /* ...on a FingerPrint Sensor   */
  38
  39 #undef  CONFIG_8xx_CONS_SMC1
  40 #define CONFIG_8xx_CONS_SMC2    1       /* Console is on SMC2           */
  41 #undef  CONFIG_8xx_CONS_NONE
  42 #define CONFIG_BAUDRATE         115200
  43
  44 #define CONFIG_BOOTCOUNT_LIMIT
  45
  46 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  47
  48 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  49
  50 #define CONFIG_PREBOOT  "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
  51
  52 #undef  CONFIG_BOOTARGS
  53
  54 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  55         "netdev=eth0\0"                                                 \
  56         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  57                 "nfsroot=${serverip}:${rootpath}\0"                     \
  58         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  59         "addip=setenv bootargs ${bootargs} "                            \
  60                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  61                 ":${hostname}:${netdev}:off panic=1\0"                  \
  62         "flash_nfs=run nfsargs addip;"                                  \
  63                 "bootm ${kernel_addr}\0"                                \
  64         "flash_self=run ramargs addip;"                                 \
  65                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  66         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  67         "rootpath=/opt/eldk/ppc_8xx\0"                                  \
  68         "bootfile=/tftpboot/fps850L/uImage\0"                           \
  69         "fdt_addr=40040000\0"                                           \
  70         "kernel_addr=40060000\0"                                        \
  71         "ramdisk_addr=40200000\0"                                       \
  72         ""
  73 #define CONFIG_BOOTCOMMAND      "run flash_self"
  74
  75 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  76 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  77
  78 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  79
  80 /*
  81  * BOOTP options
  82  */
  83 #define CONFIG_BOOTP_SUBNETMASK
  84 #define CONFIG_BOOTP_GATEWAY
  85 #define CONFIG_BOOTP_HOSTNAME
  86 #define CONFIG_BOOTP_BOOTPATH
  87 #define CONFIG_BOOTP_BOOTFILESIZE
  88 #define CONFIG_BOOTP_SUBNETMASK
  89 #define CONFIG_BOOTP_GATEWAY
  90 #define CONFIG_BOOTP_HOSTNAME
  91 #define CONFIG_BOOTP_NISDOMAIN
  92 #define CONFIG_BOOTP_BOOTPATH
  93 #define CONFIG_BOOTP_DNS
  94 #define CONFIG_BOOTP_DNS2
  95 #define CONFIG_BOOTP_SEND_HOSTNAME
  96 #define CONFIG_BOOTP_NTPSERVER
  97 #define CONFIG_BOOTP_TIMEOFFSET
  98
  99 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
 100
 101 /*
 102  * Command line configuration.
 103  */
 104 #include <config_cmd_default.h>
 105
 106 #define CONFIG_CMD_ASKENV
 107 #define CONFIG_CMD_DATE
 108 #define CONFIG_CMD_DHCP
 109 #define CONFIG_CMD_NFS
 110 #define CONFIG_CMD_SNTP
 111
 112
 113 /*
 114  * Miscellaneous configurable options
 115  */
 116 #define CFG_LONGHELP                    /* undef to save memory         */
 117 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 118
 119 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 120 #define CFG_HUSH_PARSER         1       /* Use the HUSH parser          */
 121 #ifdef  CFG_HUSH_PARSER
 122 #define CFG_PROMPT_HUSH_PS2     "> "
 123 #endif
 124
 125 #if defined(CONFIG_CMD_KGDB)
 126 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 127 #else
 128 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 129 #endif
 130 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 131 #define CFG_MAXARGS     16              /* max number of command args   */
 132 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 133
 134 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 135 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 136
 137 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 138
 139 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 140
 141 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 142
 143 /*
 144  * Low Level Configuration Settings
 145  * (address mappings, register initial values, etc.)
 146  * You should know what you are doing if you make changes here.
 147  */
 148 /*-----------------------------------------------------------------------
 149  * Internal Memory Mapped Register
 150  */
 151 #define CFG_IMMR                0xFFF00000
 152
 153 /*-----------------------------------------------------------------------
 154  * Definitions for initial stack pointer and data area (in DPRAM)
 155  */
 156 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 157 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 158 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 159 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 160 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 161
 162 /*-----------------------------------------------------------------------
 163  * Start addresses for the final memory configuration
 164  * (Set up by the startup code)
 165  * Please note that CFG_SDRAM_BASE _must_ start at 0
 166  */
 167 #define CFG_SDRAM_BASE          0x00000000
 168 #define CFG_FLASH_BASE          0x40000000
 169 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 170 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 171 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 172
 173 /*
 174  * For booting Linux, the board info and command line data
 175  * have to be in the first 8 MB of memory, since this is
 176  * the maximum mapped by the Linux kernel during initialization.
 177  */
 178 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 179
 180 /*-----------------------------------------------------------------------
 181  * FLASH organization
 182  */
 183 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 184 #define CFG_MAX_FLASH_SECT      71      /* max number of sectors on one chip    */
 185
 186 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 187 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 188
 189 #define CFG_ENV_IS_IN_FLASH     1
 190 #define CFG_ENV_OFFSET          0x8000  /*   Offset   of Environment Sector     */
 191 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 192
 193 /* Address and size of Redundant Environment Sector     */
 194 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SIZE)
 195 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 196
 197 /*-----------------------------------------------------------------------
 198  * Hardware Information Block
 199  */
 200 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 201 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 202 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 203
 204 /*-----------------------------------------------------------------------
 205  * Cache Configuration
 206  */
 207 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 208 #if defined(CONFIG_CMD_KGDB)
 209 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 210 #endif
 211
 212 /*-----------------------------------------------------------------------
 213  * SYPCR - System Protection Control                            11-9
 214  * SYPCR can only be written once after reset!
 215  *-----------------------------------------------------------------------
 216  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 217  */
 218 #if defined(CONFIG_WATCHDOG)
 219 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 220                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 221 #else
 222 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 223 #endif
 224
 225 /*-----------------------------------------------------------------------
 226  * SIUMCR - SIU Module Configuration                            11-6
 227  *-----------------------------------------------------------------------
 228  * PCMCIA config., multi-function pin tri-state
 229  */
 230 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
 231
 232 /*-----------------------------------------------------------------------
 233  * TBSCR - Time Base Status and Control                         11-26
 234  *-----------------------------------------------------------------------
 235  * Clear Reference Interrupt Status, Timebase freezing enabled
 236  */
 237 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 238
 239 /*-----------------------------------------------------------------------
 240  * RTCSC - Real-Time Clock Status and Control Register          11-27
 241  *-----------------------------------------------------------------------
 242  */
 243 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 244
 245 /*-----------------------------------------------------------------------
 246  * PISCR - Periodic Interrupt Status and Control                11-31
 247  *-----------------------------------------------------------------------
 248  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 249  */
 250 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 251
 252 /*-----------------------------------------------------------------------
 253  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 254  *-----------------------------------------------------------------------
 255  * Reset PLL lock status sticky bit, timer expired status bit and timer
 256  * interrupt status bit - leave PLL multiplication factor unchanged !
 257  */
 258 #define CFG_PLPRCR      (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST)
 259
 260 /*-----------------------------------------------------------------------
 261  * SCCR - System Clock and reset Control Register               15-27
 262  *-----------------------------------------------------------------------
 263  * Set clock output, timebase and RTC source and divider,
 264  * power management and some other internal clocks
 265  */
 266 #define SCCR_MASK       SCCR_EBDF11
 267 #define CFG_SCCR        (SCCR_TBS     | \
 268                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 269                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 270                          SCCR_DFALCD00)
 271
 272 /*-----------------------------------------------------------------------
 273  * PCMCIA stuff
 274  *-----------------------------------------------------------------------
 275  *
 276  */
 277 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 278 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 279 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 280 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 281 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 282 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 283 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 284 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 285
 286 /*-----------------------------------------------------------------------
 287  *
 288  *-----------------------------------------------------------------------
 289  *
 290  */
 291 #define CFG_DER 0
 292
 293 /*
 294  * Init Memory Controller:
 295  *
 296  * BR0/1 and OR0/1 (FLASH)
 297  */
 298
 299 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 300 #define FLASH_BASE1_PRELIM      0x60000000      /* FLASH bank #0        */
 301
 302 /* used to re-map FLASH both when starting from SRAM or FLASH:
 303  * restrict access enough to keep SRAM working (if any)
 304  * but not too much to meddle with FLASH accesses
 305  */
 306 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 307 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 308
 309 /*
 310  * FLASH timing:
 311  */
 312 #define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 313                                  OR_SCY_3_CLK | OR_EHTR | OR_BI)
 314
 315 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 316 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 317 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
 318
 319 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 320 #define CFG_OR1_PRELIM  CFG_OR0_PRELIM
 321 #define CFG_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V )
 322
 323 /*
 324  * BR2/3 and OR2/3 (SDRAM)
 325  *
 326  */
 327 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank #0        */
 328 #define SDRAM_BASE3_PRELIM      0x20000000      /* SDRAM bank #1        */
 329 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB per bank   */
 330
 331 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 332 #define CFG_OR_TIMING_SDRAM     0x00000A00
 333
 334 #define CFG_OR2_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
 335 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 336
 337 #define CFG_OR3_PRELIM  CFG_OR2_PRELIM
 338 #define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 339
 340 /*
 341  * Memory Periodic Timer Prescaler
 342  *
 343  * The Divider for PTA (refresh timer) configuration is based on an
 344  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 345  * the number of chip selects (NCS) and the actually needed refresh
 346  * rate is done by setting MPTPR.
 347  *
 348  * PTA is calculated from
 349  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 350  *
 351  *      gclk      CPU clock (not bus clock!)
 352  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 353  *
 354  * 4096  Rows from SDRAM example configuration
 355  * 1000  factor s -> ms
 356  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 357  *    4  Number of refresh cycles per period
 358  *   64  Refresh cycle in ms per number of rows
 359  * --------------------------------------------
 360  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 361  *
 362  * 50 MHz => 50.000.000 / Divider =  98
 363  * 66 Mhz => 66.000.000 / Divider = 129
 364  * 80 Mhz => 80.000.000 / Divider = 156
 365  */
 366
 367 #define CFG_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64))
 368 #define CFG_MAMR_PTA    98
 369
 370 /*
 371  * For 16 MBit, refresh rates could be 31.3 us
 372  * (= 64 ms / 2K = 125 / quad bursts).
 373  * For a simpler initialization, 15.6 us is used instead.
 374  *
 375  * #define CFG_MPTPR_2BK_2K     MPTPR_PTP_DIV32         for 2 banks
 376  * #define CFG_MPTPR_1BK_2K     MPTPR_PTP_DIV64         for 1 bank
 377  */
 378 #define CFG_MPTPR_2BK_4K        MPTPR_PTP_DIV16         /* setting for 2 banks  */
 379 #define CFG_MPTPR_1BK_4K        MPTPR_PTP_DIV32         /* setting for 1 bank   */
 380
 381 /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit         */
 382 #define CFG_MPTPR_2BK_8K        MPTPR_PTP_DIV8          /* setting for 2 banks  */
 383 #define CFG_MPTPR_1BK_8K        MPTPR_PTP_DIV16         /* setting for 1 bank   */
 384
 385 /*
 386  * MAMR settings for SDRAM
 387  */
 388
 389 /* 8 column SDRAM */
 390 #define CFG_MAMR_8COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 391                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |   \
 392                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 393 /* 9 column SDRAM */
 394 #define CFG_MAMR_9COL   ((CFG_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE      |   \
 395                          MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 396                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 397
 398
 399 /*
 400  * Internal Definitions
 401  *
 402  * Boot Flags
 403  */
 404 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 405 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 406
 407 #endif  /* __CONFIG_H */