include/configs/G2000.h

   1 /*
   2  * (C) Copyright 2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  21 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  22 #define CONFIG_G2000            1       /* ...on a PLU405 board         */
  23
  24 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  25
  26 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  27 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  28
  29 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  30
  31 #if 0 /* test-only */
  32 #define CONFIG_BAUDRATE         115200
  33 #else
  34 #define CONFIG_BAUDRATE         9600
  35 #endif
  36
  37 #define CONFIG_PREBOOT
  38
  39 #undef  CONFIG_BOOTARGS
  40
  41 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  42         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  43                 "nfsroot=${serverip}:${rootpath}\0"                     \
  44         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  45         "addip=setenv bootargs ${bootargs} "                            \
  46                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  47                 ":${hostname}:${netdev}:off\0"                          \
  48         "addmisc=setenv bootargs ${bootargs} "                          \
  49                 "console=ttyS0,${baudrate} "                            \
  50                 "panic=1\0"                                             \
  51         "flash_nfs=run nfsargs addip addmisc;"                          \
  52                 "bootm ${kernel_addr}\0"                                \
  53         "flash_self=run ramargs addip addmisc;"                         \
  54                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  55         "net_nfs=tftp 200000 ${bootfile};"                              \
  56                 "run nfsargs addip addmisc;bootm\0"                     \
  57         "rootpath=/opt/eldk/ppc_4xx\0"                                  \
  58         "bootfile=/tftpboot/g2000/pImage\0"                             \
  59         "kernel_addr=ff800000\0"                                        \
  60         "ramdisk_addr=ff900000\0"                                       \
  61         "pciconfighost=yes\0"                                           \
  62         ""
  63 #define CONFIG_BOOTCOMMAND      "run net_nfs"
  64
  65 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  66
  67
  68 #define CONFIG_PPC4xx_EMAC
  69 #define CONFIG_MII              1       /* MII PHY management           */
  70 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  71 #define CONFIG_PHY1_ADDR        1       /* PHY address                  */
  72
  73 #if 0 /* test-only */
  74 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
  75 #endif
  76
  77
  78 /*
  79  * BOOTP options
  80  */
  81 #define CONFIG_BOOTP_BOOTFILESIZE
  82 #define CONFIG_BOOTP_BOOTPATH
  83 #define CONFIG_BOOTP_GATEWAY
  84 #define CONFIG_BOOTP_HOSTNAME
  85
  86
  87 /*
  88  * Command line configuration.
  89  */
  90 #include <config_cmd_default.h>
  91
  92 #define CONFIG_CMD_DHCP
  93 #define CONFIG_CMD_PCI
  94 #define CONFIG_CMD_IRQ
  95 #define CONFIG_CMD_ELF
  96 #define CONFIG_CMD_DATE
  97 #define CONFIG_CMD_I2C
  98 #define CONFIG_CMD_MII
  99 #define CONFIG_CMD_PING
 100 #define CONFIG_CMD_BSP
 101 #define CONFIG_CMD_EEPROM
 102
 103
 104 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 105
 106 #if 0 /* test-only */
 107 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
 108 #endif
 109
 110 /*
 111  * Miscellaneous configurable options
 112  */
 113 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 114 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 115
 116 #undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
 117
 118 #if defined(CONFIG_CMD_KGDB)
 119 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 120 #else
 121 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 122 #endif
 123 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 124 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 125 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 126
 127 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
 128
 129 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 130
 131 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 132
 133 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 134 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 135
 136 #define CONFIG_CONS_INDEX       1
 137 #define CONFIG_SYS_NS16550
 138 #define CONFIG_SYS_NS16550_SERIAL
 139 #define CONFIG_SYS_NS16550_REG_SIZE     1
 140 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 141
 142 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 143 #define CONFIG_SYS_BASE_BAUD        691200
 144
 145 /* The following table includes the supported baudrates */
 146 #define CONFIG_SYS_BAUDRATE_TABLE       \
 147         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 148          57600, 115200, 230400, 460800, 921600 }
 149
 150 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 151 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 152
 153 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 154
 155 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 156 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
 157
 158 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 159
 160 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 161
 162 /*----------------------------------------------------------------------------*/
 163 /* adding Ethernet setting:  FTS OUI 00:11:0B */
 164 /*----------------------------------------------------------------------------*/
 165 #define CONFIG_ETHADDR          00:11:0B:00:00:01
 166 #define CONFIG_HAS_ETH1
 167 #define CONFIG_ETH1ADDR         00:11:0B:00:00:02
 168 #define CONFIG_IPADDR           10.48.8.178
 169 #define CONFIG_IP1ADDR          10.48.8.188
 170 #define CONFIG_NETMASK          255.255.255.128
 171 #define CONFIG_SERVERIP         10.48.8.138
 172
 173 /*-----------------------------------------------------------------------
 174  * RTC stuff
 175  *-----------------------------------------------------------------------
 176  */
 177 #define CONFIG_RTC_DS1337
 178 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 179
 180 #if 0 /* test-only */
 181 /*-----------------------------------------------------------------------
 182  * NAND-FLASH stuff
 183  *-----------------------------------------------------------------------
 184  */
 185 #define CONFIG_SYS_MAX_NAND_DEVICE      1       /* Max number of NAND devices           */
 186
 187 #define CONFIG_SYS_NAND_CE  (0x80000000 >> 1)   /* our CE is GPIO1 */
 188 #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2)   /* our CLE is GPIO2 */
 189 #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3)   /* our ALE is GPIO3 */
 190 #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4)   /* our RDY is GPIO4 */
 191
 192 #endif
 193
 194 /*-----------------------------------------------------------------------
 195  * PCI stuff
 196  *-----------------------------------------------------------------------
 197  */
 198 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 199 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 200 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 201
 202 #define CONFIG_PCI                      /* include pci support          */
 203 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 204 #define CONFIG_PCI_HOST PCI_HOST_HOST   /* select pci host function     */
 205 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 206                                         /* resource configuration       */
 207
 208 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 209
 210 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 211
 212 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 213 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 214 #define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 215 #define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
 216 #define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
 217 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 218 #define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
 219 #define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 220 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 221
 222 /*
 223  * For booting Linux, the board info and command line data
 224  * have to be in the first 8 MB of memory, since this is
 225  * the maximum mapped by the Linux kernel during initialization.
 226  */
 227 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 228
 229 /*-----------------------------------------------------------------------
 230  * FLASH organization
 231  */
 232 #if 0 /* APC405 */
 233 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant              */
 234 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip    */
 235 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 236 #undef CONFIG_SYS_FLASH_PROTECTION              /* don't use hardware protection        */
 237 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 238 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* test-only...*/
 239 #define CONFIG_SYS_FLASH_INCREMENT      0x01000000 /* test-only */
 240 #else /* G2000 */
 241 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant              */
 242 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip    */
 243 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 244 #undef CONFIG_SYS_FLASH_PROTECTION              /* don't use hardware protection        */
 245 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 246 #define CONFIG_SYS_FLASH_BASE           0xFF800000 /* test-only...*/
 247 #define CONFIG_SYS_FLASH_INCREMENT      0x01000000 /* test-only */
 248 #endif
 249
 250 #define CONFIG_SYS_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 251
 252 #define CONFIG_SYS_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
 253 #define CONFIG_SYS_JFFS2_NUM_BANKS     1           /* ! second bank contains u-boot    */
 254
 255 /*-----------------------------------------------------------------------
 256  * Start addresses for the final memory configuration
 257  * (Set up by the startup code)
 258  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 259  */
 260 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 261 #define CONFIG_SYS_MONITOR_BASE 0xFFFC0000
 262 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 263 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Reserve 256 kB for malloc()  */
 264
 265 /*-----------------------------------------------------------------------
 266  * Environment Variable setup
 267  */
 268 #if 1 /* test-only */
 269 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 270 #define CONFIG_ENV_OFFSET               0x100   /* environment starts at the beginning of the EEPROM */
 271 #define CONFIG_ENV_SIZE         0x700   /* 2048 bytes may be used for env vars*/
 272                                    /* total size of a CAT24WC16 is 2048 bytes */
 273
 274 #else   /* DEFAULT: environment in flash, using redundand flash sectors */
 275
 276 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
 277 #define CONFIG_ENV_ADDR         0xFFFA0000 /* environment starts before u-boot */
 278 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128k bytes may be used for env vars*/
 279
 280 #endif
 281
 282 /*-----------------------------------------------------------------------
 283  * I2C EEPROM (CAT24WC16) for environment
 284  */
 285 #define CONFIG_SYS_I2C
 286 #define CONFIG_SYS_I2C_PPC4XX
 287 #define CONFIG_SYS_I2C_PPC4XX_CH0
 288 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 289 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 290
 291 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT24WC08             */
 292 /* CAT24WC08/16... */
 293 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 294 /* mask of address bits that overflow into the "EEPROM chip address"    */
 295 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 296 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 297                                         /* 16 byte page write mode using*/
 298                                         /* last 4 bits of the address   */
 299 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 300
 301 /*-----------------------------------------------------------------------
 302  * External Bus Controller (EBC) Setup
 303  */
 304
 305 /* Memory Bank 0 (Intel Strata Flash) initialization                            */
 306 #define CONFIG_SYS_EBC_PB0AP   0x92015480
 307 #define CONFIG_SYS_EBC_PB0CR   0xFF87A000          /* BAS=0xFF8,BS=08MB,BU=R/W,BW=16bit*/
 308
 309 /* Memory Bank 1 ( Power TAU) initialization               */
 310 /* #define CONFIG_SYS_EBC_PB1AP           0x04041000 */
 311 /* #define CONFIG_SYS_EBC_PB1CR           0xF0018000   */  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 312 #define CONFIG_SYS_EBC_PB1AP           0x00000000
 313 #define CONFIG_SYS_EBC_PB1CR           0x00000000
 314
 315 /* Memory Bank 2 (Intel Flash) initialization                 */
 316 #define CONFIG_SYS_EBC_PB2AP           0x00000000
 317 #define CONFIG_SYS_EBC_PB2CR           0x00000000
 318
 319 /* Memory Bank 3 (NAND) initialization                        */
 320 #define CONFIG_SYS_EBC_PB3AP           0x92015480
 321 #define CONFIG_SYS_EBC_PB3CR           0xF40B8000  /*addr 0xF40, BS=32M,BU=R/W, BW=8bit */
 322
 323 /* Memory Bank 4 (FPGA regs) initialization                                     */
 324 #define CONFIG_SYS_EBC_PB4AP           0x00000000
 325 #define CONFIG_SYS_EBC_PB4CR           0x00000000  /* leave it blank  */
 326
 327 #define CONFIG_SYS_NAND_BASE   0xF4000000
 328
 329 /*-----------------------------------------------------------------------
 330  * Definitions for initial stack pointer and data area (in data cache)
 331  */
 332 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 333 #define CONFIG_SYS_TEMP_STACK_OCM         1
 334
 335 /* On Chip Memory location */
 336 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 337 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 338 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 339 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 340
 341 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 342 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 343
 344 /*-----------------------------------------------------------------------
 345  * Definitions for GPIO setup (PPC405EP specific)
 346  *
 347  * GPIO0[0]     - External Bus Controller BLAST output
 348  * GPIO0[1-9]   - Instruction trace outputs
 349  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 350  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
 351  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 352  * GPIO0[24-27] - UART0 control signal inputs/outputs
 353  * GPIO0[28-29] - UART1 data signal input/output
 354  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 355  *
 356  * following GPIO setting changed for G20000, 080304
 357  */
 358 #define CONFIG_SYS_GPIO0_OSRL          0x40005555
 359 #define CONFIG_SYS_GPIO0_OSRH          0x40000110
 360 #define CONFIG_SYS_GPIO0_ISR1L         0x00000000
 361 #define CONFIG_SYS_GPIO0_ISR1H         0x15555445
 362 #define CONFIG_SYS_GPIO0_TSRL          0x00000000
 363 #define CONFIG_SYS_GPIO0_TSRH          0x00000000
 364 #define CONFIG_SYS_GPIO0_TCR           0xF7FF8014
 365
 366 /*
 367  * Default speed selection (cpu_plb_opb_ebc) in mhz.
 368  * This value will be set if iic boot eprom is disabled.
 369  */
 370 #if 1
 371 #define PLLMR0_DEFAULT   PLLMR0_266_66_33_33
 372 #define PLLMR1_DEFAULT   PLLMR1_266_66_33_33
 373 #endif
 374 #if 0
 375 #define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
 376 #define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
 377 #endif
 378 #if 0
 379 #define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
 380 #define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
 381 #endif
 382 #if 0
 383 #define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 384 #define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 385 #endif
 386
 387 #endif  /* __CONFIG_H */