include/configs/G2000.h

   1 /*
   2  * (C) Copyright 2004
   3  * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_405EP            1       /* This is a PPC405 CPU         */
  37 #define CONFIG_4xx              1       /* ...member of PPC4xx family   */
  38 #define CONFIG_G2000            1       /* ...on a PLU405 board         */
  39
  40 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  41
  42 #define CONFIG_BOARD_EARLY_INIT_F 1     /* call board_early_init_f()    */
  43 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
  44
  45 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  46
  47 #if 0 /* test-only */
  48 #define CONFIG_BAUDRATE         115200
  49 #else
  50 #define CONFIG_BAUDRATE         9600
  51 #endif
  52
  53 #define CONFIG_PREBOOT
  54
  55 #undef  CONFIG_BOOTARGS
  56
  57 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  58         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  59                 "nfsroot=${serverip}:${rootpath}\0"                     \
  60         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  61         "addip=setenv bootargs ${bootargs} "                            \
  62                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  63                 ":${hostname}:${netdev}:off\0"                          \
  64         "addmisc=setenv bootargs ${bootargs} "                          \
  65                 "console=ttyS0,${baudrate} "                            \
  66                 "panic=1\0"                                             \
  67         "flash_nfs=run nfsargs addip addmisc;"                          \
  68                 "bootm ${kernel_addr}\0"                                \
  69         "flash_self=run ramargs addip addmisc;"                         \
  70                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  71         "net_nfs=tftp 200000 ${bootfile};"                              \
  72                 "run nfsargs addip addmisc;bootm\0"                     \
  73         "rootpath=/opt/eldk/ppc_4xx\0"                                  \
  74         "bootfile=/tftpboot/g2000/pImage\0"                             \
  75         "kernel_addr=ff800000\0"                                        \
  76         "ramdisk_addr=ff900000\0"                                       \
  77         "pciconfighost=yes\0"                                           \
  78         ""
  79 #define CONFIG_BOOTCOMMAND      "run net_nfs"
  80
  81 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
  82
  83
  84 #define CONFIG_PPC4xx_EMAC
  85 #define CONFIG_MII              1       /* MII PHY management           */
  86 #define CONFIG_PHY_ADDR         0       /* PHY address                  */
  87 #define CONFIG_PHY1_ADDR        1       /* PHY address                  */
  88
  89 #if 0 /* test-only */
  90 #define CONFIG_PHY_CLK_FREQ     EMAC_STACR_CLK_66MHZ /* 66 MHz OPB clock*/
  91 #endif
  92
  93
  94 /*
  95  * BOOTP options
  96  */
  97 #define CONFIG_BOOTP_BOOTFILESIZE
  98 #define CONFIG_BOOTP_BOOTPATH
  99 #define CONFIG_BOOTP_GATEWAY
 100 #define CONFIG_BOOTP_HOSTNAME
 101
 102
 103 /*
 104  * Command line configuration.
 105  */
 106 #include <config_cmd_default.h>
 107
 108 #define CONFIG_CMD_DHCP
 109 #define CONFIG_CMD_PCI
 110 #define CONFIG_CMD_IRQ
 111 #define CONFIG_CMD_ELF
 112 #define CONFIG_CMD_DATE
 113 #define CONFIG_CMD_I2C
 114 #define CONFIG_CMD_MII
 115 #define CONFIG_CMD_PING
 116 #define CONFIG_CMD_BSP
 117 #define CONFIG_CMD_EEPROM
 118
 119
 120 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 121
 122 #if 0 /* test-only */
 123 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0    */
 124 #endif
 125
 126 /*
 127  * Miscellaneous configurable options
 128  */
 129 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 130 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 131
 132 #undef  CONFIG_SYS_HUSH_PARSER                  /* use "hush" command parser    */
 133
 134 #if defined(CONFIG_CMD_KGDB)
 135 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 136 #else
 137 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 138 #endif
 139 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 140 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 141 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 142
 143 #define CONFIG_SYS_DEVICE_NULLDEV       1       /* include nulldev device       */
 144
 145 #define CONFIG_SYS_CONSOLE_INFO_QUIET   1       /* don't print console @ startup*/
 146
 147 #define CONFIG_AUTO_COMPLETE    1       /* add autocompletion support   */
 148
 149 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 150 #define CONFIG_SYS_MEMTEST_END          0x0C00000       /* 4 ... 12 MB in DRAM  */
 151
 152 #define CONFIG_CONS_INDEX       1
 153 #define CONFIG_SYS_NS16550
 154 #define CONFIG_SYS_NS16550_SERIAL
 155 #define CONFIG_SYS_NS16550_REG_SIZE     1
 156 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 157
 158 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK            /* no external serial clock used */
 159 #define CONFIG_SYS_BASE_BAUD        691200
 160
 161 /* The following table includes the supported baudrates */
 162 #define CONFIG_SYS_BAUDRATE_TABLE       \
 163         { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400,     \
 164          57600, 115200, 230400, 460800, 921600 }
 165
 166 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 167 #define CONFIG_SYS_EXTBDINFO    1               /* To use extended board_into (bd_t) */
 168
 169 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 170
 171 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 172 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds     */
 173
 174 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 175
 176 #define CONFIG_SYS_RX_ETH_BUFFER        16      /* use 16 rx buffer on 405 emac */
 177
 178 /*----------------------------------------------------------------------------*/
 179 /* adding Ethernet setting:  FTS OUI 00:11:0B */
 180 /*----------------------------------------------------------------------------*/
 181 #define CONFIG_ETHADDR          00:11:0B:00:00:01
 182 #define CONFIG_HAS_ETH1
 183 #define CONFIG_ETH1ADDR         00:11:0B:00:00:02
 184 #define CONFIG_IPADDR           10.48.8.178
 185 #define CONFIG_IP1ADDR          10.48.8.188
 186 #define CONFIG_NETMASK          255.255.255.128
 187 #define CONFIG_SERVERIP         10.48.8.138
 188
 189 /*-----------------------------------------------------------------------
 190  * RTC stuff
 191  *-----------------------------------------------------------------------
 192  */
 193 #define CONFIG_RTC_DS1337
 194 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 195
 196 #if 0 /* test-only */
 197 /*-----------------------------------------------------------------------
 198  * NAND-FLASH stuff
 199  *-----------------------------------------------------------------------
 200  */
 201 #define CONFIG_SYS_MAX_NAND_DEVICE      1       /* Max number of NAND devices           */
 202
 203 #define CONFIG_SYS_NAND_CE  (0x80000000 >> 1)   /* our CE is GPIO1 */
 204 #define CONFIG_SYS_NAND_CLE (0x80000000 >> 2)   /* our CLE is GPIO2 */
 205 #define CONFIG_SYS_NAND_ALE (0x80000000 >> 3)   /* our ALE is GPIO3 */
 206 #define CONFIG_SYS_NAND_RDY (0x80000000 >> 4)   /* our RDY is GPIO4 */
 207
 208 #endif
 209
 210 /*-----------------------------------------------------------------------
 211  * PCI stuff
 212  *-----------------------------------------------------------------------
 213  */
 214 #define PCI_HOST_ADAPTER 0              /* configure as pci adapter     */
 215 #define PCI_HOST_FORCE  1               /* configure as pci host        */
 216 #define PCI_HOST_AUTO   2               /* detected via arbiter enable  */
 217
 218 #define CONFIG_PCI                      /* include pci support          */
 219 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 220 #define CONFIG_PCI_HOST PCI_HOST_HOST   /* select pci host function     */
 221 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 222                                         /* resource configuration       */
 223
 224 #define CONFIG_PCI_SCAN_SHOW            /* print pci devices @ startup  */
 225
 226 #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
 227
 228 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE  /* PCI Vendor ID: esd gmbh      */
 229 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405  /* PCI Device ID: CPCI-405      */
 230 #define CONFIG_SYS_PCI_CLASSCODE       0x0b20  /* PCI Class Code: Processor/PPC*/
 231 #define CONFIG_SYS_PCI_PTM1LA  0x00000000      /* point to sdram               */
 232 #define CONFIG_SYS_PCI_PTM1MS  0xfc000001      /* 64MB, enable hard-wired to 1 */
 233 #define CONFIG_SYS_PCI_PTM1PCI 0x00000000      /* Host: use this pci address   */
 234 #define CONFIG_SYS_PCI_PTM2LA  0xffc00000      /* point to flash               */
 235 #define CONFIG_SYS_PCI_PTM2MS  0xffc00001      /* 4MB, enable                  */
 236 #define CONFIG_SYS_PCI_PTM2PCI 0x04000000      /* Host: use this pci address   */
 237
 238 /*
 239  * For booting Linux, the board info and command line data
 240  * have to be in the first 8 MB of memory, since this is
 241  * the maximum mapped by the Linux kernel during initialization.
 242  */
 243 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 244
 245 /*-----------------------------------------------------------------------
 246  * FLASH organization
 247  */
 248 #if 0 /* APC405 */
 249 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant              */
 250 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip    */
 251 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks           */
 252 #undef CONFIG_SYS_FLASH_PROTECTION              /* don't use hardware protection        */
 253 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 254 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* test-only...*/
 255 #define CONFIG_SYS_FLASH_INCREMENT      0x01000000 /* test-only */
 256 #else /* G2000 */
 257 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant              */
 258 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max number of sectors on one chip    */
 259 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 260 #undef CONFIG_SYS_FLASH_PROTECTION              /* don't use hardware protection        */
 261 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 262 #define CONFIG_SYS_FLASH_BASE           0xFF800000 /* test-only...*/
 263 #define CONFIG_SYS_FLASH_INCREMENT      0x01000000 /* test-only */
 264 #endif
 265
 266 #define CONFIG_SYS_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 267
 268 #define CONFIG_SYS_JFFS2_FIRST_BANK    0           /* use for JFFS2 */
 269 #define CONFIG_SYS_JFFS2_NUM_BANKS     1           /* ! second bank contains u-boot    */
 270
 271 /*-----------------------------------------------------------------------
 272  * Start addresses for the final memory configuration
 273  * (Set up by the startup code)
 274  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 275  */
 276 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 277 #define CONFIG_SYS_MONITOR_BASE 0xFFFC0000
 278 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024)    /* Reserve 256 kB for Monitor   */
 279 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024)    /* Reserve 256 kB for malloc()  */
 280
 281 /*-----------------------------------------------------------------------
 282  * Environment Variable setup
 283  */
 284 #if 1 /* test-only */
 285 #define CONFIG_ENV_IS_IN_EEPROM 1       /* use EEPROM for environment vars */
 286 #define CONFIG_ENV_OFFSET               0x100   /* environment starts at the beginning of the EEPROM */
 287 #define CONFIG_ENV_SIZE         0x700   /* 2048 bytes may be used for env vars*/
 288                                    /* total size of a CAT24WC16 is 2048 bytes */
 289
 290 #else   /* DEFAULT: environment in flash, using redundand flash sectors */
 291
 292 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
 293 #define CONFIG_ENV_ADDR         0xFFFA0000 /* environment starts before u-boot */
 294 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128k bytes may be used for env vars*/
 295
 296 #endif
 297
 298 /*-----------------------------------------------------------------------
 299  * I2C EEPROM (CAT24WC16) for environment
 300  */
 301 #define CONFIG_SYS_I2C
 302 #define CONFIG_SYS_I2C_PPC4XX
 303 #define CONFIG_SYS_I2C_PPC4XX_CH0
 304 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 305 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 306
 307 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50    /* EEPROM CAT24WC08             */
 308 /* CAT24WC08/16... */
 309 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1        /* Bytes of address             */
 310 /* mask of address bits that overflow into the "EEPROM chip address"    */
 311 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
 312 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4     /* The Catalyst CAT24WC08 has   */
 313                                         /* 16 byte page write mode using*/
 314                                         /* last 4 bits of the address   */
 315 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10   /* and takes up to 10 msec */
 316
 317 /*-----------------------------------------------------------------------
 318  * External Bus Controller (EBC) Setup
 319  */
 320
 321 /* Memory Bank 0 (Intel Strata Flash) initialization                            */
 322 #define CONFIG_SYS_EBC_PB0AP   0x92015480
 323 #define CONFIG_SYS_EBC_PB0CR   0xFF87A000          /* BAS=0xFF8,BS=08MB,BU=R/W,BW=16bit*/
 324
 325 /* Memory Bank 1 ( Power TAU) initialization               */
 326 /* #define CONFIG_SYS_EBC_PB1AP           0x04041000 */
 327 /* #define CONFIG_SYS_EBC_PB1CR           0xF0018000   */  /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit  */
 328 #define CONFIG_SYS_EBC_PB1AP           0x00000000
 329 #define CONFIG_SYS_EBC_PB1CR           0x00000000
 330
 331 /* Memory Bank 2 (Intel Flash) initialization                 */
 332 #define CONFIG_SYS_EBC_PB2AP           0x00000000
 333 #define CONFIG_SYS_EBC_PB2CR           0x00000000
 334
 335 /* Memory Bank 3 (NAND) initialization                        */
 336 #define CONFIG_SYS_EBC_PB3AP           0x92015480
 337 #define CONFIG_SYS_EBC_PB3CR           0xF40B8000  /*addr 0xF40, BS=32M,BU=R/W, BW=8bit */
 338
 339 /* Memory Bank 4 (FPGA regs) initialization                                     */
 340 #define CONFIG_SYS_EBC_PB4AP           0x00000000
 341 #define CONFIG_SYS_EBC_PB4CR           0x00000000  /* leave it blank  */
 342
 343 #define CONFIG_SYS_NAND_BASE   0xF4000000
 344
 345 /*-----------------------------------------------------------------------
 346  * Definitions for initial stack pointer and data area (in data cache)
 347  */
 348 /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
 349 #define CONFIG_SYS_TEMP_STACK_OCM         1
 350
 351 /* On Chip Memory location */
 352 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 353 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 354 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 355 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 356
 357 #define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 358 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 359
 360 /*-----------------------------------------------------------------------
 361  * Definitions for GPIO setup (PPC405EP specific)
 362  *
 363  * GPIO0[0]     - External Bus Controller BLAST output
 364  * GPIO0[1-9]   - Instruction trace outputs
 365  * GPIO0[10-13] - External Bus Controller CS_1 - CS_4 outputs
 366  * GPIO0[14-16] - External Bus Controller ABUS3-ABUS5 outputs
 367  * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs
 368  * GPIO0[24-27] - UART0 control signal inputs/outputs
 369  * GPIO0[28-29] - UART1 data signal input/output
 370  * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs
 371  *
 372  * following GPIO setting changed for G20000, 080304
 373  */
 374 #define CONFIG_SYS_GPIO0_OSRL          0x40005555
 375 #define CONFIG_SYS_GPIO0_OSRH          0x40000110
 376 #define CONFIG_SYS_GPIO0_ISR1L         0x00000000
 377 #define CONFIG_SYS_GPIO0_ISR1H         0x15555445
 378 #define CONFIG_SYS_GPIO0_TSRL          0x00000000
 379 #define CONFIG_SYS_GPIO0_TSRH          0x00000000
 380 #define CONFIG_SYS_GPIO0_TCR           0xF7FF8014
 381
 382 /*
 383  * Default speed selection (cpu_plb_opb_ebc) in mhz.
 384  * This value will be set if iic boot eprom is disabled.
 385  */
 386 #if 1
 387 #define PLLMR0_DEFAULT   PLLMR0_266_66_33_33
 388 #define PLLMR1_DEFAULT   PLLMR1_266_66_33_33
 389 #endif
 390 #if 0
 391 #define PLLMR0_DEFAULT   PLLMR0_266_133_66_33
 392 #define PLLMR1_DEFAULT   PLLMR1_266_133_66_33
 393 #endif
 394 #if 0
 395 #define PLLMR0_DEFAULT   PLLMR0_200_100_50_33
 396 #define PLLMR1_DEFAULT   PLLMR1_200_100_50_33
 397 #endif
 398 #if 0
 399 #define PLLMR0_DEFAULT   PLLMR0_133_66_66_33
 400 #define PLLMR1_DEFAULT   PLLMR1_133_66_66_33
 401 #endif
 402
 403 #endif  /* __CONFIG_H */