include/configs/HWW1U1A.h

   1 /*
   2  * Copyright 2009-2010 eXMeritus, A Boeing Company
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * HardwareWall HWW-1U-1A airborne unit configuration file
  25  */
  26 #ifndef __CONFIG_H
  27 #define __CONFIG_H
  28
  29 /* High-level system configuration options */
  30 #define CONFIG_BOOKE            /* Power/PowerPC Book-E                 */
  31 #define CONFIG_E500             /* e500 (Power ISA v2.03 with SPE)      */
  32 #define CONFIG_MPC85xx          /* MPC8540/60/55/41/48 family           */
  33 #define CONFIG_FSL_ELBC         /* FreeScale Enhanced LocalBus Cntlr    */
  34 #define CONFIG_FSL_LAW          /* FreeScale Local Access Window        */
  35 #define CONFIG_P2020            /* FreeScale P2020                      */
  36 #define CONFIG_HWW1U1A          /* eXMeritus HardwareWall HWW-1U-1A     */
  37 #define CONFIG_MP               /* Multiprocessing support              */
  38 #define CONFIG_HWCONFIG         /* Use hwconfig from environment        */
  39
  40 #define CONFIG_L2_CACHE                 /* L2 cache enabled             */
  41 #define CONFIG_BTB                      /* Branch predition enabled     */
  42
  43 #define CONFIG_PANIC_HANG               /* No board reset on panic      */
  44 #define CONFIG_BOARD_EARLY_INIT_R       /* Call board_early_init_r()    */
  45 #define CONFIG_CMD_REGINFO              /* Dump various CPU regs        */
  46
  47 /*
  48  * Allow the use of 36-bit physical addresses.  Device-trees with 64-bit
  49  * addresses have known compatibility issues with some existing kernels.
  50  */
  51 #define CONFIG_ENABLE_36BIT_PHYS
  52 #define CONFIG_PHYS_64BIT
  53 #define CONFIG_ADDR_MAP
  54 #define CONFIG_SYS_NUM_ADDR_MAP 16 /* Number of entries in TLB1 */
  55
  56 /* Reserve plenty of RAM for malloc (we have 2GB+) */
  57 #define CONFIG_SYS_MALLOC_LEN (1024 * 1024)
  58
  59 /* How much L2 cache do we map so we can use it as RAM */
  60 #define CONFIG_SYS_INIT_RAM_LOCK
  61 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
  62
  63 /* This is our temporary global data area just above the stack */
  64 #define CONFIG_SYS_GBL_DATA_OFFSET \
  65         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  66
  67 /* The stack grows down from the global data area */
  68 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  69
  70 /* Enable IRQs and watchdog with a 1000Hz system decrementer */
  71 #define CONFIG_CMD_IRQ
  72 #define CONFIG_SYS_HZ 1000
  73
  74
  75 /* -------------------------------------------------------------------- */
  76
  77 /*
  78  * Clock crystal configuration:
  79  *  (1) SYS: 66.666MHz +/- 50ppm (drives CPU/PCI/DDR)
  80  *  (2) CCB: Multiplier from SYS_CLK
  81  *  (3) RTC: 25.000MHz +/- 50ppm (sampled against CCB clock)
  82  */
  83 #define CONFIG_SYS_CLK_FREQ 66666000/*Hz*/
  84 #define CONFIG_DDR_CLK_FREQ 66666000/*Hz*/
  85
  86
  87 /* -------------------------------------------------------------------- */
  88
  89 /*
  90  * Memory map
  91  *
  92  * 0x0000_0000  0x7fff_ffff    2G  DDR2 ECC SDRAM
  93  * 0x8000_0000  0x9fff_ffff  512M  PCI-E Bus 1
  94  * 0xa000_0000  0xbfff_ffff  512M  PCI-E Bus 2 (unused)
  95  * 0xc000_0000  0xdfff_ffff  512M  PCI-E Bus 3
  96  * 0xe000_0000  0xe7ff_ffff  128M  Spansion FLASH
  97  * 0xe800_0000  0xefff_ffff  128M  Spansion FLASH
  98  * 0xffd0_0000  0xffd0_3fff   16K  L1 boot stack (TLB0)
  99  * 0xffe0_0000  0xffef_ffff    1M  CCSR
 100  * 0xffe0_5000  0xffe0_5fff    4K    Enhanced LocalBus Controller
 101  */
 102
 103 /* Virtual Memory Map */
 104 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
 105 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 106 #define CONFIG_SYS_PCIE3_MEM_VIRT       0x80000000
 107 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 108 #define CONFIG_SYS_PCIE1_MEM_VIRT       0xc0000000
 109 #define CONFIG_SYS_FLASH_BASE           0xe0000000
 110 #define CONFIG_SYS_PCIE3_IO_VIRT        0xffc00000
 111 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 112 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc20000
 113 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000
 114 #define CONFIG_SYS_CCSRBAR              0xffe00000 /* CCSRBAR @ runtime */
 115
 116 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000 /* 512M */
 117 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000 /* 512M */
 118 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000 /* 512M */
 119 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000 /* 64k */
 120 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000 /* 64k */
 121 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000 /* 64k */
 122
 123 /* Physical Memory Map */
 124 #define CONFIG_SYS_PCIE3_MEM_PHYS     0xc00000000ull
 125 #define CONFIG_SYS_PCIE2_MEM_PHYS     0xc20000000ull
 126 #define CONFIG_SYS_PCIE1_MEM_PHYS     0xc40000000ull
 127 #define CONFIG_SYS_FLASH_BASE_PHYS    0xfe0000000ull
 128 #define CONFIG_SYS_PCIE3_IO_PHYS      0xfffc00000ull
 129 #define CONFIG_SYS_PCIE2_IO_PHYS      0xfffc10000ull
 130 #define CONFIG_SYS_PCIE1_IO_PHYS      0xfffc20000ull
 131 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS 0xfffd00000ull
 132 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf          /* for ASM code */
 133 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW  0xffd00000   /* for ASM code */
 134 #define CONFIG_SYS_CCSRBAR_PHYS_HIGH       0xf          /* for ASM code */
 135 #define CONFIG_SYS_CCSRBAR_PHYS_LOW        0xffe00000   /* for ASM code */
 136
 137
 138 /* -------------------------------------------------------------------- */
 139
 140 /* U-Boot image (MONITOR_BASE == TEXT_BASE) */
 141 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc /* Top address in flash */
 142 #define CONFIG_SYS_TEXT_BASE            0xeff80000 /* Start of U-Boot image */
 143 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 144 #define CONFIG_SYS_MONITOR_LEN          0x80000 /* 512kB (4 flash sectors) */
 145
 146 /*
 147  * U-Boot Environment Image:  The two sectors immediately below U-Boot
 148  * form the U-Boot environment (regular and redundant).
 149  */
 150 #define CONFIG_ENV_IS_IN_FLASH  /* The environment image is stored in FLASH */
 151 #define CONFIG_ENV_OVERWRITE    /* Allow "protected" variables to be erased */
 152 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128kB (1 flash sector) */
 153 #define CONFIG_ENV_ADDR        (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 154 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR         - CONFIG_ENV_SECT_SIZE)
 155
 156 /* Only use 8kB of each environment sector for data */
 157 #define CONFIG_ENV_SIZE         0x2000 /* 8kB */
 158 #define CONFIG_ENV_SIZE_REDUND  0x2000 /* 8kB */
 159
 160
 161 /* -------------------------------------------------------------------- */
 162
 163 /* Serial Console Configuration */
 164 #define CONFIG_CONS_INDEX 1
 165 #define CONFIG_SYS_NS16550
 166 #define CONFIG_SYS_NS16550_SERIAL
 167 #define CONFIG_SYS_NS16550_REG_SIZE 1
 168 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
 169
 170 #define CONFIG_BAUDRATE 115200
 171 #define CONFIG_SYS_BAUDRATE_TABLE \
 172         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
 173
 174 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 175 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 176
 177 /* Echo back characters received during a serial download */
 178 #define CONFIG_LOADS_ECHO
 179
 180 /* Allow a serial-download to temporarily change baud */
 181 #define CONFIG_SYS_LOADS_BAUD_CHANGE
 182
 183
 184 /* -------------------------------------------------------------------- */
 185
 186 /* PCI and PCI-Express Support */
 187 #define CONFIG_PCI              /* Enable PCI/PCIE                      */
 188 #define CONFIG_PCI_PNP          /* Scan PCI busses                      */
 189 #define CONFIG_CMD_PCI          /* Enable the "pci" command             */
 190 #define CONFIG_FSL_PCI_INIT     /* Common FreeScale PCI initialization  */
 191 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 192 #define CONFIG_FSL_PCIE_RESET   /* We have PCI-E reset errata           */
 193 #define CONFIG_SYS_PCI_64BIT    /* PCI resources are 64-bit             */
 194 #define CONFIG_PCI_SCAN_SHOW    /* Display PCI scan during boot         */
 195
 196 /* Enable 2 of the 3 PCI-E controllers */
 197 #define CONFIG_PCIE3
 198 #undef  CONFIG_PCIE2
 199 #define CONFIG_PCIE1
 200
 201 /* Display human-readable names when initializing */
 202 #define CONFIG_SYS_PCIE3_NAME "Intel 82571EB"
 203 #define CONFIG_SYS_PCIE2_NAME "Unused"
 204 #define CONFIG_SYS_PCIE1_NAME "Silicon Image SIL3531"
 205
 206 /*
 207  * PCI bus addresses
 208  * Memory space is mapped 1-1, but I/O space must start from 0.
 209  */
 210 #define CONFIG_SYS_PCIE3_IO_BUS  0x00000000
 211 #define CONFIG_SYS_PCIE2_IO_BUS  0x00000000
 212 #define CONFIG_SYS_PCIE1_IO_BUS  0x00000000
 213 #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
 214 #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
 215 #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
 216
 217
 218 /* -------------------------------------------------------------------- */
 219
 220 /* Generic FreeScale hardware I2C support */
 221 #define CONFIG_SYS_I2C
 222 #define CONFIG_SYS_I2C_FSL
 223 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 224 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 225 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 226 #define CONFIG_SYS_FSL_I2C2_SPEED       400000
 227 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 228 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 229 #define CONFIG_SYS_I2C_NOPROBES         { {0, 0x29} }
 230 #define CONFIG_CMD_I2C
 231
 232 /* DDR2 SO-RDIMM SPD EEPROM is at I2C0-0x51 */
 233 #define CONFIG_SYS_SPD_BUS_NUM 0
 234 #define SPD_EEPROM_ADDRESS 0x51
 235
 236 /* DS1339 RTC is at I2C0-0x68 (I know it says "DS1337", it's a DS1339) */
 237 #define CONFIG_CMD_DATE
 238 #define CONFIG_RTC_DS1337
 239 #define CONFIG_SYS_RTC_BUS_NUM 0
 240 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 241 /* Turn off RTC square-wave output to save battery */
 242 #define CONFIG_SYS_RTC_DS1337_NOOSC
 243
 244 /*
 245  * AT24C128N EEPROM at I2C0-0x53.
 246  *
 247  * That Atmel EEPROM has 128kbit of memory (16kByte) divided into 256 pages
 248  * of 64 bytes per page.  The chip uses 2-byte addresses and has a max write
 249  * cycle time of 20ms according to the datasheet.
 250  *
 251  * NOTE: Our environment is stored on regular direct-attached FLASH, this
 252  * chip is only used as a write-protected backup for certain key settings
 253  * such as the serial# and macaddr values.  (EG: "env import")
 254  */
 255 #define CONFIG_CMD_EEPROM
 256 #define CONFIG_ENV_EEPROM_IS_ON_I2C
 257 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
 258 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
 259 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 1 << 6 == 64 byte pages */
 260 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 21
 261
 262 /*
 263  * PCA9554 is at I2C1-0x3f (I know it says "PCA953X", it's a PCA9554).  You
 264  * must first select the I2C1 bus with "i2c dev 1" or the "pca953x" command
 265  * will not be able to access the chip.
 266  */
 267 #define CONFIG_PCA953X
 268 #define CONFIG_CMD_PCA953X
 269 #define CONFIG_CMD_PCA953X_INFO
 270 #define CONFIG_SYS_I2C_PCA953X_ADDR 0x3f
 271
 272
 273 /* -------------------------------------------------------------------- */
 274
 275 /* FreeScale DDR2/3 SDRAM Controller */
 276 #define CONFIG_FSL_DDR2         /* Our SDRAM slot is DDR2               */
 277 #define CONFIG_DDR_ECC          /* Enable ECC by default                */
 278 #define CONFIG_DDR_SPD          /* Detect DDR config from SPD EEPROM    */
 279 #define CONFIG_SPD_EEPROM       /* ...why 2 config variables for this?  */
 280 #define CONFIG_VERY_BIG_RAM     /* Allow 2GB+ of RAM                    */
 281 #define CONFIG_CMD_SDRAM
 282
 283 /* Standard P2020 DDR controller parameters */
 284 #define CONFIG_NUM_DDR_CONTROLLERS 1
 285 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
 286 #define CONFIG_CHIP_SELECTS_PER_CTRL 2
 287
 288 /* Make sure to tell the DDR controller to preinitialze all of RAM */
 289 #define CONFIG_MEM_INIT_VALUE 0xDEADBEEF
 290 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 291
 292
 293 /* -------------------------------------------------------------------- */
 294
 295 /* FLASH Memory Configuration (2x 128MB SPANSION FLASH) */
 296 #define CONFIG_FLASH_CFI_DRIVER
 297 #define CONFIG_SYS_FLASH_CFI
 298 #define CONFIG_SYS_FLASH_EMPTY_INFO
 299 #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7
 300
 301 /* Flash banks (2x 128MB) */
 302 #define FLASH0_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000ull)
 303 #define FLASH1_PHYS (CONFIG_SYS_FLASH_BASE_PHYS + 0x0000000ull)
 304 #define CONFIG_SYS_MAX_FLASH_BANKS 2
 305 #define CONFIG_SYS_MAX_FLASH_SECT 1024
 306 #define CONFIG_SYS_FLASH_BANKS_LIST { FLASH0_PHYS, FLASH1_PHYS }
 307
 308 /*
 309  * Flash access modes and timings (values are the defaults after a RESET).
 310  *
 311  * NOTE: These could probably be optimized but are more than sufficient for
 312  * this particular system for the moment.
 313  */
 314 #define FLASH_BRx (BR_PS_16 | BR_MS_GPCM | BR_V)
 315 #define FLASH_ORx (OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
 316                 | OR_GPCM_SCY_15 | OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 317
 318 /* Configure both flash banks */
 319 #define CONFIG_SYS_BR0_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH0_PHYS))
 320 #define CONFIG_SYS_BR1_PRELIM (FLASH_BRx | BR_PHYS_ADDR(FLASH1_PHYS))
 321 #define CONFIG_SYS_OR0_PRELIM (FLASH_ORx | OR_AM_128MB)
 322 #define CONFIG_SYS_OR1_PRELIM (FLASH_ORx | OR_AM_128MB)
 323
 324 /* Flash timeouts (in ms) */
 325 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000UL /* Erase (60s)      */
 326 #define CONFIG_SYS_FLASH_WRITE_TOUT   500UL /* Write (0.5s)     */
 327
 328 /* Quiet flash testing */
 329 #define CONFIG_SYS_FLASH_QUIET_TEST
 330
 331 /* Make program/erase count down from 45/5 (9....8....7....) */
 332 #define CONFIG_FLASH_SHOW_PROGRESS 45
 333
 334
 335 /* -------------------------------------------------------------------- */
 336
 337 /* Ethernet Device Support */
 338 #define CONFIG_MII                      /* Enable MII PHY code          */
 339 #define CONFIG_MII_DEFAULT_TSEC         /* ??? Copied from P2020DS      */
 340 #define CONFIG_PHY_GIGE                 /* Support Gigabit PHYs         */
 341 #define CONFIG_ETHPRIME "e1000#0"       /* Default to external ports    */
 342
 343 /* Turn on various helpful networking commands */
 344 #define CONFIG_CMD_DHCP
 345 #define CONFIG_CMD_MII
 346 #define CONFIG_CMD_NET
 347 #define CONFIG_CMD_PING
 348
 349 /* On-chip FreeScale P2020 "tsec" Ethernet (oneway fibers and peer) */
 350 #define CONFIG_TSEC_ENET
 351 #define CONFIG_TSEC1
 352 #define CONFIG_TSEC2
 353 #define CONFIG_TSEC3
 354 #define CONFIG_TSEC1_NAME "owt0"
 355 #define CONFIG_TSEC2_NAME "owt1"
 356 #define CONFIG_TSEC3_NAME "peer"
 357 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
 358 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
 359 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
 360 #define TSEC1_PHYIDX 0
 361 #define TSEC2_PHYIDX 0
 362 #define TSEC3_PHYIDX 0
 363 #define TSEC1_PHY_ADDR      2
 364 #define TSEC2_PHY_ADDR      3
 365 #define TSEC3_PHY_ADDR      4
 366 #define TSEC3_PHY_ADDR_CPUA 4
 367 #define TSEC3_PHY_ADDR_CPUB 5
 368
 369 /* PCI-E dual-port E1000 (external ethernet ports) */
 370 #define CONFIG_E1000
 371 #define CONFIG_E1000_SPI
 372 #define CONFIG_E1000_SPI_GENERIC
 373 #define CONFIG_CMD_E1000
 374
 375 /* We need the SPI infrastructure to poke the E1000's EEPROM */
 376 #define CONFIG_SPI
 377 #define CONFIG_SPI_X
 378 #define CONFIG_CMD_SPI
 379 #define MAX_SPI_BYTES 32
 380
 381
 382 /* -------------------------------------------------------------------- */
 383
 384 /* USB Thumbdrive Device Support */
 385 #define CONFIG_USB_EHCI
 386 #define CONFIG_USB_EHCI_FSL
 387 #define CONFIG_USB_STORAGE
 388 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 389 #define CONFIG_CMD_USB
 390
 391 /* Partition and Filesystem support */
 392 #define CONFIG_DOS_PARTITION
 393 #define CONFIG_EFI_PARTITION
 394 #define CONFIG_ISO_PARTITION
 395 #define CONFIG_CMD_EXT2
 396 #define CONFIG_CMD_FAT
 397
 398
 399 /* -------------------------------------------------------------------- */
 400
 401 /* Command line configuration. */
 402 #define CONFIG_CMDLINE_EDITING          /* Enable command editing       */
 403 #define CONFIG_COMMAND_HISTORY          /* Enable command history       */
 404 #define CONFIG_AUTO_COMPLETE            /* Enable command completion    */
 405 #define CONFIG_SYS_LONGHELP             /* Enable detailed command help */
 406 #define CONFIG_SYS_MAXARGS 128          /* Up to 128 command-line args  */
 407 #define CONFIG_SYS_PBSIZE 8192          /* Allow up to 8k printed lines */
 408 #define CONFIG_SYS_CBSIZE 4096          /* Allow up to 4k command lines */
 409 #define CONFIG_SYS_BARGSIZE 4096        /* Allow up to 4k boot args     */
 410 #define CONFIG_SYS_HUSH_PARSER          /* Enable a fancier shell       */
 411
 412 /* A little extra magic here for the prompt */
 413 #define CONFIG_SYS_PROMPT hww1u1a_get_ps1()
 414 #ifndef __ASSEMBLY__
 415 const char *hww1u1a_get_ps1(void);
 416 #endif
 417
 418 /* Include a bunch of default commands we probably want */
 419 #include <config_cmd_default.h>
 420
 421 /* Other helpful shell-like commands */
 422 #define CONFIG_MD5
 423 #define CONFIG_SHA1
 424 #define CONFIG_CMD_MD5SUM
 425 #define CONFIG_CMD_SHA1SUM
 426 #define CONFIG_CMD_ASKENV
 427 #define CONFIG_CMD_SETEXPR
 428
 429
 430 /* -------------------------------------------------------------------- */
 431
 432 /* Image manipulation and booting */
 433
 434 /* We use the OpenFirmware-esque "Flattened Device Tree" */
 435 #define CONFIG_OF_LIBFDT
 436 #define CONFIG_OF_BOARD_SETUP
 437 #define CONFIG_OF_STDOUT_VIA_ALIAS
 438
 439 /*
 440  * For booting Linux, the board info and command line data
 441  * have to be in the first 64 MB of memory, since this is
 442  * the maximum mapped by the Linux kernel during initialization.
 443  */
 444 #define CONFIG_CMD_ELF
 445 #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Maximum kernel memory map    */
 446 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Maximum kernel size of 64MB  */
 447
 448 /* This is the default address for commands with an optional address arg */
 449 #define CONFIG_LOADADDR           100000
 450 #define CONFIG_SYS_LOAD_ADDR    0x100000
 451
 452 /* Test memory starting from the default load address to just below 2GB */
 453 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_LOAD_ADDR
 454 #define CONFIG_SYS_MEMTEST_END          0x7f000000
 455
 456 #define CONFIG_BOOTDELAY 20
 457 #define CONFIG_BOOTCOMMAND "echo Not yet flashed"
 458 #define CONFIG_BOOTARGS ""
 459 #define CONFIG_BOOTARGS_DYNAMIC "console=ttyS0,${baudrate}n1"
 460
 461 /* Extra environment parameters */
 462 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 463         "ethprime=e1000#0\0"                                            \
 464         "ethrotate=no\0"                                                \
 465         "setbootargs=setenv bootargs "                                  \
 466                         "\"${bootargs} "CONFIG_BOOTARGS_DYNAMIC"\"\0"   \
 467         "perf_mode=performance\0"                                       \
 468         "hwconfig="     "fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;"   \
 469                         "usb1:dr_mode=host,phy_type=ulpi\0"             \
 470         "flkernel=0xe8000000\0"                                         \
 471         "flinitramfs=0xe8800000\0"                                      \
 472         "fldevicetree=0xeff20000\0"                                     \
 473         "flbootm=bootm ${flkernel} ${flinitramfs} ${fldevicetree}\0"    \
 474         "flboot=run preboot; run flbootm\0"                             \
 475         "restore_eeprom=i2c dev 0 && "                                  \
 476                         "eeprom read $loadaddr 0x0000 0x2000 && "       \
 477                         "env import -c $loadaddr 0x2000\0"
 478
 479 #endif  /* __CONFIG_H */