include/configs/IDS8247.h

   1 /*
   2  * (C) Copyright 2005
   3  * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC8260          1       /* This is a MPC8260 CPU                */
  21 #define CONFIG_MPC8272_FAMILY   1
  22 #define CONFIG_IDS8247          1
  23 #define CPU_ID_STR              "MPC8247"
  24 #define CONFIG_CPM2             1       /* Has a CPM2 */
  25
  26 #define CONFIG_SYS_TEXT_BASE    0xfff00000
  27
  28 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  29
  30 #define CONFIG_BOOTCOUNT_LIMIT
  31
  32 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
  33
  34 #undef  CONFIG_BOOTARGS
  35
  36 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  37         "netdev=eth0\0"                                                 \
  38         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  39                 "nfsroot=${serverip}:${rootpath}\0"                     \
  40         "ramargs=setenv bootargs root=/dev/ram rw "                     \
  41         "console=ttyS0,115200\0"                                        \
  42         "addip=setenv bootargs ${bootargs} "                            \
  43                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  44                 ":${hostname}:${netdev}:off panic=1\0"                  \
  45         "flash_nfs=run nfsargs addip;"                                  \
  46                 "bootm ${kernel_addr}\0"                                \
  47         "flash_self=run ramargs addip;"                                 \
  48                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  49         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  50         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
  51         "bootfile=/tftpboot/IDS8247/uImage\0"                           \
  52         "kernel_addr=ff800000\0"                                        \
  53         "ramdisk_addr=ffa00000\0"                                       \
  54         ""
  55 #define CONFIG_BOOTCOMMAND      "run flash_self"
  56
  57 #define CONFIG_MISC_INIT_R      1
  58
  59 /* enable I2C and select the hardware/software driver */
  60 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
  61 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
  62 #define CONFIG_SYS_I2C_SPEED            400000  /* I2C speed and slave address  */
  63 #define CONFIG_SYS_I2C_SLAVE            0x7F
  64
  65 /*
  66  * Software (bit-bang) I2C driver configuration
  67  */
  68
  69 #define I2C_PORT        0               /* Port A=0, B=1, C=2, D=3 */
  70 #define I2C_ACTIVE      (iop->pdir |=  0x00000080)
  71 #define I2C_TRISTATE    (iop->pdir &= ~0x00000080)
  72 #define I2C_READ        ((iop->pdat & 0x00000080) != 0)
  73 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00000080; \
  74                         else    iop->pdat &= ~0x00000080
  75 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00000100; \
  76                         else    iop->pdat &= ~0x00000100
  77 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
  78
  79 #if 0
  80 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
  81 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  82 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
  83 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* and takes up to 10 msec */
  84
  85 #define CONFIG_I2C_X
  86 #endif
  87
  88 /*
  89  * select serial console configuration
  90  * use the extern UART for the console
  91  */
  92 #define CONFIG_CONS_INDEX       1
  93 #define CONFIG_BAUDRATE         115200
  94 /*
  95  * NS16550 Configuration
  96  */
  97 #define CONFIG_SYS_NS16550
  98 #define CONFIG_SYS_NS16550_SERIAL
  99
 100 #define CONFIG_SYS_NS16550_REG_SIZE    1
 101
 102 #define CONFIG_SYS_NS16550_CLK         14745600
 103
 104 #define CONFIG_SYS_UART_BASE    0xE0000000
 105 #define CONFIG_SYS_UART_SIZE    0x10000
 106
 107 #define CONFIG_SYS_NS16550_COM1        (CONFIG_SYS_UART_BASE + 0x8000)
 108
 109
 110 /* pass open firmware flat tree */
 111 #define CONFIG_OF_LIBFDT        1
 112 #define CONFIG_OF_BOARD_SETUP   1
 113
 114 #define OF_TBCLK        (bd->bi_busfreq / 4)
 115 #define OF_STDOUT_PATH  "/soc@f0000000/serial8250@e0008000"
 116
 117
 118 /*
 119  * select ethernet configuration
 120  *
 121  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 122  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 123  * for FCC)
 124  *
 125  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 126  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 127  */
 128 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 129 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 130 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 131 #define CONFIG_ETHER_INDEX      1       /* which SCC/FCC channel for ethernet */
 132 #define CONFIG_ETHER_ON_FCC1
 133 #define FCC_ENET
 134
 135 /*
 136  * - Rx-CLK is CLK10
 137  * - Tx-CLK is CLK9
 138  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 139  * - Enable Full Duplex in FSMR
 140  */
 141 # define CONFIG_SYS_CMXFCR_MASK1        (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
 142 # define CONFIG_SYS_CMXFCR_VALUE1       (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK9)
 143 # define CONFIG_SYS_CPMFCR_RAMTYPE      0
 144 # define CONFIG_SYS_FCC_PSMR            (FCC_PSMR_FDE|FCC_PSMR_LPB)
 145
 146
 147 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 148 #define CONFIG_8260_CLKIN       66666666        /* in Hz */
 149
 150 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 151 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
 152
 153 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 154
 155 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
 156
 157 /*
 158  * BOOTP options
 159  */
 160 #define CONFIG_BOOTP_SUBNETMASK
 161 #define CONFIG_BOOTP_GATEWAY
 162 #define CONFIG_BOOTP_HOSTNAME
 163 #define CONFIG_BOOTP_BOOTPATH
 164 #define CONFIG_BOOTP_BOOTFILESIZE
 165
 166 #define CONFIG_RTC_PCF8563
 167 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 168
 169 /*
 170  * Command line configuration.
 171  */
 172 #include <config_cmd_default.h>
 173
 174 #define CONFIG_CMD_DHCP
 175 #define CONFIG_CMD_NFS
 176 #define CONFIG_CMD_NAND
 177 #define CONFIG_CMD_I2C
 178 #define CONFIG_CMD_SNTP
 179
 180
 181 /*
 182  * Miscellaneous configurable options
 183  */
 184 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 185 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 186 #if defined(CONFIG_CMD_KGDB)
 187 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 188 #else
 189 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 190 #endif
 191 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 192 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 193 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 194
 195 #define CONFIG_SYS_MEMTEST_START        0x0400000       /* memtest works on     */
 196 #define CONFIG_SYS_MEMTEST_END  0x0C00000       /* 4 ... 12 MB in DRAM  */
 197
 198 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 199
 200 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1 ms ticks */
 201
 202 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC     /* "bad" address                */
 203
 204 /*
 205  * For booting Linux, the board info and command line data
 206  * have to be in the first 8 MB of memory, since this is
 207  * the maximum mapped by the Linux kernel during initialization.
 208  */
 209 #define CONFIG_SYS_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 210
 211 #define CONFIG_SYS_FLASH_CFI                            /* The flash is CFI compatible  */
 212 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
 213 #define CONFIG_SYS_FLASH_BANKS_LIST     { 0xFF800000 }
 214 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks         */
 215 /* What should the base address of the main FLASH be and how big is
 216  * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/ids8247/config.mk
 217  * The main FLASH is whichever is connected to *CS0.
 218  */
 219 #define CONFIG_SYS_FLASH0_BASE 0xFFF00000
 220 #define CONFIG_SYS_FLASH0_SIZE 8
 221
 222 /* Flash bank size (for preliminary settings)
 223  */
 224 #define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
 225
 226 /*-----------------------------------------------------------------------
 227  * FLASH organization
 228  */
 229 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 230
 231 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 232 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 233
 234 /* Environment in flash */
 235 #define CONFIG_ENV_IS_IN_FLASH  1
 236 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE+0x60000)
 237 #define CONFIG_ENV_SIZE         0x20000
 238 #define CONFIG_ENV_SECT_SIZE    0x20000
 239
 240 /*-----------------------------------------------------------------------
 241  * NAND-FLASH stuff
 242  *-----------------------------------------------------------------------
 243  */
 244 #if defined(CONFIG_CMD_NAND)
 245
 246 #define CONFIG_SYS_NAND0_BASE 0xE1000000
 247 #define CONFIG_SYS_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
 248
 249 #endif /* CONFIG_CMD_NAND */
 250
 251 /*-----------------------------------------------------------------------
 252  * Hard Reset Configuration Words
 253  *
 254  * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
 255  * defines for the various registers affected by the HRCW e.g. changing
 256  * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
 257  */
 258 #define CONFIG_SYS_HRCW_MASTER  (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
 259
 260 /* no slaves so just fill with zeros */
 261 #define CONFIG_SYS_HRCW_SLAVE1          0
 262 #define CONFIG_SYS_HRCW_SLAVE2          0
 263 #define CONFIG_SYS_HRCW_SLAVE3          0
 264 #define CONFIG_SYS_HRCW_SLAVE4          0
 265 #define CONFIG_SYS_HRCW_SLAVE5          0
 266 #define CONFIG_SYS_HRCW_SLAVE6          0
 267 #define CONFIG_SYS_HRCW_SLAVE7          0
 268
 269 /*-----------------------------------------------------------------------
 270  * Internal Memory Mapped Register
 271  */
 272 #define CONFIG_SYS_IMMR         0xF0000000
 273
 274 /*-----------------------------------------------------------------------
 275  * Definitions for initial stack pointer and data area (in DPRAM)
 276  */
 277 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 278 #define CONFIG_SYS_INIT_RAM_SIZE        0x2000  /* Size of used area in DPRAM    */
 279 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 280 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 281
 282 /*-----------------------------------------------------------------------
 283  * Start addresses for the final memory configuration
 284  * (Set up by the startup code)
 285  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 286  *
 287  * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE
 288  */
 289 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 290 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_FLASH0_BASE
 291 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 292 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 293 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()*/
 294
 295 /*-----------------------------------------------------------------------
 296  * Cache Configuration
 297  */
 298 #define CONFIG_SYS_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 299 #if defined(CONFIG_CMD_KGDB)
 300 # define CONFIG_SYS_CACHELINE_SHIFT     5       /* log base 2 of the above value */
 301 #endif
 302
 303 /*-----------------------------------------------------------------------
 304  * HIDx - Hardware Implementation-dependent Registers                    2-11
 305  *-----------------------------------------------------------------------
 306  * HID0 also contains cache control - initially enable both caches and
 307  * invalidate contents, then the final state leaves only the instruction
 308  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 309  * but Soft reset does not.
 310  *
 311  * HID1 has only read-only information - nothing to set.
 312  */
 313
 314 #define CONFIG_SYS_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
 315 #define CONFIG_SYS_HID0_FINAL  0
 316 #define CONFIG_SYS_HID2        0
 317
 318 /*-----------------------------------------------------------------------
 319  * RMR - Reset Mode Register                                     5-5
 320  *-----------------------------------------------------------------------
 321  * turn on Checkstop Reset Enable
 322  */
 323 #define CONFIG_SYS_RMR         0
 324
 325 /*-----------------------------------------------------------------------
 326  * BCR - Bus Configuration                                       4-25
 327  *-----------------------------------------------------------------------
 328  */
 329 #define CONFIG_SYS_BCR          0
 330
 331 /*-----------------------------------------------------------------------
 332  * SIUMCR - SIU Module Configuration                             4-31
 333  *-----------------------------------------------------------------------
 334  */
 335 #define CONFIG_SYS_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
 336
 337 /*-----------------------------------------------------------------------
 338  * SYPCR - System Protection Control                             4-35
 339  * SYPCR can only be written once after reset!
 340  *-----------------------------------------------------------------------
 341  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 342  */
 343 #if defined(CONFIG_WATCHDOG)
 344 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 345                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 346 #else
 347 #define CONFIG_SYS_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 348                          SYPCR_SWRI|SYPCR_SWP)
 349 #endif /* CONFIG_WATCHDOG */
 350
 351 /*-----------------------------------------------------------------------
 352  * TMCNTSC - Time Counter Status and Control                     4-40
 353  *-----------------------------------------------------------------------
 354  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 355  * and enable Time Counter
 356  */
 357 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 358
 359 /*-----------------------------------------------------------------------
 360  * PISCR - Periodic Interrupt Status and Control                 4-42
 361  *-----------------------------------------------------------------------
 362  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 363  * Periodic timer
 364  */
 365 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 366
 367 /*-----------------------------------------------------------------------
 368  * SCCR - System Clock Control                                   9-8
 369  *-----------------------------------------------------------------------
 370  * Ensure DFBRG is Divide by 16
 371  */
 372 #define CONFIG_SYS_SCCR        (0x00000028 | SCCR_DFBRG01)
 373
 374 /*-----------------------------------------------------------------------
 375  * RCCR - RISC Controller Configuration                         13-7
 376  *-----------------------------------------------------------------------
 377  */
 378 #define CONFIG_SYS_RCCR        0
 379
 380 /*
 381  * Init Memory Controller:
 382  *
 383  * Bank Bus     Machine PortSz  Device
 384  * ---- ---     ------- ------  ------
 385  *  0   60x     GPCM    16 bit  FLASH
 386  *  1   60x     GPCM     8 bit  NAND
 387  *  2   60x     SDRAM   32 bit  SDRAM
 388  *  3   60x     GPCM     8 bit  UART
 389  *
 390  */
 391
 392 #define SDRAM_MAX_SIZE  0x08000000      /* max. 128 MB          */
 393
 394 /* Minimum mask to separate preliminary
 395  * address ranges for CS[0:2]
 396  */
 397 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (32<<20)        /* less than 32 MB */
 398
 399 #define CONFIG_SYS_MPTPR       0x6600
 400
 401 /*-----------------------------------------------------------------------------
 402  * Address for Mode Register Set (MRS) command
 403  *-----------------------------------------------------------------------------
 404  */
 405 #define CONFIG_SYS_MRS_OFFS     0x00000110
 406
 407
 408 /* Bank 0 - FLASH
 409  */
 410 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)  |\
 411                          BRx_PS_8                       |\
 412                          BRx_MS_GPCM_P                  |\
 413                          BRx_V)
 414
 415 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)      |\
 416                          ORxG_SCY_6_CLK                 )
 417
 418 #if defined(CONFIG_CMD_NAND)
 419 /* Bank 1 - NAND Flash
 420 */
 421 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_NAND0_BASE
 422 #define CONFIG_SYS_NAND_SIZE            0x8000
 423
 424 #define CONFIG_SYS_OR_TIMING_NAND       0x000036
 425
 426 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
 427 #define CONFIG_SYS_OR1_PRELIM  (P2SZ_TO_AM(CONFIG_SYS_NAND_SIZE) | CONFIG_SYS_OR_TIMING_NAND )
 428 #endif
 429
 430 /* Bank 2 - 60x bus SDRAM
 431  */
 432 #define CONFIG_SYS_PSRT        0x20
 433 #define CONFIG_SYS_LSRT        0x20
 434
 435 #define CONFIG_SYS_BR2_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 436                          BRx_PS_32                      |\
 437                          BRx_MS_SDRAM_P                 |\
 438                          BRx_V)
 439
 440 #define CONFIG_SYS_OR2_PRELIM   CONFIG_SYS_OR2
 441
 442
 443 /* SDRAM initialization values
 444 */
 445 #define CONFIG_SYS_OR2    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 446                          ORxS_BPD_4                     |\
 447                          ORxS_ROWST_PBI0_A9             |\
 448                          ORxS_NUMR_12)
 449
 450 #define CONFIG_SYS_PSDMR  (PSDMR_SDAM_A14_IS_A5 |\
 451                          PSDMR_BSMA_A15_A17           |\
 452                          PSDMR_SDA10_PBI0_A10           |\
 453                          PSDMR_RFRC_5_CLK               |\
 454                          PSDMR_PRETOACT_2W              |\
 455                          PSDMR_ACTTORW_2W               |\
 456                          PSDMR_BL                       |\
 457                          PSDMR_LDOTOPRE_2C              |\
 458                          PSDMR_WRC_3C                   |\
 459                          PSDMR_CL_3)
 460
 461 /* Bank 3 - UART
 462 */
 463
 464 #define CONFIG_SYS_BR3_PRELIM  ((CONFIG_SYS_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
 465 #define CONFIG_SYS_OR3_PRELIM  (((-CONFIG_SYS_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
 466
 467 #endif  /* __CONFIG_H */