include/configs/IDS8247.h

   1 /*
   2  * (C) Copyright 2005
   3  * Heiko Schocher, DENX Software Engineering, <hs@denx.de>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC8260          1       /* This is a MPC8260 CPU                */
  37 #define CONFIG_MPC8272_FAMILY   1
  38 #define CONFIG_IDS8247          1
  39 #define CPU_ID_STR              "MPC8247"
  40 #define CONFIG_CPM2             1       /* Has a CPM2 */
  41
  42 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  43
  44 #define CONFIG_BOOTCOUNT_LIMIT
  45
  46 #define CONFIG_PREBOOT  "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
  47
  48 #undef  CONFIG_BOOTARGS
  49
  50 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  51         "netdev=eth0\0"                                                 \
  52         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  53                 "nfsroot=${serverip}:${rootpath}\0"                     \
  54         "ramargs=setenv bootargs root=/dev/ram rw "                     \
  55         "console=ttyS0,115200\0"                                        \
  56         "addip=setenv bootargs ${bootargs} "                            \
  57                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  58                 ":${hostname}:${netdev}:off panic=1\0"                  \
  59         "flash_nfs=run nfsargs addip;"                                  \
  60                 "bootm ${kernel_addr}\0"                                \
  61         "flash_self=run ramargs addip;"                                 \
  62                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
  63         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  64         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
  65         "bootfile=/tftpboot/IDS8247/uImage\0"                           \
  66         "kernel_addr=ff800000\0"                                        \
  67         "ramdisk_addr=ffa00000\0"                                       \
  68         ""
  69 #define CONFIG_BOOTCOMMAND      "run flash_self"
  70
  71 #define CONFIG_MISC_INIT_R      1
  72
  73 /* enable I2C and select the hardware/software driver */
  74 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
  75 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
  76 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
  77 #define CFG_I2C_SLAVE           0x7F
  78
  79 /*
  80  * Software (bit-bang) I2C driver configuration
  81  */
  82
  83 #define I2C_PORT        0               /* Port A=0, B=1, C=2, D=3 */
  84 #define I2C_ACTIVE      (iop->pdir |=  0x00000080)
  85 #define I2C_TRISTATE    (iop->pdir &= ~0x00000080)
  86 #define I2C_READ        ((iop->pdat & 0x00000080) != 0)
  87 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00000080; \
  88                         else    iop->pdat &= ~0x00000080
  89 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00000100; \
  90                         else    iop->pdat &= ~0x00000100
  91 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
  92
  93 #if 0
  94 #define CFG_I2C_EEPROM_ADDR     0x50
  95 #define CFG_I2C_EEPROM_ADDR_LEN 2
  96 #define CFG_EEPROM_PAGE_WRITE_BITS      4
  97 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10      /* and takes up to 10 msec */
  98
  99 #define CONFIG_I2C_X
 100 #endif
 101
 102 /*
 103  * select serial console configuration
 104  * use the extern UART for the console
 105  */
 106 #define CONFIG_CONS_INDEX       1
 107 #define CONFIG_BAUDRATE         115200
 108 /*
 109  * NS16550 Configuration
 110  */
 111 #define CFG_NS16550
 112 #define CFG_NS16550_SERIAL
 113
 114 #define CFG_NS16550_REG_SIZE    1
 115
 116 #define CFG_NS16550_CLK         14745600
 117
 118 #define CFG_UART_BASE   0xE0000000
 119 #define CFG_UART_SIZE   0x10000
 120
 121 #define CFG_NS16550_COM1        (CFG_UART_BASE + 0x8000)
 122
 123 /*
 124  * select ethernet configuration
 125  *
 126  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
 127  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
 128  * for FCC)
 129  *
 130  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
 131  * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
 132  */
 133 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
 134 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
 135 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
 136 #define CONFIG_ETHER_INDEX    2         /* which SCC/FCC channel for ethernet */
 137
 138 /*
 139  * - Rx-CLK is CLK13
 140  * - Tx-CLK is CLK14
 141  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 142  * - Enable Full Duplex in FSMR
 143  */
 144 # define CFG_CMXFCR_MASK        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
 145 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 146 # define CFG_CPMFCR_RAMTYPE     0
 147 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
 148
 149
 150 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 151 #define CONFIG_8260_CLKIN       66666666        /* in Hz */
 152
 153 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 154 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
 155
 156 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
 157
 158 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
 159
 160 /*
 161  * BOOTP options
 162  */
 163 #define CONFIG_BOOTP_SUBNETMASK
 164 #define CONFIG_BOOTP_GATEWAY
 165 #define CONFIG_BOOTP_HOSTNAME
 166 #define CONFIG_BOOTP_BOOTPATH
 167 #define CONFIG_BOOTP_BOOTFILESIZE
 168
 169
 170 /*
 171  * Command line configuration.
 172  */
 173 #include <config_cmd_default.h>
 174
 175 #define CONFIG_CMD_DHCP
 176 #define CONFIG_CMD_NFS
 177 #define CONFIG_CMD_NAND
 178 #define CONFIG_CMD_I2C
 179 #define CONFIG_CMD_SNTP
 180
 181
 182 /*
 183  * Miscellaneous configurable options
 184  */
 185 #define CFG_LONGHELP                    /* undef to save memory         */
 186 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 187 #if defined(CONFIG_CMD_KGDB)
 188 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 189 #else
 190 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 191 #endif
 192 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 193 #define CFG_MAXARGS     16              /* max number of command args   */
 194 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 195
 196 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 197 #define CFG_MEMTEST_END 0x0C00000       /* 4 ... 12 MB in DRAM  */
 198
 199 #define CFG_LOAD_ADDR   0x100000        /* default load address */
 200
 201 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 202
 203 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 204
 205 #define CFG_RESET_ADDRESS 0xFDFFFFFC    /* "bad" address                */
 206
 207 /*
 208  * For booting Linux, the board info and command line data
 209  * have to be in the first 8 MB of memory, since this is
 210  * the maximum mapped by the Linux kernel during initialization.
 211  */
 212 #define CFG_BOOTMAPSZ        (8 << 20)       /* Initial Memory map for Linux */
 213
 214
 215 /* What should the base address of the main FLASH be and how big is
 216  * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk
 217  * The main FLASH is whichever is connected to *CS0.
 218  */
 219 #define CFG_FLASH0_BASE 0xFFF00000
 220 #define CFG_FLASH0_SIZE 8
 221
 222 /* Flash bank size (for preliminary settings)
 223  */
 224 #define CFG_FLASH_SIZE CFG_FLASH0_SIZE
 225
 226 /*-----------------------------------------------------------------------
 227  * FLASH organization
 228  */
 229 #define CFG_MAX_FLASH_BANKS     1       /* max num of memory banks      */
 230 #define CFG_MAX_FLASH_SECT      64      /* max num of sects on one chip */
 231
 232 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 233 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 234
 235 /* Environment in flash */
 236 #define CFG_ENV_IS_IN_FLASH     1
 237 #define CFG_ENV_ADDR            (CFG_FLASH_BASE+0x60000)
 238 #define CFG_ENV_SIZE            0x20000
 239 #define CFG_ENV_SECT_SIZE       0x20000
 240
 241 /*-----------------------------------------------------------------------
 242  * NAND-FLASH stuff
 243  *-----------------------------------------------------------------------
 244  */
 245 #if defined(CONFIG_CMD_NAND)
 246
 247 #define CFG_NAND_LEGACY
 248 #define CFG_NAND0_BASE 0xE1000000
 249
 250 #define CFG_MAX_NAND_DEVICE     1       /* Max number of NAND devices           */
 251 #define SECTORSIZE 512
 252 #define NAND_NO_RB
 253
 254 #define ADDR_COLUMN 1
 255 #define ADDR_PAGE 2
 256 #define ADDR_COLUMN_PAGE 3
 257
 258 #define NAND_ChipID_UNKNOWN     0x00
 259 #define NAND_MAX_FLOORS 1
 260 #define NAND_MAX_CHIPS 1
 261
 262 #define NAND_DISABLE_CE(nand) do \
 263 { \
 264         *(((volatile __u8 *)(nand->IO_ADDR)) + 0xc) = 0; \
 265 } while(0)
 266
 267 #define NAND_ENABLE_CE(nand) do \
 268 { \
 269         *(((volatile __u8 *)(nand->IO_ADDR)) + 0x8) = 0; \
 270 } while(0)
 271
 272 #define NAND_CTL_CLRALE(nandptr) do \
 273 { \
 274         *(((volatile __u8 *)nandptr) + 0x8) = 0; \
 275 } while(0)
 276
 277 #define NAND_CTL_SETALE(nandptr) do \
 278 { \
 279         *(((volatile __u8 *)nandptr) + 0x9) = 0; \
 280 } while(0)
 281
 282 #define NAND_CTL_CLRCLE(nandptr) do \
 283 { \
 284         *(((volatile __u8 *)nandptr) + 0x8) = 0; \
 285 } while(0)
 286
 287 #define NAND_CTL_SETCLE(nandptr) do \
 288 { \
 289         *(((volatile __u8 *)nandptr) + 0xa) = 0; \
 290 } while(0)
 291
 292 #ifdef NAND_NO_RB
 293 /* constant delay (see also tR in the datasheet) */
 294 #define NAND_WAIT_READY(nand) do { \
 295         udelay(12); \
 296 } while (0)
 297 #else
 298 /* use the R/B pin */
 299 #endif
 300
 301 #define WRITE_NAND_COMMAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x2)) = (__u8)(d); } while(0)
 302 #define WRITE_NAND_ADDRESS(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x1)) = (__u8)(d); } while(0)
 303 #define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr + 0x0)) = (__u8)d; } while(0)
 304 #define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr + 0x0)))
 305
 306 #endif /* CONFIG_CMD_NAND */
 307
 308 /*-----------------------------------------------------------------------
 309  * Hard Reset Configuration Words
 310  *
 311  * if you change bits in the HRCW, you must also change the CFG_*
 312  * defines for the various registers affected by the HRCW e.g. changing
 313  * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 314  */
 315 #define CFG_HRCW_MASTER (HRCW_BPS01 | HRCW_BMS | HRCW_ISB100 | HRCW_APPC10 | HRCW_MODCK_H1000)
 316
 317 /* no slaves so just fill with zeros */
 318 #define CFG_HRCW_SLAVE1         0
 319 #define CFG_HRCW_SLAVE2         0
 320 #define CFG_HRCW_SLAVE3         0
 321 #define CFG_HRCW_SLAVE4         0
 322 #define CFG_HRCW_SLAVE5         0
 323 #define CFG_HRCW_SLAVE6         0
 324 #define CFG_HRCW_SLAVE7         0
 325
 326 /*-----------------------------------------------------------------------
 327  * Internal Memory Mapped Register
 328  */
 329 #define CFG_IMMR                0xF0000000
 330
 331 /*-----------------------------------------------------------------------
 332  * Definitions for initial stack pointer and data area (in DPRAM)
 333  */
 334 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 335 #define CFG_INIT_RAM_END        0x2000  /* End of used area in DPRAM    */
 336 #define CFG_GBL_DATA_SIZE       128 /* size in bytes reserved for initial data*/
 337 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 338 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 339
 340 /*-----------------------------------------------------------------------
 341  * Start addresses for the final memory configuration
 342  * (Set up by the startup code)
 343  * Please note that CFG_SDRAM_BASE _must_ start at 0
 344  *
 345  * 60x SDRAM is mapped at CFG_SDRAM_BASE
 346  */
 347 #define CFG_SDRAM_BASE          0x00000000
 348 #define CFG_FLASH_BASE          CFG_FLASH0_BASE
 349 #define CFG_MONITOR_BASE        TEXT_BASE
 350 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor */
 351 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()*/
 352
 353 /*
 354  * Internal Definitions
 355  *
 356  * Boot Flags
 357  */
 358 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH*/
 359 #define BOOTFLAG_WARM           0x02    /* Software reboot                 */
 360
 361
 362 /*-----------------------------------------------------------------------
 363  * Cache Configuration
 364  */
 365 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 366 #if defined(CONFIG_CMD_KGDB)
 367 # define CFG_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 368 #endif
 369
 370 /*-----------------------------------------------------------------------
 371  * HIDx - Hardware Implementation-dependent Registers                    2-11
 372  *-----------------------------------------------------------------------
 373  * HID0 also contains cache control - initially enable both caches and
 374  * invalidate contents, then the final state leaves only the instruction
 375  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 376  * but Soft reset does not.
 377  *
 378  * HID1 has only read-only information - nothing to set.
 379  */
 380
 381 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI)
 382 #define CFG_HID0_FINAL  0
 383 #define CFG_HID2        0
 384
 385 /*-----------------------------------------------------------------------
 386  * RMR - Reset Mode Register                                     5-5
 387  *-----------------------------------------------------------------------
 388  * turn on Checkstop Reset Enable
 389  */
 390 #define CFG_RMR         0
 391
 392 /*-----------------------------------------------------------------------
 393  * BCR - Bus Configuration                                       4-25
 394  *-----------------------------------------------------------------------
 395  */
 396 #define CFG_BCR         0
 397
 398 /*-----------------------------------------------------------------------
 399  * SIUMCR - SIU Module Configuration                             4-31
 400  *-----------------------------------------------------------------------
 401  */
 402 #define CFG_SIUMCR      (SIUMCR_DPPC00|SIUMCR_APPC10|SIUMCR_BCTLC01)
 403
 404 /*-----------------------------------------------------------------------
 405  * SYPCR - System Protection Control                             4-35
 406  * SYPCR can only be written once after reset!
 407  *-----------------------------------------------------------------------
 408  * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
 409  */
 410 #if defined(CONFIG_WATCHDOG)
 411 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 412                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 413 #else
 414 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 415                          SYPCR_SWRI|SYPCR_SWP)
 416 #endif /* CONFIG_WATCHDOG */
 417
 418 /*-----------------------------------------------------------------------
 419  * TMCNTSC - Time Counter Status and Control                     4-40
 420  *-----------------------------------------------------------------------
 421  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 422  * and enable Time Counter
 423  */
 424 #define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 425
 426 /*-----------------------------------------------------------------------
 427  * PISCR - Periodic Interrupt Status and Control                 4-42
 428  *-----------------------------------------------------------------------
 429  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 430  * Periodic timer
 431  */
 432 #define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 433
 434 /*-----------------------------------------------------------------------
 435  * SCCR - System Clock Control                                   9-8
 436  *-----------------------------------------------------------------------
 437  * Ensure DFBRG is Divide by 16
 438  */
 439 #define CFG_SCCR        (0x00000028 | SCCR_DFBRG01)
 440
 441 /*-----------------------------------------------------------------------
 442  * RCCR - RISC Controller Configuration                         13-7
 443  *-----------------------------------------------------------------------
 444  */
 445 #define CFG_RCCR        0
 446
 447 /*
 448  * Init Memory Controller:
 449  *
 450  * Bank Bus     Machine PortSz  Device
 451  * ---- ---     ------- ------  ------
 452  *  0   60x     GPCM    16 bit  FLASH
 453  *  1   60x     GPCM     8 bit  NAND
 454  *  2   60x     SDRAM   32 bit  SDRAM
 455  *  3   60x     GPCM     8 bit  UART
 456  *
 457  */
 458
 459 #define SDRAM_MAX_SIZE  0x08000000      /* max. 128 MB          */
 460
 461 /* Minimum mask to separate preliminary
 462  * address ranges for CS[0:2]
 463  */
 464 #define CFG_GLOBAL_SDRAM_LIMIT  (32<<20)        /* less than 32 MB */
 465
 466 #define CFG_MPTPR       0x6600
 467
 468 /*-----------------------------------------------------------------------------
 469  * Address for Mode Register Set (MRS) command
 470  *-----------------------------------------------------------------------------
 471  */
 472 #define CFG_MRS_OFFS    0x00000110
 473
 474
 475 /* Bank 0 - FLASH
 476  */
 477 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE & BRx_BA_MSK)  |\
 478                          BRx_PS_8                       |\
 479                          BRx_MS_GPCM_P                  |\
 480                          BRx_V)
 481
 482 #define CFG_OR0_PRELIM  (MEG_TO_AM(CFG_FLASH_SIZE)      |\
 483                          ORxG_SCY_6_CLK                 )
 484
 485 #if defined(CONFIG_CMD_NAND)
 486 /* Bank 1 - NAND Flash
 487 */
 488 #define CFG_NAND_BASE           CFG_NAND0_BASE
 489 #define CFG_NAND_SIZE           0x8000
 490
 491 #define CFG_OR_TIMING_NAND      0x000036
 492
 493 #define CFG_BR1_PRELIM  ((CFG_NAND_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
 494 #define CFG_OR1_PRELIM  (P2SZ_TO_AM(CFG_NAND_SIZE) | CFG_OR_TIMING_NAND )
 495 #endif
 496
 497 /* Bank 2 - 60x bus SDRAM
 498  */
 499 #define CFG_PSRT        0x20
 500 #define CFG_LSRT        0x20
 501
 502 #define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE & BRx_BA_MSK)  |\
 503                          BRx_PS_32                      |\
 504                          BRx_MS_SDRAM_P                 |\
 505                          BRx_V)
 506
 507 #define CFG_OR2_PRELIM  CFG_OR2
 508
 509
 510 /* SDRAM initialization values
 511 */
 512 #define CFG_OR2    ((~(CFG_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 513                          ORxS_BPD_4                     |\
 514                          ORxS_ROWST_PBI0_A10             |\
 515                          ORxS_NUMR_12)
 516
 517 #define CFG_PSDMR  (PSDMR_SDAM_A13_IS_A5 |\
 518                          PSDMR_BSMA_A15_A17           |\
 519                          PSDMR_SDA10_PBI0_A11         |\
 520                          PSDMR_RFRC_5_CLK               |\
 521                          PSDMR_PRETOACT_2W              |\
 522                          PSDMR_ACTTORW_2W               |\
 523                          PSDMR_BL                       |\
 524                          PSDMR_LDOTOPRE_2C              |\
 525                          PSDMR_WRC_3C                   |\
 526                          PSDMR_CL_3)
 527
 528 /* Bank 3 - UART
 529 */
 530
 531 #define CFG_BR3_PRELIM  ((CFG_UART_BASE & BRx_BA_MSK) | BRx_PS_8 | BRx_MS_GPCM_P | BRx_V  )
 532 #define CFG_OR3_PRELIM  (((-CFG_UART_SIZE) & ORxG_AM_MSK) | ORxG_CSNT | ORxG_SCY_1_CLK | ORxG_TRLX )
 533
 534 #endif  /* __CONFIG_H */