include/configs/IP860.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 /*
   9  * board/config.h - configuration options, board specific
  10  */
  11
  12 #ifndef __CONFIG_H
  13 #define __CONFIG_H
  14
  15 /*
  16  * High Level Configuration Options
  17  * (easy to change)
  18  */
  19
  20 #define CONFIG_MPC860           1       /* This is a MPC860 CPU         */
  21 #define CONFIG_IP860            1       /* ...on a IP860 board          */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0x10000000
  24
  25 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  26 #define CONFIG_RESET_PHY_R      1       /* Call reset_phy()             */
  27
  28 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  29 #define CONFIG_BAUDRATE         9600
  30 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  31
  32 #define CONFIG_PREBOOT  "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" \
  33 "\0load=tftp \"/tftpboot/u-boot.bin\"\0update=protect off 1:0;era 1:0;cp.b 100000 10000000 ${filesize}\0"
  34
  35 #undef  CONFIG_BOOTARGS
  36 #define CONFIG_BOOTCOMMAND                                                      \
  37         "bootp; "                                                               \
  38         "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "     \
  39         "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "   \
  40         "bootm"
  41
  42 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  43 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE            /* don't allow baudrate change  */
  44
  45 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  46
  47
  48 /* enable I2C and select the hardware/software driver */
  49 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
  50 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
  51 /*
  52  * Software (bit-bang) I2C driver configuration
  53  */
  54 #define PB_SCL          0x00000020      /* PB 26 */
  55 #define PB_SDA          0x00000010      /* PB 27 */
  56
  57 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
  58 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
  59 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
  60 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
  61 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
  62                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
  63 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
  64                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
  65 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
  66
  67
  68 # define CONFIG_SYS_I2C_SPEED           50000
  69 # define CONFIG_SYS_I2C_SLAVE           0xFE
  70 # define CONFIG_SYS_I2C_EEPROM_ADDR     0x50    /* EEPROM X24C16                */
  71 # define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1       /* bytes of address             */
  72 /* mask of address bits that overflow into the "EEPROM chip address"    */
  73 #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW     0x07
  74 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
  75 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* takes up to 10 msec */
  76
  77 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
  78
  79
  80 /*
  81  * Command line configuration.
  82  */
  83 #include <config_cmd_default.h>
  84
  85 #define CONFIG_CMD_BEDBUG
  86 #define CONFIG_CMD_I2C
  87 #define CONFIG_CMD_EEPROM
  88 #define CONFIG_CMD_NFS
  89 #define CONFIG_CMD_SNTP
  90
  91 /*
  92  * BOOTP options
  93  */
  94 #define CONFIG_BOOTP_SUBNETMASK
  95 #define CONFIG_BOOTP_GATEWAY
  96 #define CONFIG_BOOTP_HOSTNAME
  97 #define CONFIG_BOOTP_BOOTPATH
  98
  99 /*
 100  * Miscellaneous configurable options
 101  */
 102 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 103 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt       */
 104 #if defined(CONFIG_CMD_KGDB)
 105 #define CONFIG_SYS_CBSIZE       1024            /* Console I/O Buffer Size      */
 106 #else
 107 #define CONFIG_SYS_CBSIZE       256             /* Console I/O Buffer Size      */
 108 #endif
 109 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 110 #define CONFIG_SYS_MAXARGS      16              /* max number of command args   */
 111 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 112
 113 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on     */
 114 #define CONFIG_SYS_MEMTEST_END          0x00F00000      /* 1 ... 15MB in DRAM   */
 115
 116 #define CONFIG_SYS_LOAD_ADDR            0x00100000      /* default load address */
 117
 118 #define CONFIG_SYS_PIO_MODE             0       /* IDE interface in PIO Mode 0  */
 119
 120 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 121
 122 /*
 123  * Low Level Configuration Settings
 124  * (address mappings, register initial values, etc.)
 125  * You should know what you are doing if you make changes here.
 126  */
 127 /*-----------------------------------------------------------------------
 128  * Internal Memory Mapped Register
 129  */
 130 #define CONFIG_SYS_IMMR         0xF1000000      /* Non-standard value!! */
 131
 132 /*-----------------------------------------------------------------------
 133  * Definitions for initial stack pointer and data area (in DPRAM)
 134  */
 135 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 136 #define CONFIG_SYS_INIT_RAM_SIZE        0x2F00  /* Size of used area in DPRAM   */
 137 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 138 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 139
 140 /*-----------------------------------------------------------------------
 141  * Start addresses for the final memory configuration
 142  * (Set up by the startup code)
 143  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 144  */
 145 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 146 #define CONFIG_SYS_FLASH_BASE           0x10000000
 147 #ifdef  DEBUG
 148 #define CONFIG_SYS_MONITOR_LEN          (512 << 10)     /* Reserve 512 kB for Monitor   */
 149 #else
 150 #if 0 /* need more space for I2C tests */
 151 #define CONFIG_SYS_MONITOR_LEN          (128 << 10)     /* Reserve 128 kB for Monitor   */
 152 #else
 153 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)
 154 #endif
 155 #endif
 156 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
 157 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 158
 159 /*
 160  * For booting Linux, the board info and command line data
 161  * have to be in the first 8 MB of memory, since this is
 162  * the maximum mapped by the Linux kernel during initialization.
 163  */
 164 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 165 /*-----------------------------------------------------------------------
 166  * FLASH organization
 167  */
 168 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 169 #define CONFIG_SYS_MAX_FLASH_SECT       124     /* max number of sectors on one chip    */
 170
 171 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 172 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 173
 174 #undef  CONFIG_ENV_IS_IN_FLASH
 175 #undef  CONFIG_ENV_IS_IN_NVRAM
 176 #undef  CONFIG_ENV_IS_IN_NVRAM
 177 #undef  DEBUG_I2C
 178 #define CONFIG_ENV_IS_IN_EEPROM
 179
 180 #ifdef  CONFIG_ENV_IS_IN_NVRAM
 181 #define CONFIG_ENV_ADDR         0x20000000      /* use SRAM     */
 182 #define CONFIG_ENV_SIZE         (16<<10)        /* use 16 kB    */
 183 #endif  /* CONFIG_ENV_IS_IN_NVRAM */
 184
 185 #ifdef  CONFIG_ENV_IS_IN_EEPROM
 186 #define CONFIG_ENV_OFFSET                512    /* Leave 512 bytes free for other data  */
 187 #define CONFIG_ENV_SIZE         1536    /* Use remaining space                  */
 188 #endif  /* CONFIG_ENV_IS_IN_EEPROM */
 189
 190 /*-----------------------------------------------------------------------
 191  * Cache Configuration
 192  */
 193 #define CONFIG_SYS_CACHELINE_SIZE       16      /* For all MPC8xx CPUs                  */
 194 #if defined(CONFIG_CMD_KGDB)
 195 #define CONFIG_SYS_CACHELINE_SHIFT      4       /* log base 2 of the above value        */
 196 #endif
 197 #define CONFIG_SYS_DELAYED_ICACHE       1       /* enable ICache not before
 198                                                  * running in RAM.
 199                                                  */
 200
 201 /*-----------------------------------------------------------------------
 202  * SYPCR - System Protection Control                            11-9
 203  * SYPCR can only be written once after reset!
 204  *-----------------------------------------------------------------------
 205  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 206  * +0x0004
 207  */
 208 #if defined(CONFIG_WATCHDOG)
 209 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 210                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 211 #else
 212 #define CONFIG_SYS_SYPCR        (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 213 #endif
 214
 215 /*-----------------------------------------------------------------------
 216  * SIUMCR - SIU Module Configuration                            11-6
 217  *-----------------------------------------------------------------------
 218  * +0x0000 => 0x80600800
 219  */
 220 #define CONFIG_SYS_SIUMCR       (SIUMCR_EARB   | SIUMCR_EARP0 | \
 221                          SIUMCR_DBGC11 | SIUMCR_MLRC10)
 222
 223 /*-----------------------------------------------------------------------
 224  * Clock Setting - get clock frequency from Board Revision Register
 225  *-----------------------------------------------------------------------
 226  */
 227 #ifndef __ASSEMBLY__
 228 extern  unsigned long           ip860_get_clk_freq (void);
 229 #endif
 230 #define CONFIG_8xx_GCLK_FREQ    ip860_get_clk_freq()
 231
 232 /*-----------------------------------------------------------------------
 233  * TBSCR - Time Base Status and Control                         11-26
 234  *-----------------------------------------------------------------------
 235  * Clear Reference Interrupt Status, Timebase freezing enabled
 236  * +0x0200 => 0x00C2
 237  */
 238 #define CONFIG_SYS_TBSCR        (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 239
 240 /*-----------------------------------------------------------------------
 241  * PISCR - Periodic Interrupt Status and Control                11-31
 242  *-----------------------------------------------------------------------
 243  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 244  * +0x0240 => 0x0082
 245  */
 246 #define CONFIG_SYS_PISCR        (PISCR_PS | PISCR_PITF)
 247
 248 /*-----------------------------------------------------------------------
 249  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 250  *-----------------------------------------------------------------------
 251  * Reset PLL lock status sticky bit, timer expired status bit and timer
 252  * interrupt status bit, set PLL multiplication factor !
 253  */
 254 /* +0x0286 => was: 0x0000D000 */
 255 #define CONFIG_SYS_PLPRCR                                                       \
 256                 (       PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |    \
 257                         /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |            \
 258                         PLPRCR_CSR   | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/   \
 259                 )
 260
 261 /*-----------------------------------------------------------------------
 262  * SCCR - System Clock and reset Control Register               15-27
 263  *-----------------------------------------------------------------------
 264  * Set clock output, timebase and RTC source and divider,
 265  * power management and some other internal clocks
 266  */
 267 #define SCCR_MASK       SCCR_EBDF11
 268 #define CONFIG_SYS_SCCR (SCCR_COM00     |   SCCR_TBS      |     \
 269                          SCCR_RTDIV     |   SCCR_RTSEL    |     \
 270                          /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
 271                          SCCR_EBDF00    |   SCCR_DFSYNC00 |     \
 272                          SCCR_DFBRG00   |   SCCR_DFNL000  |     \
 273                          SCCR_DFNH000)
 274
 275 /*-----------------------------------------------------------------------
 276  * RTCSC - Real-Time Clock Status and Control Register          11-27
 277  *-----------------------------------------------------------------------
 278  */
 279 /* +0x0220 => 0x00C3 */
 280 #define CONFIG_SYS_RTCSC        (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 281
 282
 283 /*-----------------------------------------------------------------------
 284  * RCCR - RISC Controller Configuration Register                19-4
 285  *-----------------------------------------------------------------------
 286  */
 287 /* +0x09C4 => TIMEP=1 */
 288 #define CONFIG_SYS_RCCR 0x0100
 289
 290 /*-----------------------------------------------------------------------
 291  * RMDS - RISC Microcode Development Support Control Register
 292  *-----------------------------------------------------------------------
 293  */
 294 #define CONFIG_SYS_RMDS 0
 295
 296 /*-----------------------------------------------------------------------
 297  * DER - Debug Event Register
 298  *-----------------------------------------------------------------------
 299  *
 300  */
 301 #define CONFIG_SYS_DER  0
 302
 303 /*
 304  * Init Memory Controller:
 305  */
 306
 307 /*
 308  * MAMR settings for SDRAM      - 16-14
 309  * => 0xC3804114
 310  */
 311
 312 /* periodic timer for refresh */
 313 #define CONFIG_SYS_MAMR_PTA     0xC3
 314
 315 #define CONFIG_SYS_MAMR ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE       |   \
 316                          MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |   \
 317                          MAMR_RLFA_1X    | MAMR_WLFA_1X    | MAMR_TLFA_4X)
 318 /*
 319  * BR1 and OR1 (FLASH)
 320  */
 321 #define FLASH_BASE              0x10000000      /* FLASH bank #0        */
 322
 323 /* used to re-map FLASH
 324  * restrict access enough to keep SRAM working (if any)
 325  * but not too much to meddle with FLASH accesses
 326  */
 327 /* allow for max 8 MB of Flash */
 328 #define CONFIG_SYS_REMAP_OR_AM          0xFF800000      /* OR addr mask */
 329 #define CONFIG_SYS_PRELIM_OR_AM 0xFF800000      /* OR addr mask */
 330
 331 #define CONFIG_SYS_OR_TIMING_FLASH      (OR_CSNT_SAM | OR_ACS_DIV2 | OR_BI | OR_SCY_6_CLK)
 332
 333 #define CONFIG_SYS_OR0_REMAP    (CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
 334 #define CONFIG_SYS_OR0_PRELIM   (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
 335 /* 16 bit, bank valid */
 336 #define CONFIG_SYS_BR0_PRELIM   ((FLASH_BASE & BR_BA_MSK) | BR_PS_32 | BR_V )
 337
 338 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR0_PRELIM
 339 #define CONFIG_SYS_BR1_PRELIM   CONFIG_SYS_BR0_PRELIM
 340
 341 /*
 342  * BR2/OR2 - SDRAM
 343  */
 344 #define SDRAM_BASE              0x00000000      /* SDRAM bank */
 345 #define SDRAM_PRELIM_OR_AM      0xF8000000      /* map max. 128 MB */
 346 #define SDRAM_TIMING            0x00000A00      /* SDRAM-Timing */
 347
 348 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB SDRAM */
 349
 350 #define CONFIG_SYS_OR2          (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
 351 #define CONFIG_SYS_BR2          ((SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 352
 353 /*
 354  * BR3/OR3 - SRAM (16 bit)
 355  */
 356 #define SRAM_BASE       0x20000000
 357 #define CONFIG_SYS_OR3          0xFFF00130              /* BI/SCY = 5/TRLX (internal) */
 358 #define CONFIG_SYS_BR3          ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 359 #define SRAM_SIZE       (1 + (~(CONFIG_SYS_OR3 & BR_BA_MSK)))
 360 #define CONFIG_SYS_OR3_PRELIM   CONFIG_SYS_OR3                  /* Make sure to map early */
 361 #define CONFIG_SYS_BR3_PRELIM   CONFIG_SYS_BR3                  /* in case it's used for ENV */
 362 #define CONFIG_SYS_SRAM_BASE    SRAM_BASE
 363 #define CONFIG_SYS_SRAM_SIZE    SRAM_SIZE
 364
 365 /*
 366  * BR4/OR4 - Board Control & Status (8 bit)
 367  */
 368 #define BCSR_BASE       0xFC000000
 369 #define CONFIG_SYS_OR4          0xFFFF0120              /* BI (internal) */
 370 #define CONFIG_SYS_BR4          ((BCSR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 371
 372 /*
 373  * BR5/OR5 - IP Slot A/B (16 bit)
 374  */
 375 #define IP_SLOT_BASE    0x40000000
 376 #define CONFIG_SYS_OR5          0xFE00010C              /* SETA/TRLX/BI/ SCY=0 (external) */
 377 #define CONFIG_SYS_BR5          ((IP_SLOT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 378
 379 /*
 380  * BR6/OR6 - VME STD  (16 bit)
 381  */
 382 #define VME_STD_BASE    0xFE000000
 383 #define CONFIG_SYS_OR6          0xFF00010C              /* SETA/TRLX/BI/SCY=0  (external) */
 384 #define CONFIG_SYS_BR6          ((VME_STD_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 385
 386 /*
 387  * BR7/OR7 - SHORT I/O + RTC + IACK  (16 bit)
 388  */
 389 #define VME_SHORT_BASE  0xFF000000
 390 #define CONFIG_SYS_OR7          0xFF00010C              /* SETA/TRLX/BI/ SCY=0 (external) */
 391 #define CONFIG_SYS_BR7          ((VME_SHORT_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 392
 393 /*-----------------------------------------------------------------------
 394  * Board Control and Status Region:
 395  *-----------------------------------------------------------------------
 396  */
 397 #ifndef __ASSEMBLY__
 398 typedef struct ip860_bcsr_s {
 399         unsigned char   shmem_addr;     /* +00 shared memory address register   */
 400         unsigned char   reserved0;
 401         unsigned char   mbox_addr;      /* +02 mailbox address register         */
 402         unsigned char   reserved1;
 403         unsigned char   vme_int_mask;   /* +04 VME Bus interrupt mask register  */
 404         unsigned char   reserved2;
 405         unsigned char   vme_int_pend;   /* +06 VME interrupt pending register   */
 406         unsigned char   reserved3;
 407         unsigned char   bd_int_mask;    /* +08 board interrupt mask register    */
 408         unsigned char   reserved4;
 409         unsigned char   bd_int_pend;    /* +0A board interrupt pending register */
 410         unsigned char   reserved5;
 411         unsigned char   bd_ctrl;        /* +0C board control register           */
 412         unsigned char   reserved6;
 413         unsigned char   bd_status;      /* +0E board status  register           */
 414         unsigned char   reserved7;
 415         unsigned char   vme_irq;        /* +10 VME interrupt request register   */
 416         unsigned char   reserved8;
 417         unsigned char   vme_ivec;       /* +12 VME interrupt vector register    */
 418         unsigned char   reserved9;
 419         unsigned char   cli_mbox;       /* +14 clear mailbox irq                */
 420         unsigned char   reservedA;
 421         unsigned char   rtc;            /* +16 RTC control register             */
 422         unsigned char   reservedB;
 423         unsigned char   mbox_data;      /* +18 mailbox read/write register      */
 424         unsigned char   reservedC;
 425         unsigned char   wd_trigger;     /* +1A Watchdog trigger register        */
 426         unsigned char   reservedD;
 427         unsigned char   rmw_req;        /* +1C RMW request register             */
 428         unsigned char   reservedE;
 429         unsigned char   bd_rev;         /* +1E Board Revision register          */
 430 } ip860_bcsr_t;
 431 #endif  /* __ASSEMBLY__ */
 432
 433 /*-----------------------------------------------------------------------
 434  * Board Control Register: bd_ctrl (Offset 0x0C)
 435  *-----------------------------------------------------------------------
 436  */
 437 #define BD_CTRL_IPLSE   0x80    /* IP Slot Long Select Enable           */
 438 #define BD_CTRL_WDOGE   0x40    /* Watchdog Enable                      */
 439 #define BD_CTRL_FLWE    0x20    /* Flash Write Enable                   */
 440 #define BD_CTRL_RWDN    0x10    /* VMEBus Requester Release When Done Enable */
 441
 442 #endif  /* __CONFIG_H */