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1 /*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #ifndef __CONFIG_H
25 #define __CONFIG_H
26
27 /*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
32 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33 #define CONFIG_ICECUBE 1 /* ... on IceCube board */
34
35 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
36
37 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
38 #define BOOTFLAG_WARM 0x02 /* Software reboot */
39
40 #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
41 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
42 # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
43 #endif
44
45 /*
46 * Serial console configuration
47 */
48 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
49 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
50 #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
51
52
53 #ifdef CONFIG_MPC5200 /* MPC5100 PCI is not supported yet. */
54 /*
55 * PCI Mapping:
56 * 0x40000000 - 0x4fffffff - PCI Memory
57 * 0x50000000 - 0x50ffffff - PCI IO Space
58 */
59 #define CONFIG_PCI
60
61 #if defined(CONFIG_PCI)
62 #define CONFIG_PCI_PNP 1
63 #define CONFIG_PCI_SCAN_SHOW 1
64
65 #define CONFIG_PCI_MEM_BUS 0x40000000
66 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
67 #define CONFIG_PCI_MEM_SIZE 0x10000000
68
69 #define CONFIG_PCI_IO_BUS 0x50000000
70 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
71 #define CONFIG_PCI_IO_SIZE 0x01000000
72 #define ADD_PCI_CMD CFG_CMD_PCI
73 #endif
74
75 #define CFG_XLB_PIPELINING 1
76
77 #define CONFIG_NET_MULTI 1
78 #define CONFIG_MII 1
79 #define CONFIG_EEPRO100 1
80 #define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
81 #define CONFIG_NS8382X 1
82
83 #else /* MPC5100 */
84
85 #define CONFIG_MII 1
86 #define ADD_PCI_CMD 0 /* no CFG_CMD_PCI */
87
88 #endif
89
90 /* Partitions */
91 #define CONFIG_MAC_PARTITION
92 #define CONFIG_DOS_PARTITION
93 #define CONFIG_ISO_PARTITION
94
95 /* USB */
96 #if 1
97 #define CONFIG_USB_OHCI
98 #define ADD_USB_CMD CFG_CMD_USB | CFG_CMD_FAT
99 #define CONFIG_USB_STORAGE
100 #else
101 #define ADD_USB_CMD 0
102 #endif
103
104 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
105
106 /*
107 * Supported commands
108 */
109 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
110 CFG_CMD_EEPROM | \
111 CFG_CMD_FAT | \
112 CFG_CMD_I2C | \
113 CFG_CMD_IDE | \
114 CFG_CMD_NFS | \
115 CFG_CMD_SNTP | \
116 ADD_PCI_CMD | \
117 ADD_USB_CMD )
118
119 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
120 #include <cmd_confdefs.h>
121
122 #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
123 # define CFG_LOWBOOT 1
124 # define CFG_LOWBOOT16 1
125 #endif
126 #if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
127 #if defined(CONFIG_LITE5200B)
128 # error CFG_LOWBOOT08 is incompatible with the Lite5200B
129 #else
130 # define CFG_LOWBOOT 1
131 # define CFG_LOWBOOT08 1
132 #endif
133 #endif
134
135 /*
136 * Autobooting
137 */
138 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
139
140 #define CONFIG_PREBOOT "echo;" \
141 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
142 "echo"
143
144 #undef CONFIG_BOOTARGS
145
146 #define CONFIG_EXTRA_ENV_SETTINGS \
147 "netdev=eth0\0" \
148 "nfsargs=setenv bootargs root=/dev/nfs rw " \
149 "nfsroot=${serverip}:${rootpath}\0" \
150 "ramargs=setenv bootargs root=/dev/ram rw\0" \
151 "addip=setenv bootargs ${bootargs} " \
152 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
153 ":${hostname}:${netdev}:off panic=1\0" \
154 "flash_nfs=run nfsargs addip;" \
155 "bootm ${kernel_addr}\0" \
156 "flash_self=run ramargs addip;" \
157 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
158 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
159 "rootpath=/opt/eldk/ppc_82xx\0" \
160 "bootfile=/tftpboot/MPC5200/uImage\0" \
161 ""
162
163 #define CONFIG_BOOTCOMMAND "run flash_self"
164
165 #if defined(CONFIG_MPC5200)
166 /*
167 * IPB Bus clocking configuration.
168 */
169 #if defined(CONFIG_LITE5200B)
170 #define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
171 #else
172 #undef CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
173 #endif
174 #endif /* CONFIG_MPC5200 */
175
176 /* pass open firmware flat tree */
177 #define CONFIG_OF_FLAT_TREE 1
178 #define CONFIG_OF_BOARD_SETUP 1
179
180 /* maximum size of the flat tree (8K) */
181 #define OF_FLAT_TREE_MAX_SIZE 8192
182
183 #define OF_CPU "PowerPC,5200@0"
184 #define OF_SOC "soc5200@f0000000"
185 #define OF_TBCLK (bd->bi_busfreq / 4)
186 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
187
188 /*
189 * I2C configuration
190 */
191 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
192 #define CFG_I2C_MODULE 2 /* Select I2C module #1 or #2 */
193
194 #define CFG_I2C_SPEED 100000 /* 100 kHz */
195 #define CFG_I2C_SLAVE 0x7F
196
197 /*
198 * EEPROM configuration
199 */
200 #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */
201 #define CFG_I2C_EEPROM_ADDR_LEN 1
202 #define CFG_EEPROM_PAGE_WRITE_BITS 3
203 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 70
204
205 /*
206 * Flash configuration
207 */
208 #if defined(CONFIG_LITE5200B)
209 #define CFG_FLASH_BASE 0xFE000000
210 #define CFG_FLASH_SIZE 0x01000000
211 #if !defined(CFG_LOWBOOT)
212 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01760000 + 0x00800000)
213 #else /* CFG_LOWBOOT */
214 #if defined(CFG_LOWBOOT08)
215 # error CFG_LOWBOOT08 is incompatible with the Lite5200B
216 #endif
217 #if defined(CFG_LOWBOOT16)
218 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x01060000)
219 #endif
220 #endif /* CFG_LOWBOOT */
221 #else /* !CONFIG_LITE5200B (IceCube)*/
222 #define CFG_FLASH_BASE 0xFF000000
223 #define CFG_FLASH_SIZE 0x01000000
224 #if !defined(CFG_LOWBOOT)
225 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00740000 + 0x00800000)
226 #else /* CFG_LOWBOOT */
227 #if defined(CFG_LOWBOOT08)
228 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000 + 0x00800000)
229 #endif
230 #if defined(CFG_LOWBOOT16)
231 #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00040000)
232 #endif
233 #endif /* CFG_LOWBOOT */
234 #endif /* CONFIG_LITE5200B */
235 #define CFG_MAX_FLASH_BANKS 2 /* max num of memory banks */
236
237 #define CFG_MAX_FLASH_SECT 128 /* max num of sects on one chip */
238
239 #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
240 #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
241
242 #undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
243
244 #if defined(CONFIG_LITE5200B)
245 #define CFG_FLASH_CFI_DRIVER
246 #define CFG_FLASH_CFI
247 #define CFG_FLASH_BANKS_LIST {CFG_CS1_START,CFG_CS0_START}
248 #endif
249
250
251 /*
252 * Environment settings
253 */
254 #define CFG_ENV_IS_IN_FLASH 1
255 #define CFG_ENV_SIZE 0x10000
256 #if defined(CONFIG_LITE5200B)
257 #define CFG_ENV_SECT_SIZE 0x20000
258 #else
259 #define CFG_ENV_SECT_SIZE 0x10000
260 #endif
261 #define CONFIG_ENV_OVERWRITE 1
262
263 /*
264 * Memory map
265 */
266 #define CFG_MBAR 0xF0000000
267 #define CFG_SDRAM_BASE 0x00000000
268 #define CFG_DEFAULT_MBAR 0x80000000
269
270 /* Use SRAM until RAM will be available */
271 #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM
272 #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
273
274
275 #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
276 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
277 #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
278
279 #define CFG_MONITOR_BASE TEXT_BASE
280 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
281 # define CFG_RAMBOOT 1
282 #endif
283
284 #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
285 #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
286 #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
287
288 /*
289 * Ethernet configuration
290 */
291 #define CONFIG_MPC5xxx_FEC 1
292 /*
293 * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
294 */
295 /* #define CONFIG_FEC_10MBIT 1 */
296 #define CONFIG_PHY_ADDR 0x00
297 #if defined(CONFIG_LITE5200B)
298 #define CONFIG_FEC_MII100 1
299 #endif
300
301 /*
302 * GPIO configuration
303 */
304 #ifdef CONFIG_MPC5200_DDR
305 #define CFG_GPS_PORT_CONFIG 0x90000004
306 #else
307 #define CFG_GPS_PORT_CONFIG 0x10000004
308 #endif
309
310 /*
311 * Miscellaneous configurable options
312 */
313 #define CFG_LONGHELP /* undef to save memory */
314 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
315 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
316 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
317 #else
318 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
319 #endif
320 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
321 #define CFG_MAXARGS 16 /* max number of command args */
322 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
323
324 #define CFG_MEMTEST_START 0x00100000 /* memtest works on */
325 #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
326
327 #define CFG_LOAD_ADDR 0x100000 /* default load address */
328
329 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
330
331 /*
332 * Various low-level settings
333 */
334 #if defined(CONFIG_MPC5200)
335 #define CFG_HID0_INIT HID0_ICE | HID0_ICFI
336 #define CFG_HID0_FINAL HID0_ICE
337 #else
338 #define CFG_HID0_INIT 0
339 #define CFG_HID0_FINAL 0
340 #endif
341
342 #if defined(CONFIG_LITE5200B)
343 #define CFG_CS1_START CFG_FLASH_BASE
344 #define CFG_CS1_SIZE CFG_FLASH_SIZE
345 #define CFG_CS1_CFG 0x00047800
346 #define CFG_CS0_START (CFG_FLASH_BASE + CFG_FLASH_SIZE)
347 #define CFG_CS0_SIZE CFG_FLASH_SIZE
348 #define CFG_BOOTCS_START CFG_CS0_START
349 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
350 #define CFG_BOOTCS_CFG 0x00047800
351 #else /* IceCube aka Lite5200 */
352 #ifdef CONFIG_MPC5200_DDR
353
354 #define CFG_BOOTCS_START (CFG_CS1_START + CFG_CS1_SIZE)
355 #define CFG_BOOTCS_SIZE 0x00800000
356 #define CFG_BOOTCS_CFG 0x00047801
357 #define CFG_CS1_START CFG_FLASH_BASE
358 #define CFG_CS1_SIZE 0x00800000
359 #define CFG_CS1_CFG 0x00047800
360
361 #else /* !CONFIG_MPC5200_DDR */
362
363 #define CFG_BOOTCS_START CFG_FLASH_BASE
364 #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE
365 #define CFG_BOOTCS_CFG 0x00047801
366 #define CFG_CS0_START CFG_FLASH_BASE
367 #define CFG_CS0_SIZE CFG_FLASH_SIZE
368
369 #endif /* CONFIG_MPC5200_DDR */
370 #endif /*CONFIG_LITE5200B */
371
372 #define CFG_CS_BURST 0x00000000
373 #define CFG_CS_DEADCYCLE 0x33333333
374
375 #define CFG_RESET_ADDRESS 0xff000000
376
377 /*-----------------------------------------------------------------------
378 * USB stuff
379 *-----------------------------------------------------------------------
380 */
381 #define CONFIG_USB_CLOCK 0x0001BBBB
382 #define CONFIG_USB_CONFIG 0x00001000
383
384 /*-----------------------------------------------------------------------
385 * IDE/ATA stuff Supports IDE harddisk
386 *-----------------------------------------------------------------------
387 */
388
389 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
390
391 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
392 #undef CONFIG_IDE_LED /* LED for ide not supported */
393
394 #define CONFIG_IDE_RESET /* reset for ide supported */
395 #define CONFIG_IDE_PREINIT
396
397 #define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */
398 #define CFG_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
399
400 #define CFG_ATA_IDE0_OFFSET 0x0000
401
402 #define CFG_ATA_BASE_ADDR MPC5XXX_ATA
403
404 /* Offset for data I/O */
405 #define CFG_ATA_DATA_OFFSET (0x0060)
406
407 /* Offset for normal register accesses */
408 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET)
409
410 /* Offset for alternate registers */
411 #define CFG_ATA_ALT_OFFSET (0x005C)
412
413 /* Interval between registers */
414 #define CFG_ATA_STRIDE 4
415
416 #define CONFIG_ATAPI 1
417
418 #endif /* __CONFIG_H */