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1 /*
2 * (C) Copyright 2003-2005
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24 #ifndef __CONFIG_H
25 #define __CONFIG_H
26
27 /*
28 * High Level Configuration Options
29 * (easy to change)
30 */
31
32 #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */
33 #define CONFIG_MPC5200 1 /* (more precisely a MPC5200 CPU) */
34 #define CONFIG_ICECUBE 1 /* ... on IceCube board */
35
36 #define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */
37
38 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
39 #define BOOTFLAG_WARM 0x02 /* Software reboot */
40
41 #define CONFIG_HIGH_BATS 1 /* High BATs supported */
42
43 /*
44 * Serial console configuration
45 */
46 #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */
47 #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */
48 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
49
50
51 /*
52 * PCI Mapping:
53 * 0x40000000 - 0x4fffffff - PCI Memory
54 * 0x50000000 - 0x50ffffff - PCI IO Space
55 */
56 #define CONFIG_PCI
57
58 #if defined(CONFIG_PCI)
59 #define CONFIG_PCI_PNP 1
60 #define CONFIG_PCI_SCAN_SHOW 1
61 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
62
63 #define CONFIG_PCI_MEM_BUS 0x40000000
64 #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
65 #define CONFIG_PCI_MEM_SIZE 0x10000000
66
67 #define CONFIG_PCI_IO_BUS 0x50000000
68 #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
69 #define CONFIG_PCI_IO_SIZE 0x01000000
70 #endif
71
72 #define CONFIG_SYS_XLB_PIPELINING 1
73
74 #define CONFIG_NET_MULTI 1
75 #define CONFIG_MII 1
76 #define CONFIG_EEPRO100 1
77 #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
78 #define CONFIG_NS8382X 1
79
80 /* Partitions */
81 #define CONFIG_MAC_PARTITION
82 #define CONFIG_DOS_PARTITION
83 #define CONFIG_ISO_PARTITION
84
85 /* USB */
86 #define CONFIG_USB_OHCI_NEW
87 #define CONFIG_USB_STORAGE
88 #define CONFIG_SYS_OHCI_BE_CONTROLLER
89 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
90 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1
91 #define CONFIG_SYS_USB_OHCI_REGS_BASE MPC5XXX_USB
92 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "mpc5200"
93 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
94
95 #define CONFIG_TIMESTAMP /* Print image info with timestamp */
96
97
98 /*
99 * BOOTP options
100 */
101 #define CONFIG_BOOTP_BOOTFILESIZE
102 #define CONFIG_BOOTP_BOOTPATH
103 #define CONFIG_BOOTP_GATEWAY
104 #define CONFIG_BOOTP_HOSTNAME
105
106
107 /*
108 * Command line configuration.
109 */
110 #include <config_cmd_default.h>
111
112 #define CONFIG_CMD_EEPROM
113 #define CONFIG_CMD_FAT
114 #define CONFIG_CMD_I2C
115 #define CONFIG_CMD_IDE
116 #define CONFIG_CMD_NFS
117 #define CONFIG_CMD_SNTP
118 #define CONFIG_CMD_USB
119
120 #if defined(CONFIG_PCI)
121 #define CONFIG_CMD_PCI
122 #endif
123
124
125 #if (TEXT_BASE == 0xFF000000) /* Boot low with 16 MB Flash */
126 # define CONFIG_SYS_LOWBOOT 1
127 # define CONFIG_SYS_LOWBOOT16 1
128 #endif
129 #if (TEXT_BASE == 0xFF800000) /* Boot low with 8 MB Flash */
130 #if defined(CONFIG_LITE5200B)
131 # error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
132 #else
133 # define CONFIG_SYS_LOWBOOT 1
134 # define CONFIG_SYS_LOWBOOT08 1
135 #endif
136 #endif
137
138 /*
139 * Autobooting
140 */
141 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
142
143 #define CONFIG_PREBOOT "echo;" \
144 "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
145 "echo"
146
147 #undef CONFIG_BOOTARGS
148
149 #define CONFIG_EXTRA_ENV_SETTINGS \
150 "netdev=eth0\0" \
151 "nfsargs=setenv bootargs root=/dev/nfs rw " \
152 "nfsroot=${serverip}:${rootpath}\0" \
153 "ramargs=setenv bootargs root=/dev/ram rw\0" \
154 "addip=setenv bootargs ${bootargs} " \
155 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
156 ":${hostname}:${netdev}:off panic=1\0" \
157 "flash_nfs=run nfsargs addip;" \
158 "bootm ${kernel_addr}\0" \
159 "flash_self=run ramargs addip;" \
160 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
161 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \
162 "rootpath=/opt/eldk/ppc_82xx\0" \
163 "bootfile=/tftpboot/MPC5200/uImage\0" \
164 ""
165
166 #define CONFIG_BOOTCOMMAND "run flash_self"
167
168 /*
169 * IPB Bus clocking configuration.
170 */
171 #if defined(CONFIG_LITE5200B)
172 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
173 #else
174 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
175 #endif
176
177 /* pass open firmware flat tree */
178 #define CONFIG_OF_LIBFDT 1
179 #define CONFIG_OF_BOARD_SETUP 1
180
181 #define OF_CPU "PowerPC,5200@0"
182 #define OF_SOC "soc5200@f0000000"
183 #define OF_TBCLK (bd->bi_busfreq / 4)
184 #define OF_STDOUT_PATH "/soc5200@f0000000/serial@2000"
185
186 /*
187 * I2C configuration
188 */
189 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
190 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
191
192 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
193 #define CONFIG_SYS_I2C_SLAVE 0x7F
194
195 /*
196 * EEPROM configuration
197 */
198 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */
199 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
200 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
201 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 70
202
203 /*
204 * Flash configuration
205 */
206 #if defined(CONFIG_LITE5200B)
207 #define CONFIG_SYS_FLASH_BASE 0xFE000000
208 #define CONFIG_SYS_FLASH_SIZE 0x01000000
209 #if !defined(CONFIG_SYS_LOWBOOT)
210 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000)
211 #else /* CONFIG_SYS_LOWBOOT */
212 #if defined(CONFIG_SYS_LOWBOOT08)
213 # error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
214 #endif
215 #if defined(CONFIG_SYS_LOWBOOT16)
216 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x01060000)
217 #endif
218 #endif /* CONFIG_SYS_LOWBOOT */
219 #else /* !CONFIG_LITE5200B (IceCube)*/
220 #define CONFIG_SYS_FLASH_BASE 0xFF000000
221 #define CONFIG_SYS_FLASH_SIZE 0x01000000
222 #if !defined(CONFIG_SYS_LOWBOOT)
223 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000)
224 #else /* CONFIG_SYS_LOWBOOT */
225 #if defined(CONFIG_SYS_LOWBOOT08)
226 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000)
227 #endif
228 #if defined(CONFIG_SYS_LOWBOOT16)
229 #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00040000)
230 #endif
231 #endif /* CONFIG_SYS_LOWBOOT */
232 #endif /* CONFIG_LITE5200B */
233 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
234
235 #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
236
237 #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
238 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
239
240 #undef CONFIG_FLASH_16BIT /* Flash is 8-bit */
241
242 #if defined(CONFIG_LITE5200B)
243 #define CONFIG_FLASH_CFI_DRIVER
244 #define CONFIG_SYS_FLASH_CFI
245 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START}
246 #endif
247
248
249 /*
250 * Environment settings
251 */
252 #define CONFIG_ENV_IS_IN_FLASH 1
253 #define CONFIG_ENV_SIZE 0x10000
254 #if defined(CONFIG_LITE5200B)
255 #define CONFIG_ENV_SECT_SIZE 0x20000
256 #else
257 #define CONFIG_ENV_SECT_SIZE 0x10000
258 #endif
259 #define CONFIG_ENV_OVERWRITE 1
260
261 /*
262 * Memory map
263 */
264 #define CONFIG_SYS_MBAR 0xF0000000
265 #define CONFIG_SYS_SDRAM_BASE 0x00000000
266 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
267
268 /* Use SRAM until RAM will be available */
269 #define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM
270 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE /* End of used area in DPRAM */
271
272
273 #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
274 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
275 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
276
277 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
278 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
279 # define CONFIG_SYS_RAMBOOT 1
280 #endif
281
282 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
283 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
284 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
285
286 /*
287 * Ethernet configuration
288 */
289 #define CONFIG_MPC5xxx_FEC 1
290 #define CONFIG_MPC5xxx_FEC_MII100
291 /*
292 * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
293 */
294 /* #define CONFIG_MPC5xxx_FEC_MII10 */
295 #define CONFIG_PHY_ADDR 0x00
296
297 /*
298 * GPIO configuration
299 */
300 #ifdef CONFIG_MPC5200_DDR
301 #define CONFIG_SYS_GPS_PORT_CONFIG 0x90000004
302 #else
303 #define CONFIG_SYS_GPS_PORT_CONFIG 0x10000004
304 #endif
305
306 /*
307 * Miscellaneous configurable options
308 */
309 #define CONFIG_SYS_LONGHELP /* undef to save memory */
310 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
311 #if defined(CONFIG_CMD_KGDB)
312 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
313 #else
314 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
315 #endif
316 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
317 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
318 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
319
320 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
321 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
322
323 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
324
325 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
326
327 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
328 #if defined(CONFIG_CMD_KGDB)
329 # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
330 #endif
331
332 /*
333 * Various low-level settings
334 */
335 #define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI
336 #define CONFIG_SYS_HID0_FINAL HID0_ICE
337
338 #if defined(CONFIG_LITE5200B)
339 #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
340 #define CONFIG_SYS_CS1_SIZE CONFIG_SYS_FLASH_SIZE
341 #define CONFIG_SYS_CS1_CFG 0x00047800
342 #define CONFIG_SYS_CS0_START (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)
343 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
344 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_CS0_START
345 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
346 #define CONFIG_SYS_BOOTCS_CFG 0x00047800
347 #else /* IceCube aka Lite5200 */
348 #ifdef CONFIG_MPC5200_DDR
349
350 #define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE)
351 #define CONFIG_SYS_BOOTCS_SIZE 0x00800000
352 #define CONFIG_SYS_BOOTCS_CFG 0x00047801
353 #define CONFIG_SYS_CS1_START CONFIG_SYS_FLASH_BASE
354 #define CONFIG_SYS_CS1_SIZE 0x00800000
355 #define CONFIG_SYS_CS1_CFG 0x00047800
356
357 #else /* !CONFIG_MPC5200_DDR */
358
359 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
360 #define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE
361 #define CONFIG_SYS_BOOTCS_CFG 0x00047801
362 #define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE
363 #define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE
364
365 #endif /* CONFIG_MPC5200_DDR */
366 #endif /*CONFIG_LITE5200B */
367
368 #define CONFIG_SYS_CS_BURST 0x00000000
369 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
370
371 #define CONFIG_SYS_RESET_ADDRESS 0xff000000
372
373 /*-----------------------------------------------------------------------
374 * USB stuff
375 *-----------------------------------------------------------------------
376 */
377 #define CONFIG_USB_CLOCK 0x0001BBBB
378 #define CONFIG_USB_CONFIG 0x00001000
379
380 /*-----------------------------------------------------------------------
381 * IDE/ATA stuff Supports IDE harddisk
382 *-----------------------------------------------------------------------
383 */
384
385 #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
386
387 #undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */
388 #undef CONFIG_IDE_LED /* LED for ide not supported */
389
390 #define CONFIG_IDE_RESET /* reset for ide supported */
391 #define CONFIG_IDE_PREINIT
392
393 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
394 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 1 drive per IDE bus */
395
396 #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
397
398 #define CONFIG_SYS_ATA_BASE_ADDR MPC5XXX_ATA
399
400 /* Offset for data I/O */
401 #define CONFIG_SYS_ATA_DATA_OFFSET (0x0060)
402
403 /* Offset for normal register accesses */
404 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET)
405
406 /* Offset for alternate registers */
407 #define CONFIG_SYS_ATA_ALT_OFFSET (0x005C)
408
409 /* Interval between registers */
410 #define CONFIG_SYS_ATA_STRIDE 4
411
412 #define CONFIG_ATAPI 1
413
414 #endif /* __CONFIG_H */