include/configs/IceCube.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU */
  33 #define CONFIG_MPC5200          1       /* (more precisely a MPC5200 CPU) */
  34 #define CONFIG_ICECUBE          1       /* ... on IceCube board */
  35
  36 /*
  37  * Valid values for CONFIG_SYS_TEXT_BASE are:
  38  * 0xFFF00000   boot high (standard configuration)
  39  * 0xFF000000   boot low for 16 MiB boards
  40  * 0xFF800000   boot low for  8 MiB boards
  41  * 0x00100000   boot from RAM (for testing only)
  42  */
  43 #ifndef CONFIG_SYS_TEXT_BASE
  44 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  45 #endif
  46
  47 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz */
  48
  49 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
  50
  51 /*
  52  * Serial console configuration
  53  */
  54 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  55 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  56 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  57
  58
  59 /*
  60  * PCI Mapping:
  61  * 0x40000000 - 0x4fffffff - PCI Memory
  62  * 0x50000000 - 0x50ffffff - PCI IO Space
  63  */
  64 #define CONFIG_PCI
  65
  66 #if defined(CONFIG_PCI)
  67 #define CONFIG_PCI_PNP          1
  68 #define CONFIG_PCI_SCAN_SHOW    1
  69 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  70
  71 #define CONFIG_PCI_MEM_BUS      0x40000000
  72 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  73 #define CONFIG_PCI_MEM_SIZE     0x10000000
  74
  75 #define CONFIG_PCI_IO_BUS       0x50000000
  76 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  77 #define CONFIG_PCI_IO_SIZE      0x01000000
  78 #endif
  79
  80 #define CONFIG_SYS_XLB_PIPELINING       1
  81
  82 #define CONFIG_NET_MULTI        1
  83 #define CONFIG_MII              1
  84 #define CONFIG_EEPRO100         1
  85 #define CONFIG_SYS_RX_ETH_BUFFER        8  /* use 8 rx buffer on eepro100  */
  86 #define CONFIG_NS8382X          1
  87
  88 /* Partitions */
  89 #define CONFIG_MAC_PARTITION
  90 #define CONFIG_DOS_PARTITION
  91 #define CONFIG_ISO_PARTITION
  92
  93 /* USB */
  94 #define CONFIG_USB_OHCI_NEW
  95 #define CONFIG_USB_STORAGE
  96 #define CONFIG_SYS_OHCI_BE_CONTROLLER
  97 #undef CONFIG_SYS_USB_OHCI_BOARD_INIT
  98 #define CONFIG_SYS_USB_OHCI_CPU_INIT    1
  99 #define CONFIG_SYS_USB_OHCI_REGS_BASE   MPC5XXX_USB
 100 #define CONFIG_SYS_USB_OHCI_SLOT_NAME   "mpc5200"
 101 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
 102
 103 #define CONFIG_TIMESTAMP                /* Print image info with timestamp */
 104
 105
 106 /*
 107  * BOOTP options
 108  */
 109 #define CONFIG_BOOTP_BOOTFILESIZE
 110 #define CONFIG_BOOTP_BOOTPATH
 111 #define CONFIG_BOOTP_GATEWAY
 112 #define CONFIG_BOOTP_HOSTNAME
 113
 114
 115 /*
 116  * Command line configuration.
 117  */
 118 #include <config_cmd_default.h>
 119
 120 #define CONFIG_CMD_EEPROM
 121 #define CONFIG_CMD_FAT
 122 #define CONFIG_CMD_I2C
 123 #define CONFIG_CMD_IDE
 124 #define CONFIG_CMD_NFS
 125 #define CONFIG_CMD_SNTP
 126 #define CONFIG_CMD_USB
 127
 128 #if defined(CONFIG_PCI)
 129 #define CONFIG_CMD_PCI
 130 #endif
 131
 132
 133 #if (CONFIG_SYS_TEXT_BASE == 0xFF000000)                /* Boot low with 16 MB Flash */
 134 #   define CONFIG_SYS_LOWBOOT           1
 135 #   define CONFIG_SYS_LOWBOOT16 1
 136 #endif
 137 #if (CONFIG_SYS_TEXT_BASE == 0xFF800000)                /* Boot low with  8 MB Flash */
 138 #if defined(CONFIG_LITE5200B)
 139 #   error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
 140 #else
 141 #   define CONFIG_SYS_LOWBOOT           1
 142 #   define CONFIG_SYS_LOWBOOT08 1
 143 #endif
 144 #endif
 145
 146 /*
 147  * Autobooting
 148  */
 149 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
 150
 151 #define CONFIG_PREBOOT  "echo;" \
 152         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 153         "echo"
 154
 155 #undef  CONFIG_BOOTARGS
 156
 157 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 158         "netdev=eth0\0"                                                 \
 159         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 160                 "nfsroot=${serverip}:${rootpath}\0"                     \
 161         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 162         "addip=setenv bootargs ${bootargs} "                            \
 163                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 164                 ":${hostname}:${netdev}:off panic=1\0"                  \
 165         "flash_nfs=run nfsargs addip;"                                  \
 166                 "bootm ${kernel_addr}\0"                                \
 167         "flash_self=run ramargs addip;"                                 \
 168                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 169         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 170         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
 171         "bootfile=/tftpboot/MPC5200/uImage\0"                           \
 172         ""
 173
 174 #define CONFIG_BOOTCOMMAND      "run flash_self"
 175
 176 /*
 177  * IPB Bus clocking configuration.
 178  */
 179 #if defined(CONFIG_LITE5200B)
 180 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
 181 #else
 182 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK          /* define for 133MHz speed */
 183 #endif
 184
 185 /* pass open firmware flat tree */
 186 #define CONFIG_OF_LIBFDT        1
 187 #define CONFIG_OF_BOARD_SETUP   1
 188
 189 #define OF_CPU                  "PowerPC,5200@0"
 190 #define OF_SOC                  "soc5200@f0000000"
 191 #define OF_TBCLK                (bd->bi_busfreq / 4)
 192 #define OF_STDOUT_PATH          "/soc5200@f0000000/serial@2000"
 193
 194 /*
 195  * I2C configuration
 196  */
 197 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 198 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
 199
 200 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 201 #define CONFIG_SYS_I2C_SLAVE            0x7F
 202
 203 /*
 204  * EEPROM configuration
 205  */
 206 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* 1010000x */
 207 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 208 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 209 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   70
 210
 211 /*
 212  * Flash configuration
 213  */
 214 #if defined(CONFIG_LITE5200B)
 215 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 216 #define CONFIG_SYS_FLASH_SIZE           0x01000000
 217 #if !defined(CONFIG_SYS_LOWBOOT)
 218 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x01760000 + 0x00800000)
 219 #else   /* CONFIG_SYS_LOWBOOT */
 220 #if defined(CONFIG_SYS_LOWBOOT08)
 221 # error CONFIG_SYS_LOWBOOT08 is incompatible with the Lite5200B
 222 #endif
 223 #if defined(CONFIG_SYS_LOWBOOT16)
 224 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x01060000)
 225 #endif
 226 #endif /* CONFIG_SYS_LOWBOOT */
 227 #else /* !CONFIG_LITE5200B (IceCube)*/
 228 #define CONFIG_SYS_FLASH_BASE           0xFF000000
 229 #define CONFIG_SYS_FLASH_SIZE           0x01000000
 230 #if !defined(CONFIG_SYS_LOWBOOT)
 231 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00740000 + 0x00800000)
 232 #else   /* CONFIG_SYS_LOWBOOT */
 233 #if defined(CONFIG_SYS_LOWBOOT08)
 234 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00040000 + 0x00800000)
 235 #endif
 236 #if defined(CONFIG_SYS_LOWBOOT16)
 237 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x00040000)
 238 #endif
 239 #endif  /* CONFIG_SYS_LOWBOOT */
 240 #endif /* CONFIG_LITE5200B */
 241 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of memory banks      */
 242
 243 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 244
 245 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 246 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 247
 248 #undef CONFIG_FLASH_16BIT       /* Flash is 8-bit */
 249
 250 #if defined(CONFIG_LITE5200B)
 251 #define CONFIG_FLASH_CFI_DRIVER
 252 #define CONFIG_SYS_FLASH_CFI
 253 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_CS1_START,CONFIG_SYS_CS0_START}
 254 #endif
 255
 256
 257 /*
 258  * Environment settings
 259  */
 260 #define CONFIG_ENV_IS_IN_FLASH  1
 261 #define CONFIG_ENV_SIZE         0x10000
 262 #if defined(CONFIG_LITE5200B)
 263 #define CONFIG_ENV_SECT_SIZE    0x20000
 264 #else
 265 #define CONFIG_ENV_SECT_SIZE    0x10000
 266 #endif
 267 #define CONFIG_ENV_OVERWRITE    1
 268
 269 /*
 270  * Memory map
 271  */
 272 #define CONFIG_SYS_MBAR         0xF0000000
 273 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 274 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 275
 276 /* Use SRAM until RAM will be available */
 277 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 278 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE       /* End of used area in DPRAM */
 279
 280
 281 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
 282 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 283 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 284
 285 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 286 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 287 #   define CONFIG_SYS_RAMBOOT           1
 288 #endif
 289
 290 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 291 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)     /* Reserve 512 kB for malloc()  */
 292 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 293
 294 /*
 295  * Ethernet configuration
 296  */
 297 #define CONFIG_MPC5xxx_FEC      1
 298 #define CONFIG_MPC5xxx_FEC_MII100
 299 /*
 300  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 301  */
 302 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 303 #define CONFIG_PHY_ADDR         0x00
 304
 305 /*
 306  * GPIO configuration
 307  */
 308 #ifdef CONFIG_MPC5200_DDR
 309 #define CONFIG_SYS_GPS_PORT_CONFIG      0x90000004
 310 #else
 311 #define CONFIG_SYS_GPS_PORT_CONFIG      0x10000004
 312 #endif
 313
 314 /*
 315  * Miscellaneous configurable options
 316  */
 317 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 318 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 319 #if defined(CONFIG_CMD_KGDB)
 320 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 321 #else
 322 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 323 #endif
 324 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size */
 325 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 326 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 327
 328 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 329 #define CONFIG_SYS_HUSH_PARSER          1       /* use "hush" command parser    */
 330 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 331
 332 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 333 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 334
 335 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 336
 337 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 338
 339 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs */
 340 #if defined(CONFIG_CMD_KGDB)
 341 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 342 #endif
 343
 344 /*
 345  * Various low-level settings
 346  */
 347 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 348 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 349
 350 #if defined(CONFIG_LITE5200B)
 351 #define CONFIG_SYS_CS1_START            CONFIG_SYS_FLASH_BASE
 352 #define CONFIG_SYS_CS1_SIZE             CONFIG_SYS_FLASH_SIZE
 353 #define CONFIG_SYS_CS1_CFG              0x00047800
 354 #define CONFIG_SYS_CS0_START            (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_FLASH_SIZE)
 355 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 356 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_CS0_START
 357 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 358 #define CONFIG_SYS_BOOTCS_CFG           0x00047800
 359 #else /* IceCube aka Lite5200 */
 360 #ifdef CONFIG_MPC5200_DDR
 361
 362 #define CONFIG_SYS_BOOTCS_START (CONFIG_SYS_CS1_START + CONFIG_SYS_CS1_SIZE)
 363 #define CONFIG_SYS_BOOTCS_SIZE          0x00800000
 364 #define CONFIG_SYS_BOOTCS_CFG           0x00047801
 365 #define CONFIG_SYS_CS1_START            CONFIG_SYS_FLASH_BASE
 366 #define CONFIG_SYS_CS1_SIZE             0x00800000
 367 #define CONFIG_SYS_CS1_CFG              0x00047800
 368
 369 #else /* !CONFIG_MPC5200_DDR */
 370
 371 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 372 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 373 #define CONFIG_SYS_BOOTCS_CFG           0x00047801
 374 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 375 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 376
 377 #endif /* CONFIG_MPC5200_DDR */
 378 #endif /*CONFIG_LITE5200B */
 379
 380 #define CONFIG_SYS_CS_BURST             0x00000000
 381 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 382
 383 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 384
 385 /*-----------------------------------------------------------------------
 386  * USB stuff
 387  *-----------------------------------------------------------------------
 388  */
 389 #define CONFIG_USB_CLOCK        0x0001BBBB
 390 #define CONFIG_USB_CONFIG       0x00001000
 391
 392 /*-----------------------------------------------------------------------
 393  * IDE/ATA stuff Supports IDE harddisk
 394  *-----------------------------------------------------------------------
 395  */
 396
 397 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 398
 399 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 400 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 401
 402 #define CONFIG_IDE_RESET                /* reset for ide supported      */
 403 #define CONFIG_IDE_PREINIT
 404
 405 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 406 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 1 drive per IDE bus     */
 407
 408 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 409
 410 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 411
 412 /* Offset for data I/O                  */
 413 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 414
 415 /* Offset for normal register accesses  */
 416 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 417
 418 /* Offset for alternate registers       */
 419 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 420
 421 /* Interval between registers                                                */
 422 #define CONFIG_SYS_ATA_STRIDE          4
 423
 424 #define CONFIG_ATAPI            1
 425
 426 #endif /* __CONFIG_H */