include/configs/KUP4K.h

   1 /*
   2  * (C) Copyright 2000, 2001, 2002
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * board/config.h - configuration options, board specific
  27  * Derived from ../tqm8xx/tqm8xx.c
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #define CONFIG_MPC855           1       /* This is a MPC855 CPU         */
  39 #define CONFIG_KUP4K            1       /* ...on a KUP4K module */
  40
  41 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  42 #undef  CONFIG_8xx_CONS_SMC2
  43 #undef  CONFIG_8xx_CONS_NONE
  44 #define CONFIG_BAUDRATE         115200  /* console baudrate             */
  45 #if 0
  46 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  47 #else
  48 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second      */
  49 #endif
  50
  51 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  52
  53 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  54
  55
  56 #undef  CONFIG_BOOTARGS
  57
  58
  59 #define CONFIG_EXTRA_ENV_SETTINGS                                         \
  60 "slot_a_boot=setenv bootargs root=/dev/hda2 ip=off panic=1;\
  61  diskboot 200000 0:1; bootm 200000\0"                                     \
  62 "slot_b_boot=setenv bootargs root=/dev/hda2 ip=off panic=1;\
  63  diskboot 200000 2:1; bootm 200000\0"                                     \
  64 "nfs_boot=dhcp; run nfsargs addip; bootm 200000\0"                        \
  65 "panic_boot=echo No Bootdevice !!! reset\0"                               \
  66 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=$(nfsip):$(rootpath)\0" \
  67 "ramargs=setenv bootargs root=/dev/ram rw\0"                              \
  68 "addip=setenv bootargs $(bootargs) ip=$(ipaddr):$(nfsip):$(gatewayip)\
  69 :$(netmask):$(hostname):$(netdev):off panic=1\0"                          \
  70 "netdev=eth0\0"                                                           \
  71 "load=tftp 200000 bootloader.bitmap;tftp 100000 u-boot.bin\0"             \
  72 "update=protect off 1:0-8;era 1:0-8;cp.b 100000 40000000 $(filesize);\
  73 cp.b 200000 40040000 14000\0"                                                   \
  74 "nfsip=192.168.2.19\0"
  75
  76 #define CONFIG_BOOTCOMMAND  \
  77     "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot"
  78
  79
  80 #define CONFIG_MISC_INIT_R  1
  81
  82 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  83 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  84
  85 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  86
  87 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  88
  89 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  90
  91 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  92
  93 #define CONFIG_MAC_PARTITION
  94 #define CONFIG_DOS_PARTITION
  95
  96 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  97
  98 #define CONFIG_ETHADDR                  00:0B:64:00:00:00 /* our OUI from IEEE */
  99 #define CONFIG_KUP4K_LOGO               0x40040000  /* Address of logo bitmap */
 100
 101 /* Define to allow the user to overwrite serial and ethaddr */
 102 #define CONFIG_ENV_OVERWRITE
 103
 104 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
 105                                 CFG_CMD_DHCP    | \
 106                                 CFG_CMD_IDE     | \
 107                                 CFG_CMD_DATE    )
 108
 109 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 110 #include <cmd_confdefs.h>
 111
 112 /*
 113  * Miscellaneous configurable options
 114  */
 115 #define CFG_LONGHELP                    /* undef to save memory         */
 116 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 117 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 118 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 119 #else
 120 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 121 #endif
 122 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 123 #define CFG_MAXARGS     16              /* max number of command args   */
 124 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 125
 126 #define CFG_MEMTEST_START       0x0400000       /* memtest works on     */
 127 #define CFG_MEMTEST_END         0x0C00000       /* 4 ... 12 MB in DRAM  */
 128
 129 #define CFG_LOAD_ADDR           0x200000        /* default load address */
 130
 131 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 132
 133 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 134
 135 #define CFG_CONSOLE_INFO_QUIET 1
 136
 137 /*
 138  * Low Level Configuration Settings
 139  * (address mappings, register initial values, etc.)
 140  * You should know what you are doing if you make changes here.
 141  */
 142 /*-----------------------------------------------------------------------
 143  * Internal Memory Mapped Register
 144  */
 145 #define CFG_IMMR                0xFFF00000
 146
 147 /*-----------------------------------------------------------------------
 148  * Definitions for initial stack pointer and data area (in DPRAM)
 149  */
 150 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 151 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 152 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 153 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 154 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 155
 156 /*-----------------------------------------------------------------------
 157  * Start addresses for the final memory configuration
 158  * (Set up by the startup code)
 159  * Please note that CFG_SDRAM_BASE _must_ start at 0
 160  */
 161 #define CFG_SDRAM_BASE          0x00000000
 162 #define CFG_FLASH_BASE          0x40000000
 163 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 164 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 165 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 166
 167 /*
 168  * For booting Linux, the board info and command line data
 169  * have to be in the first 8 MB of memory, since this is
 170  * the maximum mapped by the Linux kernel during initialization.
 171  */
 172 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 173
 174 /*-----------------------------------------------------------------------
 175  * FLASH organization
 176  */
 177 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 178 #define CFG_MAX_FLASH_SECT      67      /* max number of sectors on one chip    */
 179
 180 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 181 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 182
 183 #define CFG_ENV_IS_IN_FLASH     1
 184 #define CFG_ENV_OFFSET          0x8000  /*   Offset   of Environment Sector     */
 185 #define CFG_ENV_SIZE            0x1000  /* Total Size of Environment Sector     */
 186 #define CFG_ENV_SECT_SIZE       0x8000
 187
 188 /* Address and size of Redundant Environment Sector     */
 189 #if 0
 190 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SIZE)
 191 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 192 #endif
 193 /*-----------------------------------------------------------------------
 194  * Hardware Information Block
 195  */
 196 #if 0
 197 #define CFG_HWINFO_OFFSET       0x0003FFC0      /* offset of HW Info block */
 198 #define CFG_HWINFO_SIZE         0x00000040      /* size   of HW Info block */
 199 #define CFG_HWINFO_MAGIC        0x54514D38      /* 'TQM8' */
 200 #endif
 201 /*-----------------------------------------------------------------------
 202  * Cache Configuration
 203  */
 204 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 205 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 206 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 207 #endif
 208
 209 /*-----------------------------------------------------------------------
 210  * SYPCR - System Protection Control                            11-9
 211  * SYPCR can only be written once after reset!
 212  *-----------------------------------------------------------------------
 213  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 214  */
 215 #if defined(CONFIG_WATCHDOG)
 216 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 217                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 218 #else
 219 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 220 #endif
 221
 222 /*-----------------------------------------------------------------------
 223  * SIUMCR - SIU Module Configuration                            11-6
 224  *-----------------------------------------------------------------------
 225  * PCMCIA config., multi-function pin tri-state
 226  */
 227 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
 228
 229 /*-----------------------------------------------------------------------
 230  * TBSCR - Time Base Status and Control                         11-26
 231  *-----------------------------------------------------------------------
 232  * Clear Reference Interrupt Status, Timebase freezing enabled
 233  */
 234 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 235
 236 /*-----------------------------------------------------------------------
 237  * RTCSC - Real-Time Clock Status and Control Register          11-27
 238  *-----------------------------------------------------------------------
 239  */
 240 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 241
 242 /*-----------------------------------------------------------------------
 243  * PISCR - Periodic Interrupt Status and Control                11-31
 244  *-----------------------------------------------------------------------
 245  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 246  */
 247 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 248
 249 /*-----------------------------------------------------------------------
 250  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 251  *-----------------------------------------------------------------------
 252  * Reset PLL lock status sticky bit, timer expired status bit and timer
 253  * interrupt status bit
 254  *
 255  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 256  */
 257 #define CFG_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
 258
 259 /*-----------------------------------------------------------------------
 260  * SCCR - System Clock and reset Control Register               15-27
 261  *-----------------------------------------------------------------------
 262  * Set clock output, timebase and RTC source and divider,
 263  * power management and some other internal clocks
 264  */
 265 #define SCCR_MASK       SCCR_EBDF00
 266 #define CFG_SCCR        (SCCR_TBS | SCCR_EBDF01 |  \
 267                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 268                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 269                          SCCR_DFALCD00)
 270
 271 /*-----------------------------------------------------------------------
 272  * PCMCIA stuff
 273  *-----------------------------------------------------------------------
 274  *
 275  */
 276
 277 /* KUP4K use both slots, SLOT_A as "primary". */
 278 #define CONFIG_PCMCIA_SLOT_A 1
 279
 280 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 281 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 282 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 283 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 284 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 285 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 286 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 287 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 288
 289 #define PCMCIA_SOCKETS_NO 2
 290 #define PCMCIA_MEM_WIN_NO 8
 291 /*-----------------------------------------------------------------------
 292  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 293  *-----------------------------------------------------------------------
 294  */
 295
 296 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 297
 298 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 299 #define CONFIG_IDE_LED                  1   /* LED   for ide supported  */
 300 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 301
 302 #define CFG_IDE_MAXBUS          2
 303 #define CFG_IDE_MAXDEVICE       4
 304
 305 #define CFG_ATA_IDE0_OFFSET     0x0000
 306
 307 #define CFG_ATA_IDE1_OFFSET     (4 * CFG_PCMCIA_MEM_SIZE)
 308
 309 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 310
 311 /* Offset for data I/O                  */
 312 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 313
 314 /* Offset for normal register accesses  */
 315 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 316
 317 /* Offset for alternate registers       */
 318 #define CFG_ATA_ALT_OFFSET      0x0100
 319
 320
 321 /*-----------------------------------------------------------------------
 322  *
 323  *-----------------------------------------------------------------------
 324  *
 325  */
 326 #define CFG_DER 0
 327
 328 /*
 329  * Init Memory Controller:
 330  *
 331  * BR0/1 and OR0/1 (FLASH)
 332  */
 333 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 334
 335 /* used to re-map FLASH both when starting from SRAM or FLASH:
 336  * restrict access enough to keep SRAM working (if any)
 337  * but not too much to meddle with FLASH accesses
 338  */
 339 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 340 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 341
 342 /*
 343  * FLASH timing:
 344  */
 345 #define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 346                                  OR_SCY_2_CLK | OR_EHTR | OR_BI)
 347
 348 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 349 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 350 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 351
 352
 353 /*
 354  * BR2/3 and OR2/3 (SDRAM)
 355  *
 356  */
 357 #define SDRAM_BASE1_PRELIM      0x00000000      /* SDRAM bank #0        */
 358 #define SDRAM_BASE2_PRELIM      0x20000000      /* SDRAM bank #1        */
 359 #define SDRAM_BASE3_PRELIM      0x30000000      /* SDRAM bank #2        */
 360 #define SDRAM_MAX_SIZE          0x04000000      /* max 648 MB per bank  */
 361
 362 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 363 #define CFG_OR_TIMING_SDRAM     0x00000A00
 364
 365 #if 0
 366 #define CFG_OR1_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
 367 #define CFG_BR1_PRELIM  ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 368
 369 #define CFG_OR2_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
 370 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 371
 372 #define CFG_OR3_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM )
 373 #define CFG_BR3_PRELIM  ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 374 #endif
 375
 376
 377 /*
 378  * Memory Periodic Timer Prescaler
 379  *
 380  * The Divider for PTA (refresh timer) configuration is based on an
 381  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 382  * the number of chip selects (NCS) and the actually needed refresh
 383  * rate is done by setting MPTPR.
 384  *
 385  * PTA is calculated from
 386  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 387  *
 388  *      gclk      CPU clock (not bus clock!)
 389  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 390  *
 391  * 4096  Rows from SDRAM example configuration
 392  * 1000  factor s -> ms
 393  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 394  *    4  Number of refresh cycles per period
 395  *   64  Refresh cycle in ms per number of rows
 396  * --------------------------------------------
 397  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 398  *
 399  * 50 MHz => 50.000.000 / Divider =  98
 400  * 66 Mhz => 66.000.000 / Divider = 129
 401  * 80 Mhz => 80.000.000 / Divider = 156
 402  */
 403 #if   defined(CONFIG_80MHz)
 404 #define CFG_MAMR_PTA            156
 405 #elif defined(CONFIG_66MHz)
 406 #define CFG_MAMR_PTA            129
 407 #else           /*   50 MHz */
 408 #define CFG_MAMR_PTA             98
 409 #endif  /*CONFIG_??MHz */
 410
 411 /*
 412  * For 16 MBit, refresh rates could be 31.3 us
 413  * (= 64 ms / 2K = 125 / quad bursts).
 414  * For a simpler initialization, 15.6 us is used instead.
 415  *
 416  * #define CFG_MPTPR_2BK_2K     MPTPR_PTP_DIV32         for 2 banks
 417  * #define CFG_MPTPR_1BK_2K     MPTPR_PTP_DIV64         for 1 bank
 418  */
 419 #define CFG_MPTPR 0x400
 420
 421 /*
 422  * MAMR settings for SDRAM
 423  */
 424 #define CFG_MAMR 0x80802114
 425
 426 /*
 427  * Internal Definitions
 428  *
 429  * Boot Flags
 430  */
 431 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 432 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 433
 434
 435 #define CONFIG_AUTOBOOT_KEYED           /* use key strings to stop autoboot */
 436 #if 0
 437 #define CONFIG_AUTOBOOT_PROMPT          "Boote in %d Sekunden - stop mit \"2\"\n"
 438 #endif
 439 #define CONFIG_AUTOBOOT_STOP_STR        "." /* easy to stop for now */
 440
 441
 442 #endif  /* __CONFIG_H */