include/configs/KUP4K.h

   1 /*
   2  * (C) Copyright 2000-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  * Klaus Heydeck, Kieback & Peter GmbH & Co KG, heydeck@kieback-peter.de
   5  *
   6  * See file CREDITS for list of people who contributed to this
   7  * project.
   8  *
   9  * This program is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU General Public License as
  11  * published by the Free Software Foundation; either version 2 of
  12  * the License, or (at your option) any later version.
  13  *
  14  * This program is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17  * GNU General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU General Public License
  20  * along with this program; if not, write to the Free Software
  21  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22  * MA 02111-1307 USA
  23  */
  24
  25 /*
  26  * board/config.h - configuration options, board specific
  27  * Derived from ../tqm8xx/tqm8xx.c
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37
  38 #define CONFIG_MPC855           1       /* This is a MPC855 CPU         */
  39 #define CONFIG_KUP4K            1       /* ...on a KUP4K module */
  40
  41 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  42 #undef  CONFIG_8xx_CONS_SMC2
  43 #undef  CONFIG_8xx_CONS_NONE
  44 #define CONFIG_BAUDRATE         115200  /* console baudrate             */
  45 #if 0
  46 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  47 #else
  48 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second      */
  49 #endif
  50
  51 #define CONFIG_BOARD_TYPES      1       /* support board types          */
  52
  53
  54 #undef  CONFIG_BOOTARGS
  55
  56
  57 #define CONFIG_EXTRA_ENV_SETTINGS                                               \
  58 "slot_a_boot=setenv bootargs root=/dev/hda2 ip=off;"                            \
  59  "run addhw; diskboot 200000 0:1; bootm 200000\0"                               \
  60 "slot_b_boot=setenv bootargs root=/dev/hda2 ip=off;"                            \
  61  "run addhw; diskboot 200000 2:1; bootm 200000\0"                               \
  62 "nfs_boot=dhcp; run nfsargs addip addhw; bootm 200000\0"                        \
  63 "panic_boot=echo No Bootdevice !!! reset\0"                                     \
  64 "nfsargs=setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath}\0"    \
  65 "ramargs=setenv bootargs root=/dev/ram rw\0"                                    \
  66 "addip=setenv bootargs ${bootargs} ip=${ipaddr}:${serverip}:${gatewayip}"       \
  67  ":${netmask}:${hostname}:${netdev}:off\0"                                      \
  68 "addhw=setenv bootargs ${bootargs} hw=${hw} key1=${key1} panic=1\0"             \
  69 "netdev=eth0\0"                                                                 \
  70 "contrast=55\0"                                                                 \
  71 "silent=1\0"                                                                    \
  72 "load=tftp 200000 bootloader-4k.bitmap;tftp 100000 bootloader-4k.bin\0"         \
  73 "update=protect off 1:0-7;era 1:0-7;cp.b 100000 40000000 ${filesize};"          \
  74  "cp.b 200000 40050000 14000\0"
  75
  76 #define CONFIG_BOOTCOMMAND  \
  77     "run slot_a_boot;run slot_b_boot;run nfs_boot;run panic_boot"
  78
  79
  80 #define CONFIG_MISC_INIT_R      1
  81 #define CONFIG_MISC_INIT_F      1
  82
  83 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  84 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  85
  86 #define CONFIG_WATCHDOG 1               /* watchdog enabled             */
  87
  88 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  89
  90 #undef  CONFIG_CAN_DRIVER               /* CAN Driver support disabled  */
  91
  92 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  93
  94 #define CONFIG_MAC_PARTITION
  95 #define CONFIG_DOS_PARTITION
  96
  97
  98 /*
  99  * enable I2C and select the hardware/software driver
 100  */
 101 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 102 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 103
 104 #define CFG_I2C_SPEED           93000   /* 93 kHz is supposed to work   */
 105 #define CFG_I2C_SLAVE           0xFE
 106
 107 #ifdef CONFIG_SOFT_I2C
 108 /*
 109  * Software (bit-bang) I2C driver configuration
 110  */
 111 #define PB_SCL          0x00000020      /* PB 26 */
 112 #define PB_SDA          0x00000010      /* PB 27 */
 113
 114 #define I2C_INIT        (immr->im_cpm.cp_pbdir |=  PB_SCL)
 115 #define I2C_ACTIVE      (immr->im_cpm.cp_pbdir |=  PB_SDA)
 116 #define I2C_TRISTATE    (immr->im_cpm.cp_pbdir &= ~PB_SDA)
 117 #define I2C_READ        ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
 118 #define I2C_SDA(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
 119                         else    immr->im_cpm.cp_pbdat &= ~PB_SDA
 120 #define I2C_SCL(bit)    if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
 121                         else    immr->im_cpm.cp_pbdat &= ~PB_SCL
 122 #define I2C_DELAY       udelay(2)       /* 1/4 I2C clock duration */
 123 #endif  /* CONFIG_SOFT_I2C */
 124
 125
 126 /*-----------------------------------------------------------------------
 127  * I2C Configuration
 128  */
 129
 130 #define CFG_I2C_PICIO_ADDR      0x21    /* PCF8574 IO Expander                  */
 131 #define CFG_I2C_RTC_ADDR        0x51    /* PCF8563 RTC                          */
 132
 133
 134 /* List of I2C addresses to be verified by POST */
 135
 136 #define I2C_ADDR_LIST   {CFG_I2C_PICIO_ADDR,    \
 137                         CFG_I2C_RTC_ADDR,       \
 138                         }
 139
 140
 141 #define CONFIG_RTC_PCF8563              /* use Philips PCF8563 RTC      */
 142
 143 #define CFG_DISCOVER_PHY
 144 #define CONFIG_MII
 145
 146 #if 0
 147 #define CONFIG_ETHADDR                  00:0B:64:00:00:00 /* our OUI from IEEE */
 148 #endif
 149 #define CONFIG_KUP4K_LOGO               0x40050000  /* Address of logo bitmap */
 150
 151 /* Define to allow the user to overwrite serial and ethaddr */
 152 #define CONFIG_ENV_OVERWRITE
 153 #if 1
 154 /* POST support */
 155
 156 #define CONFIG_POST             (CFG_POST_CPU      | \
 157                                  CFG_POST_RTC      | \
 158                                  CFG_POST_I2C)
 159
 160 #ifdef CONFIG_POST
 161 #define CFG_CMD_POST_DIAG CFG_CMD_DIAG
 162 #else
 163 #define CFG_CMD_POST_DIAG 0
 164 #endif
 165 #endif
 166
 167 #define CONFIG_COMMANDS       ( CONFIG_CMD_DFL  | \
 168                                 CFG_CMD_DATE    | \
 169                                 CFG_CMD_DHCP    | \
 170                                 CFG_CMD_I2C     | \
 171                                 CFG_CMD_IDE     | \
 172                                 CFG_CMD_NFS     | \
 173                                 CFG_CMD_POST_DIAG       | \
 174                                 CFG_CMD_SNTP    )
 175
 176 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 177 #include <cmd_confdefs.h>
 178
 179 /*
 180  * Miscellaneous configurable options
 181  */
 182 #define CFG_LONGHELP                    /* undef to save memory         */
 183 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 184 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 185 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 186 #else
 187 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 188 #endif
 189 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 190 #define CFG_MAXARGS     16              /* max number of command args   */
 191 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 192
 193 #define CFG_MEMTEST_START       0x000400000     /* memtest works on     */
 194 #define CFG_MEMTEST_END         0x002C00000     /* 4 ... 44 MB in DRAM  */
 195
 196 #define CFG_LOAD_ADDR           0x200000        /* default load address */
 197
 198 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 199
 200 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 115200 }
 201
 202 #define CFG_CONSOLE_INFO_QUIET 1
 203
 204 /*
 205  * Low Level Configuration Settings
 206  * (address mappings, register initial values, etc.)
 207  * You should know what you are doing if you make changes here.
 208  */
 209 /*-----------------------------------------------------------------------
 210  * Internal Memory Mapped Register
 211  */
 212 #define CFG_IMMR                0xFFF00000
 213
 214 /*-----------------------------------------------------------------------
 215  * Definitions for initial stack pointer and data area (in DPRAM)
 216  */
 217 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 218 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 219 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 220 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 221 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 222
 223 /*-----------------------------------------------------------------------
 224  * Start addresses for the final memory configuration
 225  * (Set up by the startup code)
 226  * Please note that CFG_SDRAM_BASE _must_ start at 0
 227  */
 228 #define CFG_SDRAM_BASE          0x00000000
 229 #define CFG_FLASH_BASE          0x40000000
 230 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor   */
 231 #define CFG_MONITOR_BASE        CFG_FLASH_BASE
 232 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 233
 234 /*
 235  * For booting Linux, the board info and command line data
 236  * have to be in the first 8 MB of memory, since this is
 237  * the maximum mapped by the Linux kernel during initialization.
 238  */
 239 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 240
 241 /*-----------------------------------------------------------------------
 242  * FLASH organization
 243  */
 244 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 245 #define CFG_MAX_FLASH_SECT      19      /* max number of sectors on one chip    */
 246
 247 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 248 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 249
 250 #define CFG_ENV_IS_IN_FLASH     1
 251 #define CFG_ENV_OFFSET          0x40000 /*   Offset   of Environment Sector     */
 252 #define CFG_ENV_SIZE            0x1000  /* Total Size of Environment Sector     */
 253 #define CFG_ENV_SECT_SIZE       0x10000
 254
 255 /* Address and size of Redundant Environment Sector     */
 256 #if 0
 257 #define CFG_ENV_OFFSET_REDUND   (CFG_ENV_OFFSET+CFG_ENV_SIZE)
 258 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 259 #endif
 260 /*-----------------------------------------------------------------------
 261  * Hardware Information Block
 262  */
 263 #if 1
 264 #define CFG_HWINFO_OFFSET       0x000F0000      /* offset of HW Info block */
 265 #define CFG_HWINFO_SIZE         0x00000100      /* size   of HW Info block */
 266 #define CFG_HWINFO_MAGIC        0x4B26500D      /* 'K&P<CR>' */
 267 #endif
 268 /*-----------------------------------------------------------------------
 269  * Cache Configuration
 270  */
 271 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 272 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 273 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 274 #endif
 275
 276 /*-----------------------------------------------------------------------
 277  * SYPCR - System Protection Control                            11-9
 278  * SYPCR can only be written once after reset!
 279  *-----------------------------------------------------------------------
 280  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 281  */
 282 #if 0 && defined(CONFIG_WATCHDOG)       /* KUP uses external TPS3705 WD */
 283 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 284                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 285 #else
 286 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 287 #endif
 288
 289 /*-----------------------------------------------------------------------
 290  * SIUMCR - SIU Module Configuration                            11-6
 291  *-----------------------------------------------------------------------
 292  * PCMCIA config., multi-function pin tri-state
 293  */
 294 #define CFG_SIUMCR      (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00)
 295
 296 /*-----------------------------------------------------------------------
 297  * TBSCR - Time Base Status and Control                         11-26
 298  *-----------------------------------------------------------------------
 299  * Clear Reference Interrupt Status, Timebase freezing enabled
 300  */
 301 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 302
 303 /*-----------------------------------------------------------------------
 304  * RTCSC - Real-Time Clock Status and Control Register          11-27
 305  *-----------------------------------------------------------------------
 306  */
 307 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 308
 309 /*-----------------------------------------------------------------------
 310  * PISCR - Periodic Interrupt Status and Control                11-31
 311  *-----------------------------------------------------------------------
 312  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 313  */
 314 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 315
 316 /*-----------------------------------------------------------------------
 317  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 318  *-----------------------------------------------------------------------
 319  * Reset PLL lock status sticky bit, timer expired status bit and timer
 320  * interrupt status bit
 321  *
 322  * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)!
 323  */
 324 #define CFG_PLPRCR ( (5-1)<<PLPRCR_MF_SHIFT | PLPRCR_TEXPS | PLPRCR_TMIST )
 325
 326 /*-----------------------------------------------------------------------
 327  * SCCR - System Clock and reset Control Register               15-27
 328  *-----------------------------------------------------------------------
 329  * Set clock output, timebase and RTC source and divider,
 330  * power management and some other internal clocks
 331  */
 332 #define SCCR_MASK       SCCR_EBDF00
 333 #define CFG_SCCR        (SCCR_TBS | SCCR_EBDF01 |  \
 334                          SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
 335                          SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 336                          SCCR_DFALCD00)
 337
 338 /*-----------------------------------------------------------------------
 339  * PCMCIA stuff
 340  *-----------------------------------------------------------------------
 341  *
 342  */
 343
 344 /* KUP4K use both slots, SLOT_A as "primary". */
 345 #define CONFIG_PCMCIA_SLOT_A 1
 346
 347 #define CFG_PCMCIA_MEM_ADDR     (0xE0000000)
 348 #define CFG_PCMCIA_MEM_SIZE     ( 64 << 20 )
 349 #define CFG_PCMCIA_DMA_ADDR     (0xE4000000)
 350 #define CFG_PCMCIA_DMA_SIZE     ( 64 << 20 )
 351 #define CFG_PCMCIA_ATTRB_ADDR   (0xE8000000)
 352 #define CFG_PCMCIA_ATTRB_SIZE   ( 64 << 20 )
 353 #define CFG_PCMCIA_IO_ADDR      (0xEC000000)
 354 #define CFG_PCMCIA_IO_SIZE      ( 64 << 20 )
 355
 356 #define PCMCIA_SOCKETS_NO 2
 357 #define PCMCIA_MEM_WIN_NO 8
 358 /*-----------------------------------------------------------------------
 359  * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 360  *-----------------------------------------------------------------------
 361  */
 362
 363 #define CONFIG_IDE_8xx_PCCARD   1       /* Use IDE with PC Card Adapter */
 364
 365 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 366 #define CONFIG_IDE_LED          1       /* LED   for ide supported      */
 367 #undef  CONFIG_IDE_RESET                /* reset for ide not supported  */
 368
 369 #define CFG_IDE_MAXBUS          2
 370 #define CFG_IDE_MAXDEVICE       4
 371
 372 #define CFG_ATA_IDE0_OFFSET     0x0000
 373
 374 #define CFG_ATA_IDE1_OFFSET     (4 * CFG_PCMCIA_MEM_SIZE)
 375
 376 #define CFG_ATA_BASE_ADDR       CFG_PCMCIA_MEM_ADDR
 377
 378 /* Offset for data I/O                  */
 379 #define CFG_ATA_DATA_OFFSET     (CFG_PCMCIA_MEM_SIZE + 0x320)
 380
 381 /* Offset for normal register accesses  */
 382 #define CFG_ATA_REG_OFFSET      (2 * CFG_PCMCIA_MEM_SIZE + 0x320)
 383
 384 /* Offset for alternate registers       */
 385 #define CFG_ATA_ALT_OFFSET      0x0100
 386
 387
 388 /*-----------------------------------------------------------------------
 389  *
 390  *-----------------------------------------------------------------------
 391  *
 392  */
 393 #define CFG_DER 0
 394
 395 /*
 396  * Init Memory Controller:
 397  *
 398  * BR0/1 and OR0/1 (FLASH)
 399  */
 400 #define FLASH_BASE0_PRELIM      0x40000000      /* FLASH bank #0        */
 401
 402 /* used to re-map FLASH both when starting from SRAM or FLASH:
 403  * restrict access enough to keep SRAM working (if any)
 404  * but not too much to meddle with FLASH accesses
 405  */
 406 #define CFG_REMAP_OR_AM         0x80000000      /* OR addr mask */
 407 #define CFG_PRELIM_OR_AM        0xE0000000      /* OR addr mask */
 408
 409 /*
 410  * FLASH timing:
 411  */
 412 #define CFG_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
 413                                  OR_SCY_2_CLK | OR_EHTR | OR_BI)
 414
 415 #define CFG_OR0_REMAP   (CFG_REMAP_OR_AM  | CFG_OR_TIMING_FLASH)
 416 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH)
 417 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 418
 419
 420 /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)      */
 421 #define CFG_OR_TIMING_SDRAM     0x00000A00
 422
 423
 424 /*
 425  * Memory Periodic Timer Prescaler
 426  *
 427  * The Divider for PTA (refresh timer) configuration is based on an
 428  * example SDRAM configuration (64 MBit, one bank). The adjustment to
 429  * the number of chip selects (NCS) and the actually needed refresh
 430  * rate is done by setting MPTPR.
 431  *
 432  * PTA is calculated from
 433  *      PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 434  *
 435  *      gclk      CPU clock (not bus clock!)
 436  *      Trefresh  Refresh cycle * 4 (four word bursts used)
 437  *
 438  * 4096  Rows from SDRAM example configuration
 439  * 1000  factor s -> ms
 440  *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 441  *    4  Number of refresh cycles per period
 442  *   64  Refresh cycle in ms per number of rows
 443  * --------------------------------------------
 444  * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 445  *
 446  * 50 MHz => 50.000.000 / Divider =  98
 447  * 66 Mhz => 66.000.000 / Divider = 129
 448  * 80 Mhz => 80.000.000 / Divider = 156
 449  */
 450 #if   defined(CONFIG_80MHz)
 451 #define CFG_MAMR_PTA            156
 452 #elif defined(CONFIG_66MHz)
 453 #define CFG_MAMR_PTA            129
 454 #else           /*   50 MHz */
 455 #define CFG_MAMR_PTA             98
 456 #endif  /*CONFIG_??MHz */
 457
 458 /*
 459  * For 16 MBit, refresh rates could be 31.3 us
 460  * (= 64 ms / 2K = 125 / quad bursts).
 461  * For a simpler initialization, 15.6 us is used instead.
 462  *
 463  * #define CFG_MPTPR_2BK_2K     MPTPR_PTP_DIV32         for 2 banks
 464  * #define CFG_MPTPR_1BK_2K     MPTPR_PTP_DIV64         for 1 bank
 465  */
 466 #define CFG_MPTPR 0x400
 467
 468 /*
 469  * MAMR settings for SDRAM
 470  */
 471 #define CFG_MAMR 0x80802114
 472
 473 /*
 474  * Internal Definitions
 475  *
 476  * Boot Flags
 477  */
 478 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 479 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 480
 481
 482 #define CONFIG_AUTOBOOT_KEYED           /* use key strings to stop autoboot */
 483 #if 0
 484 #define CONFIG_AUTOBOOT_PROMPT          "Boote in %d Sekunden - stop mit \"2\"\n"
 485 #endif
 486 #define CONFIG_AUTOBOOT_STOP_STR        "." /* easy to stop for now */
 487 #define CONFIG_SILENT_CONSOLE   1
 488
 489 #endif  /* __CONFIG_H */