include/configs/M5208EVBE.h

   1 /*
   2  * Configuation settings for the Freescale MCF5208EVBe.
   3  *
   4  * Copyright (C) 2004-2008 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #ifndef _M5208EVBE_H
  11 #define _M5208EVBE_H
  12
  13 /*
  14  * High Level Configuration Options
  15  * (easy to change)
  16  */
  17 #define CONFIG_MCFUART
  18 #define CONFIG_SYS_UART_PORT            (0)
  19
  20 #undef CONFIG_WATCHDOG
  21 #define CONFIG_WATCHDOG_TIMEOUT         5000
  22
  23 #define CONFIG_MCFFEC
  24 #ifdef CONFIG_MCFFEC
  25 #       define CONFIG_MII               1
  26 #       define CONFIG_MII_INIT          1
  27 #       define CONFIG_SYS_DISCOVER_PHY
  28 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  29 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  30 #       define CONFIG_HAS_ETH1
  31
  32 #       define CONFIG_SYS_FEC0_PINMUX   0
  33 #       define CONFIG_SYS_FEC0_MIIBASE  CONFIG_SYS_FEC0_IOBASE
  34 #       define MCFFEC_TOUT_LOOP         50000
  35 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  36 #       ifndef CONFIG_SYS_DISCOVER_PHY
  37 #               define FECDUPLEX        FULL
  38 #               define FECSPEED         _100BASET
  39 #       else
  40 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  41 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  42 #               endif
  43 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  44 #endif
  45
  46 /* Timer */
  47 #define CONFIG_MCFTMR
  48 #undef CONFIG_MCFPIT
  49
  50 /* I2C */
  51 #define CONFIG_SYS_I2C
  52 #define CONFIG_SYS_I2C_FSL
  53 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  54 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  55 #define CONFIG_SYS_FSL_I2C_OFFSET       0x58000
  56 #define CONFIG_SYS_IMMR                 CONFIG_SYS_MBAR
  57
  58 #define CONFIG_UDP_CHECKSUM
  59
  60 #ifdef CONFIG_MCFFEC
  61 #       define CONFIG_IPADDR    192.162.1.2
  62 #       define CONFIG_NETMASK   255.255.255.0
  63 #       define CONFIG_SERVERIP  192.162.1.1
  64 #       define CONFIG_GATEWAYIP 192.162.1.1
  65 #endif                          /* CONFIG_MCFFEC */
  66
  67 #define CONFIG_HOSTNAME         M5208EVBe
  68 #define CONFIG_EXTRA_ENV_SETTINGS               \
  69         "netdev=eth0\0"                         \
  70         "loadaddr=40010000\0"                   \
  71         "u-boot=u-boot.bin\0"                   \
  72         "load=tftp ${loadaddr) ${u-boot}\0"     \
  73         "upd=run load; run prog\0"              \
  74         "prog=prot off 0 3ffff;"                \
  75         "era 0 3ffff;"                          \
  76         "cp.b ${loadaddr} 0 ${filesize};"       \
  77         "save\0"                                \
  78         ""
  79
  80 #define CONFIG_PRAM             512     /* 512 KB */
  81
  82 #define CONFIG_SYS_LOAD_ADDR    0x40010000
  83
  84 #define CONFIG_SYS_CLK          166666666       /* CPU Core Clock */
  85 #define CONFIG_SYS_PLL_ODR      0x36
  86 #define CONFIG_SYS_PLL_FDR      0x7D
  87
  88 #define CONFIG_SYS_MBAR         0xFC000000
  89
  90 /*
  91  * Low Level Configuration Settings
  92  * (address mappings, register initial values, etc.)
  93  * You should know what you are doing if you make changes here.
  94  */
  95 /* Definitions for initial stack pointer and data area (in DPRAM) */
  96 #define CONFIG_SYS_INIT_RAM_ADDR        0x80000000
  97 #define CONFIG_SYS_INIT_RAM_SIZE                0x4000  /* Size of used area in internal SRAM */
  98 #define CONFIG_SYS_INIT_RAM_CTRL        0x221
  99 #define CONFIG_SYS_GBL_DATA_OFFSET      ((CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) - 0x10)
 100 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 101
 102 /*
 103  * Start addresses for the final memory configuration
 104  * (Set up by the startup code)
 105  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 106  */
 107 #define CONFIG_SYS_SDRAM_BASE           0x40000000
 108 #define CONFIG_SYS_SDRAM_SIZE           32      /* SDRAM size in MB */
 109 #define CONFIG_SYS_SDRAM_CFG1           0x43711630
 110 #define CONFIG_SYS_SDRAM_CFG2           0x56670000
 111 #define CONFIG_SYS_SDRAM_CTRL           0xE1002000
 112 #define CONFIG_SYS_SDRAM_EMOD           0x80010000
 113 #define CONFIG_SYS_SDRAM_MODE           0x00CD0000
 114
 115 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 116 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 117
 118 #define CONFIG_SYS_MONITOR_BASE         (CONFIG_SYS_FLASH_BASE + 0x400)
 119 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 120
 121 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 122 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 123
 124 /*
 125  * For booting Linux, the board info and command line data
 126  * have to be in the first 8 MB of memory, since this is
 127  * the maximum mapped by the Linux kernel during initialization ??
 128  */
 129 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 130 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 131
 132 /* FLASH organization */
 133 #define CONFIG_SYS_FLASH_CFI
 134 #ifdef CONFIG_SYS_FLASH_CFI
 135 #       define CONFIG_FLASH_CFI_DRIVER          1
 136 #       define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
 137 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 138 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 139 #       define CONFIG_SYS_MAX_FLASH_SECT        254     /* max number of sectors on one chip */
 140 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 141 #endif
 142
 143 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_CS0_BASE
 144
 145 /*
 146  * Configuration for environment
 147  * Environment is embedded in u-boot in the second sector of the flash
 148  */
 149 #define CONFIG_ENV_OFFSET               0x2000
 150 #define CONFIG_ENV_SIZE                 0x1000
 151 #define CONFIG_ENV_SECT_SIZE            0x2000
 152
 153 #define LDS_BOARD_TEXT \
 154         . = DEFINED(env_offset) ? env_offset : .; \
 155         env/embedded.o(.text*);
 156
 157 /* Cache Configuration */
 158 #define CONFIG_SYS_CACHELINE_SIZE       16
 159
 160 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 161                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 162 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 163                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 164 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV | CF_CACR_INVI)
 165 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 166                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 167                                          CF_ACR_EN | CF_ACR_SM_ALL)
 168 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_CINV | \
 169                                          CF_CACR_DISD | CF_CACR_INVI | \
 170                                          CF_CACR_CEIB | CF_CACR_DCM | \
 171                                          CF_CACR_EUSP)
 172
 173 /* Chipselect bank definitions */
 174 /*
 175  * CS0 - NOR Flash
 176  * CS1 - Available
 177  * CS2 - Available
 178  * CS3 - Available
 179  * CS4 - Available
 180  * CS5 - Available
 181  */
 182 #define CONFIG_SYS_CS0_BASE             0
 183 #define CONFIG_SYS_CS0_MASK             0x007F0001
 184 #define CONFIG_SYS_CS0_CTRL             0x00001FA0
 185
 186 #endif                          /* _M5208EVBE_H */