include/configs/M5235EVB.h

   1 /*
   2  * Configuation settings for the Freescale MCF5329 FireEngine board.
   3  *
   4  * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
   5  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /*
  11  * board/config.h - configuration options, board specific
  12  */
  13
  14 #ifndef _M5235EVB_H
  15 #define _M5235EVB_H
  16
  17 /*
  18  * High Level Configuration Options
  19  * (easy to change)
  20  */
  21
  22 #define CONFIG_MCFUART
  23 #define CONFIG_SYS_UART_PORT            (0)
  24
  25 #undef CONFIG_WATCHDOG
  26 #define CONFIG_WATCHDOG_TIMEOUT 5000    /* timeout in milliseconds, max timeout is 6.71sec */
  27
  28 /*
  29  * BOOTP options
  30  */
  31 #define CONFIG_BOOTP_BOOTFILESIZE
  32 #define CONFIG_BOOTP_BOOTPATH
  33 #define CONFIG_BOOTP_GATEWAY
  34 #define CONFIG_BOOTP_HOSTNAME
  35
  36 /* Command line configuration */
  37 #define CONFIG_CMD_PCI
  38
  39 #define CONFIG_MCFFEC
  40 #ifdef CONFIG_MCFFEC
  41 #       define CONFIG_MII               1
  42 #       define CONFIG_MII_INIT          1
  43 #       define CONFIG_SYS_DISCOVER_PHY
  44 #       define CONFIG_SYS_RX_ETH_BUFFER 8
  45 #       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  46
  47 #       define CONFIG_SYS_FEC0_PINMUX           0
  48 #       define CONFIG_SYS_FEC0_MIIBASE          CONFIG_SYS_FEC0_IOBASE
  49 #       define MCFFEC_TOUT_LOOP         50000
  50 /* If CONFIG_SYS_DISCOVER_PHY is not defined - hardcoded */
  51 #       ifndef CONFIG_SYS_DISCOVER_PHY
  52 #               define FECDUPLEX        FULL
  53 #               define FECSPEED         _100BASET
  54 #       else
  55 #               ifndef CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  56 #                       define CONFIG_SYS_FAULT_ECHO_LINK_DOWN
  57 #               endif
  58 #       endif                   /* CONFIG_SYS_DISCOVER_PHY */
  59 #endif
  60
  61 /* Timer */
  62 #define CONFIG_MCFTMR
  63 #undef CONFIG_MCFPIT
  64
  65 /* I2C */
  66 #define CONFIG_SYS_I2C
  67 #define CONFIG_SYS_i2C_FSL
  68 #define CONFIG_SYS_FSL_I2C_SPEED        80000
  69 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
  70 #define CONFIG_SYS_FSL_I2C_OFFSET       0x00000300
  71 #define CONFIG_SYS_IMMR         CONFIG_SYS_MBAR
  72 #define CONFIG_SYS_I2C_PINMUX_REG       (gpio->par_qspi)
  73 #define CONFIG_SYS_I2C_PINMUX_CLR       ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK)
  74 #define CONFIG_SYS_I2C_PINMUX_SET       (GPIO_PAR_FECI2C_SCL_I2CSCL | GPIO_PAR_FECI2C_SDA_I2CSDA)
  75
  76 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  77 #define CONFIG_BOOTFILE         "u-boot.bin"
  78 #ifdef CONFIG_MCFFEC
  79 #       define CONFIG_IPADDR    192.162.1.2
  80 #       define CONFIG_NETMASK   255.255.255.0
  81 #       define CONFIG_SERVERIP  192.162.1.1
  82 #       define CONFIG_GATEWAYIP 192.162.1.1
  83 #endif                          /* FEC_ENET */
  84
  85 #define CONFIG_HOSTNAME         M5235EVB
  86 #define CONFIG_EXTRA_ENV_SETTINGS               \
  87         "netdev=eth0\0"                         \
  88         "loadaddr=10000\0"                      \
  89         "u-boot=u-boot.bin\0"                   \
  90         "load=tftp ${loadaddr) ${u-boot}\0"     \
  91         "upd=run load; run prog\0"              \
  92         "prog=prot off ffe00000 ffe3ffff;"      \
  93         "era ffe00000 ffe3ffff;"                \
  94         "cp.b ${loadaddr} ffe00000 ${filesize};"\
  95         "save\0"                                \
  96         ""
  97
  98 #define CONFIG_PRAM             512     /* 512 KB */
  99 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 100
 101 #if defined(CONFIG_KGDB)
 102 #       define CONFIG_SYS_CBSIZE                1024    /* Console I/O Buffer Size */
 103 #else
 104 #       define CONFIG_SYS_CBSIZE                256     /* Console I/O Buffer Size */
 105 #endif
 106
 107 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)        /* Print Buffer Size */
 108 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 109 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 110 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE+0x20000)
 111
 112 #define CONFIG_SYS_CLK                  75000000
 113 #define CONFIG_SYS_CPU_CLK              CONFIG_SYS_CLK * 2
 114
 115 #define CONFIG_SYS_MBAR         0x40000000
 116
 117 /*
 118  * Low Level Configuration Settings
 119  * (address mappings, register initial values, etc.)
 120  * You should know what you are doing if you make changes here.
 121  */
 122 /*-----------------------------------------------------------------------
 123  * Definitions for initial stack pointer and data area (in DPRAM)
 124  */
 125 #define CONFIG_SYS_INIT_RAM_ADDR        0x20000000
 126 #define CONFIG_SYS_INIT_RAM_SIZE        0x10000 /* Size of used area in internal SRAM */
 127 #define CONFIG_SYS_INIT_RAM_CTRL        0x21
 128 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10)
 129 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 130
 131 /*-----------------------------------------------------------------------
 132  * Start addresses for the final memory configuration
 133  * (Set up by the startup code)
 134  * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 135  */
 136 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 137 #define CONFIG_SYS_SDRAM_SIZE           16      /* SDRAM size in MB */
 138
 139 #define CONFIG_SYS_MEMTEST_START        CONFIG_SYS_SDRAM_BASE + 0x400
 140 #define CONFIG_SYS_MEMTEST_END          ((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 141
 142 #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE + 0x400)
 143 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor */
 144
 145 #define CONFIG_SYS_BOOTPARAMS_LEN       64*1024
 146 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc() */
 147
 148 /*
 149  * For booting Linux, the board info and command line data
 150  * have to be in the first 8 MB of memory, since this is
 151  * the maximum mapped by the Linux kernel during initialization ??
 152  */
 153 /* Initial Memory map for Linux */
 154 #define CONFIG_SYS_BOOTMAPSZ            (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
 155 #define CONFIG_SYS_BOOTM_LEN            (CONFIG_SYS_SDRAM_SIZE << 20)
 156
 157 /*-----------------------------------------------------------------------
 158  * FLASH organization
 159  */
 160 #define CONFIG_SYS_FLASH_CFI
 161 #ifdef CONFIG_SYS_FLASH_CFI
 162 #       define CONFIG_FLASH_CFI_DRIVER  1
 163 #       define CONFIG_SYS_FLASH_SIZE            0x800000        /* Max size that the board might have */
 164 #ifdef NORFLASH_PS32BIT
 165 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_32BIT
 166 #else
 167 #       define CONFIG_SYS_FLASH_CFI_WIDTH       FLASH_CFI_16BIT
 168 #endif
 169 #       define CONFIG_SYS_MAX_FLASH_BANKS       1       /* max number of memory banks */
 170 #       define CONFIG_SYS_MAX_FLASH_SECT        137     /* max number of sectors on one chip */
 171 #       define CONFIG_SYS_FLASH_PROTECTION      /* "Real" (hardware) sectors protection */
 172 #endif
 173
 174 #define CONFIG_SYS_FLASH_BASE           (CONFIG_SYS_CS0_BASE)
 175
 176 /* Configuration for environment
 177  * Environment is embedded in u-boot in the second sector of the flash
 178  */
 179
 180 #define LDS_BOARD_TEXT \
 181         . = DEFINED(env_offset) ? env_offset : .; \
 182         common/env_embedded.o (.text);
 183
 184 #ifdef NORFLASH_PS32BIT
 185 #       define CONFIG_ENV_OFFSET                (0x8000)
 186 #       define CONFIG_ENV_SIZE          0x4000
 187 #       define CONFIG_ENV_SECT_SIZE     0x4000
 188 #else
 189 #       define CONFIG_ENV_OFFSET                (0x4000)
 190 #       define CONFIG_ENV_SIZE          0x2000
 191 #       define CONFIG_ENV_SECT_SIZE     0x2000
 192 #endif
 193
 194 /*-----------------------------------------------------------------------
 195  * Cache Configuration
 196  */
 197 #define CONFIG_SYS_CACHELINE_SIZE       16
 198
 199 #define ICACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 200                                          CONFIG_SYS_INIT_RAM_SIZE - 8)
 201 #define DCACHE_STATUS                   (CONFIG_SYS_INIT_RAM_ADDR + \
 202                                          CONFIG_SYS_INIT_RAM_SIZE - 4)
 203 #define CONFIG_SYS_ICACHE_INV           (CF_CACR_CINV)
 204 #define CONFIG_SYS_CACHE_ACR0           (CONFIG_SYS_SDRAM_BASE | \
 205                                          CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \
 206                                          CF_ACR_EN | CF_ACR_SM_ALL)
 207 #define CONFIG_SYS_CACHE_ICACR          (CF_CACR_CENB | CF_CACR_DISD | \
 208                                          CF_CACR_CEIB | CF_CACR_DCM | \
 209                                          CF_CACR_EUSP)
 210
 211 /*-----------------------------------------------------------------------
 212  * Chipselect bank definitions
 213  */
 214 /*
 215  * CS0 - NOR Flash 1, 2, 4, or 8MB
 216  * CS1 - Available
 217  * CS2 - Available
 218  * CS3 - Available
 219  * CS4 - Available
 220  * CS5 - Available
 221  * CS6 - Available
 222  * CS7 - Available
 223  */
 224 #ifdef NORFLASH_PS32BIT
 225 #       define CONFIG_SYS_CS0_BASE      0xFFC00000
 226 #       define CONFIG_SYS_CS0_MASK      0x003f0001
 227 #       define CONFIG_SYS_CS0_CTRL      0x00001D00
 228 #else
 229 #       define CONFIG_SYS_CS0_BASE      0xFFE00000
 230 #       define CONFIG_SYS_CS0_MASK      0x001f0001
 231 #       define CONFIG_SYS_CS0_CTRL      0x00001D80
 232 #endif
 233
 234 #endif                          /* _M5329EVB_H */